1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pmuv3.h> 34 #include <lib/extensions/sme.h> 35 #include <lib/extensions/spe.h> 36 #include <lib/extensions/sve.h> 37 #include <lib/extensions/sysreg128.h> 38 #include <lib/extensions/sys_reg_trace.h> 39 #include <lib/extensions/tcr2.h> 40 #include <lib/extensions/trbe.h> 41 #include <lib/extensions/trf.h> 42 #include <lib/utils.h> 43 44 #if ENABLE_FEAT_TWED 45 /* Make sure delay value fits within the range(0-15) */ 46 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 47 #endif /* ENABLE_FEAT_TWED */ 48 49 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 50 static bool has_secure_perworld_init; 51 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 static void manage_extensions_secure_per_world(void); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 153 /** 154 * manage_extensions_secure_per_world api has to be executed once, 155 * as the registers getting initialised, maintain constant value across 156 * all the cpus for the secure world. 157 * Henceforth, this check ensures that the registers are initialised once 158 * and avoids re-initialization from multiple cores. 159 */ 160 if (!has_secure_perworld_init) { 161 manage_extensions_secure_per_world(); 162 } 163 } 164 165 #if ENABLE_RME 166 /****************************************************************************** 167 * This function performs initializations that are specific to REALM state 168 * and updates the cpu context specified by 'ctx'. 169 *****************************************************************************/ 170 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 171 { 172 u_register_t scr_el3; 173 el3_state_t *state; 174 175 state = get_el3state_ctx(ctx); 176 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 177 178 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 179 180 /* CSV2 version 2 and above */ 181 if (is_feat_csv2_2_supported()) { 182 /* Enable access to the SCXTNUM_ELx registers. */ 183 scr_el3 |= SCR_EnSCXT_BIT; 184 } 185 186 if (is_feat_sctlr2_supported()) { 187 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 188 * SCTLR2_ELx registers. 189 */ 190 scr_el3 |= SCR_SCTLR2En_BIT; 191 } 192 193 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 194 195 if (is_feat_fgt2_supported()) { 196 fgt2_enable(ctx); 197 } 198 199 if (is_feat_debugv8p9_supported()) { 200 debugv8p9_extended_bp_wp_enable(ctx); 201 } 202 203 if (is_feat_brbe_supported()) { 204 brbe_enable(ctx); 205 } 206 207 } 208 #endif /* ENABLE_RME */ 209 210 /****************************************************************************** 211 * This function performs initializations that are specific to NON-SECURE state 212 * and updates the cpu context specified by 'ctx'. 213 *****************************************************************************/ 214 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 215 { 216 u_register_t scr_el3; 217 el3_state_t *state; 218 219 state = get_el3state_ctx(ctx); 220 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 221 222 /* SCR_NS: Set the NS bit */ 223 scr_el3 |= SCR_NS_BIT; 224 225 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 226 if (is_feat_mte2_supported()) { 227 scr_el3 |= SCR_ATA_BIT; 228 } 229 230 /* 231 * Pointer Authentication feature, if present, is always enabled by 232 * default for Non secure lower exception levels. We do not have an 233 * explicit flag to set it. To prevent the leakage between the worlds 234 * during world switch, we enable it only for the non-secure world. 235 * 236 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 237 * exception levels of secure and realm worlds. 238 * 239 * If the Secure/realm world wants to use pointer authentication, 240 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 241 * it will be enabled globally for all the contexts. 242 * 243 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 244 * other than EL3 245 * 246 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 247 * than EL3 248 */ 249 if (!is_ctx_pauth_supported()) { 250 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 251 } 252 253 #if HANDLE_EA_EL3_FIRST_NS 254 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 255 scr_el3 |= SCR_EA_BIT; 256 #endif 257 258 #if RAS_TRAP_NS_ERR_REC_ACCESS 259 /* 260 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 261 * and RAS ERX registers from EL1 and EL2(from any security state) 262 * are trapped to EL3. 263 * Set here to trap only for NS EL1/EL2 264 */ 265 scr_el3 |= SCR_TERR_BIT; 266 #endif 267 268 /* CSV2 version 2 and above */ 269 if (is_feat_csv2_2_supported()) { 270 /* Enable access to the SCXTNUM_ELx registers. */ 271 scr_el3 |= SCR_EnSCXT_BIT; 272 } 273 274 #ifdef IMAGE_BL31 275 /* 276 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 277 * indicated by the interrupt routing model for BL31. 278 */ 279 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 280 #endif 281 282 if (is_feat_the_supported()) { 283 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 284 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 285 */ 286 scr_el3 |= SCR_RCWMASKEn_BIT; 287 } 288 289 if (is_feat_sctlr2_supported()) { 290 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 291 * SCTLR2_ELx registers. 292 */ 293 scr_el3 |= SCR_SCTLR2En_BIT; 294 } 295 296 if (is_feat_d128_supported()) { 297 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 298 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 299 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 300 */ 301 scr_el3 |= SCR_D128En_BIT; 302 } 303 304 if (is_feat_fpmr_supported()) { 305 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 306 * register. 307 */ 308 scr_el3 |= SCR_EnFPM_BIT; 309 } 310 311 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 312 313 /* Initialize EL2 context registers */ 314 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 315 316 /* 317 * Initialize SCTLR_EL2 context register with reset value. 318 */ 319 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 320 321 if (is_feat_hcx_supported()) { 322 /* 323 * Initialize register HCRX_EL2 with its init value. 324 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 325 * chance that this can lead to unexpected behavior in lower 326 * ELs that have not been updated since the introduction of 327 * this feature if not properly initialized, especially when 328 * it comes to those bits that enable/disable traps. 329 */ 330 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 331 HCRX_EL2_INIT_VAL); 332 } 333 334 if (is_feat_fgt_supported()) { 335 /* 336 * Initialize HFG*_EL2 registers with a default value so legacy 337 * systems unaware of FEAT_FGT do not get trapped due to their lack 338 * of initialization for this feature. 339 */ 340 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 341 HFGITR_EL2_INIT_VAL); 342 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 343 HFGRTR_EL2_INIT_VAL); 344 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 345 HFGWTR_EL2_INIT_VAL); 346 } 347 #else 348 /* Initialize EL1 context registers */ 349 setup_el1_context(ctx, ep); 350 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 351 352 manage_extensions_nonsecure(ctx); 353 } 354 355 /******************************************************************************* 356 * The following function performs initialization of the cpu_context 'ctx' 357 * for first use that is common to all security states, and sets the 358 * initial entrypoint state as specified by the entry_point_info structure. 359 * 360 * The EE and ST attributes are used to configure the endianness and secure 361 * timer availability for the new execution context. 362 ******************************************************************************/ 363 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 364 { 365 u_register_t scr_el3; 366 u_register_t mdcr_el3; 367 el3_state_t *state; 368 gp_regs_t *gp_regs; 369 370 state = get_el3state_ctx(ctx); 371 372 /* Clear any residual register values from the context */ 373 zeromem(ctx, sizeof(*ctx)); 374 375 /* 376 * The lower-EL context is zeroed so that no stale values leak to a world. 377 * It is assumed that an all-zero lower-EL context is good enough for it 378 * to boot correctly. However, there are very few registers where this 379 * is not true and some values need to be recreated. 380 */ 381 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 382 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 383 384 /* 385 * These bits are set in the gicv3 driver. Losing them (especially the 386 * SRE bit) is problematic for all worlds. Henceforth recreate them. 387 */ 388 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 389 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 390 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 391 392 /* 393 * The actlr_el2 register can be initialized in platform's reset handler 394 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 395 */ 396 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 397 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 398 399 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 400 scr_el3 = SCR_RESET_VAL; 401 402 /* 403 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 404 * EL2, EL1 and EL0 are not trapped to EL3. 405 * 406 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 407 * EL2, EL1 and EL0 are not trapped to EL3. 408 * 409 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 410 * both Security states and both Execution states. 411 * 412 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 413 * Non-secure memory. 414 */ 415 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 416 417 scr_el3 |= SCR_SIF_BIT; 418 419 /* 420 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 421 * Exception level as specified by SPSR. 422 */ 423 if (GET_RW(ep->spsr) == MODE_RW_64) { 424 scr_el3 |= SCR_RW_BIT; 425 } 426 427 /* 428 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 429 * Secure timer registers to EL3, from AArch64 state only, if specified 430 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 431 * bit always behaves as 1 (i.e. secure physical timer register access 432 * is not trapped) 433 */ 434 if (EP_GET_ST(ep->h.attr) != 0U) { 435 scr_el3 |= SCR_ST_BIT; 436 } 437 438 /* 439 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 440 * SCR_EL3.HXEn. 441 */ 442 if (is_feat_hcx_supported()) { 443 scr_el3 |= SCR_HXEn_BIT; 444 } 445 446 /* 447 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 448 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 449 * SCR_EL3.EnAS0. 450 */ 451 if (is_feat_ls64_accdata_supported()) { 452 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 453 } 454 455 /* 456 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 457 * registers are trapped to EL3. 458 */ 459 if (is_feat_rng_trap_supported()) { 460 scr_el3 |= SCR_TRNDR_BIT; 461 } 462 463 #if FAULT_INJECTION_SUPPORT 464 /* Enable fault injection from lower ELs */ 465 scr_el3 |= SCR_FIEN_BIT; 466 #endif 467 468 /* 469 * Enable Pointer Authentication globally for all the worlds. 470 * 471 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 472 * other than EL3 473 * 474 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 475 * than EL3 476 */ 477 if (is_ctx_pauth_supported()) { 478 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 479 } 480 481 /* 482 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 483 */ 484 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 485 scr_el3 |= SCR_TCR2EN_BIT; 486 } 487 488 /* 489 * SCR_EL3.PIEN: Enable permission indirection and overlay 490 * registers for AArch64 if present. 491 */ 492 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 493 scr_el3 |= SCR_PIEN_BIT; 494 } 495 496 /* 497 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 498 */ 499 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 500 scr_el3 |= SCR_GCSEn_BIT; 501 } 502 503 /* 504 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 505 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 506 * next mode is Hyp. 507 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 508 * same conditions as HVC instructions and when the processor supports 509 * ARMv8.6-FGT. 510 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 511 * CNTPOFF_EL2 register under the same conditions as HVC instructions 512 * and when the processor supports ECV. 513 */ 514 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 515 || ((GET_RW(ep->spsr) != MODE_RW_64) 516 && (GET_M32(ep->spsr) == MODE32_hyp))) { 517 scr_el3 |= SCR_HCE_BIT; 518 519 if (is_feat_fgt_supported()) { 520 scr_el3 |= SCR_FGTEN_BIT; 521 } 522 523 if (is_feat_ecv_supported()) { 524 scr_el3 |= SCR_ECVEN_BIT; 525 } 526 } 527 528 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 529 if (is_feat_twed_supported()) { 530 /* Set delay in SCR_EL3 */ 531 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 532 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 533 << SCR_TWEDEL_SHIFT); 534 535 /* Enable WFE delay */ 536 scr_el3 |= SCR_TWEDEn_BIT; 537 } 538 539 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 540 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 541 if (is_feat_sel2_supported()) { 542 scr_el3 |= SCR_EEL2_BIT; 543 } 544 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 545 546 if (is_feat_mec_supported()) { 547 scr_el3 |= SCR_MECEn_BIT; 548 } 549 550 /* 551 * Populate EL3 state so that we've the right context 552 * before doing ERET 553 */ 554 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 555 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 556 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 557 558 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 559 mdcr_el3 = MDCR_EL3_RESET_VAL; 560 561 /* --------------------------------------------------------------------- 562 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 563 * Some fields are architecturally UNKNOWN on reset. 564 * 565 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 566 * Debug exceptions, other than Breakpoint Instruction exceptions, are 567 * disabled from all ELs in Secure state. 568 * 569 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 570 * privileged debug from S-EL1. 571 * 572 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 573 * access to the powerdown debug registers do not trap to EL3. 574 * 575 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 576 * debug registers, other than those registers that are controlled by 577 * MDCR_EL3.TDOSA. 578 */ 579 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 580 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 581 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 582 583 #if IMAGE_BL31 584 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 585 if (is_feat_trf_supported()) { 586 trf_enable(ctx); 587 } 588 589 pmuv3_enable(ctx); 590 #endif /* IMAGE_BL31 */ 591 592 /* 593 * Store the X0-X7 value from the entrypoint into the context 594 * Use memcpy as we are in control of the layout of the structures 595 */ 596 gp_regs = get_gpregs_ctx(ctx); 597 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 598 } 599 600 /******************************************************************************* 601 * Context management library initialization routine. This library is used by 602 * runtime services to share pointers to 'cpu_context' structures for secure 603 * non-secure and realm states. Management of the structures and their associated 604 * memory is not done by the context management library e.g. the PSCI service 605 * manages the cpu context used for entry from and exit to the non-secure state. 606 * The Secure payload dispatcher service manages the context(s) corresponding to 607 * the secure state. It also uses this library to get access to the non-secure 608 * state cpu context pointers. 609 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 610 * which will be used for programming an entry into a lower EL. The same context 611 * will be used to save state upon exception entry from that EL. 612 ******************************************************************************/ 613 void __init cm_init(void) 614 { 615 /* 616 * The context management library has only global data to initialize, but 617 * that will be done when the BSS is zeroed out. 618 */ 619 } 620 621 /******************************************************************************* 622 * This is the high-level function used to initialize the cpu_context 'ctx' for 623 * first use. It performs initializations that are common to all security states 624 * and initializations specific to the security state specified in 'ep' 625 ******************************************************************************/ 626 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 627 { 628 unsigned int security_state; 629 630 assert(ctx != NULL); 631 632 /* 633 * Perform initializations that are common 634 * to all security states 635 */ 636 setup_context_common(ctx, ep); 637 638 security_state = GET_SECURITY_STATE(ep->h.attr); 639 640 /* Perform security state specific initializations */ 641 switch (security_state) { 642 case SECURE: 643 setup_secure_context(ctx, ep); 644 break; 645 #if ENABLE_RME 646 case REALM: 647 setup_realm_context(ctx, ep); 648 break; 649 #endif 650 case NON_SECURE: 651 setup_ns_context(ctx, ep); 652 break; 653 default: 654 ERROR("Invalid security state\n"); 655 panic(); 656 break; 657 } 658 } 659 660 /******************************************************************************* 661 * Enable architecture extensions for EL3 execution. This function only updates 662 * registers in-place which are expected to either never change or be 663 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 664 ******************************************************************************/ 665 #if IMAGE_BL31 666 void cm_manage_extensions_el3(unsigned int my_idx) 667 { 668 if (is_feat_sve_supported()) { 669 sve_init_el3(); 670 } 671 672 if (is_feat_amu_supported()) { 673 amu_init_el3(my_idx); 674 } 675 676 if (is_feat_sme_supported()) { 677 sme_init_el3(); 678 } 679 680 pmuv3_init_el3(); 681 } 682 #endif /* IMAGE_BL31 */ 683 684 /****************************************************************************** 685 * Function to initialise the registers with the RESET values in the context 686 * memory, which are maintained per world. 687 ******************************************************************************/ 688 #if IMAGE_BL31 689 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 690 { 691 /* 692 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 693 * 694 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 695 * by Advanced SIMD, floating-point or SVE instructions (if 696 * implemented) do not trap to EL3. 697 * 698 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 699 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 700 */ 701 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 702 703 per_world_ctx->ctx_cptr_el3 = cptr_el3; 704 705 /* 706 * Initialize MPAM3_EL3 to its default reset value 707 * 708 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 709 * all lower ELn MPAM3_EL3 register access to, trap to EL3 710 */ 711 712 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 713 } 714 #endif /* IMAGE_BL31 */ 715 716 /******************************************************************************* 717 * Initialise per_world_context for Non-Secure world. 718 * This function enables the architecture extensions, which have same value 719 * across the cores for the non-secure world. 720 ******************************************************************************/ 721 #if IMAGE_BL31 722 void manage_extensions_nonsecure_per_world(void) 723 { 724 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 725 726 if (is_feat_sme_supported()) { 727 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 728 } 729 730 if (is_feat_sve_supported()) { 731 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 732 } 733 734 if (is_feat_amu_supported()) { 735 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 736 } 737 738 if (is_feat_sys_reg_trace_supported()) { 739 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 740 } 741 742 if (is_feat_mpam_supported()) { 743 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 744 } 745 746 if (is_feat_fpmr_supported()) { 747 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 748 } 749 } 750 #endif /* IMAGE_BL31 */ 751 752 /******************************************************************************* 753 * Initialise per_world_context for Secure world. 754 * This function enables the architecture extensions, which have same value 755 * across the cores for the secure world. 756 ******************************************************************************/ 757 static void manage_extensions_secure_per_world(void) 758 { 759 #if IMAGE_BL31 760 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 761 762 if (is_feat_sme_supported()) { 763 764 if (ENABLE_SME_FOR_SWD) { 765 /* 766 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 767 * SME, SVE, and FPU/SIMD context properly managed. 768 */ 769 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 770 } else { 771 /* 772 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 773 * world can safely use the associated registers. 774 */ 775 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 776 } 777 } 778 if (is_feat_sve_supported()) { 779 if (ENABLE_SVE_FOR_SWD) { 780 /* 781 * Enable SVE and FPU in secure context, SPM must ensure 782 * that the SVE and FPU register contexts are properly managed. 783 */ 784 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 785 } else { 786 /* 787 * Disable SVE and FPU in secure context so non-secure world 788 * can safely use them. 789 */ 790 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 791 } 792 } 793 794 /* NS can access this but Secure shouldn't */ 795 if (is_feat_sys_reg_trace_supported()) { 796 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 797 } 798 799 has_secure_perworld_init = true; 800 #endif /* IMAGE_BL31 */ 801 } 802 803 /******************************************************************************* 804 * Enable architecture extensions on first entry to Non-secure world. 805 ******************************************************************************/ 806 static void manage_extensions_nonsecure(cpu_context_t *ctx) 807 { 808 #if IMAGE_BL31 809 /* NOTE: registers are not context switched */ 810 if (is_feat_amu_supported()) { 811 amu_enable(ctx); 812 } 813 814 if (is_feat_sme_supported()) { 815 sme_enable(ctx); 816 } 817 818 if (is_feat_fgt2_supported()) { 819 fgt2_enable(ctx); 820 } 821 822 if (is_feat_debugv8p9_supported()) { 823 debugv8p9_extended_bp_wp_enable(ctx); 824 } 825 826 /* 827 * SPE, TRBE, and BRBE have multi-field enables that affect which world 828 * they apply to. Despite this, it is useful to ignore these for 829 * simplicity in determining the feature's per world enablement status. 830 * This is only possible when context is written per-world. Relied on 831 * by SMCCC_ARCH_FEATURE_AVAILABILITY 832 */ 833 if (is_feat_spe_supported()) { 834 spe_enable(ctx); 835 } 836 837 if (is_feat_trbe_supported()) { 838 trbe_enable(ctx); 839 } 840 841 if (is_feat_brbe_supported()) { 842 brbe_enable(ctx); 843 } 844 #endif /* IMAGE_BL31 */ 845 } 846 847 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 848 static __unused void enable_pauth_el2(void) 849 { 850 u_register_t hcr_el2 = read_hcr_el2(); 851 /* 852 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 853 * accessing key registers or using pointer authentication instructions 854 * from lower ELs. 855 */ 856 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 857 858 write_hcr_el2(hcr_el2); 859 } 860 861 #if INIT_UNUSED_NS_EL2 862 /******************************************************************************* 863 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 864 * world when EL2 is empty and unused. 865 ******************************************************************************/ 866 static void manage_extensions_nonsecure_el2_unused(void) 867 { 868 #if IMAGE_BL31 869 if (is_feat_spe_supported()) { 870 spe_init_el2_unused(); 871 } 872 873 if (is_feat_amu_supported()) { 874 amu_init_el2_unused(); 875 } 876 877 if (is_feat_mpam_supported()) { 878 mpam_init_el2_unused(); 879 } 880 881 if (is_feat_trbe_supported()) { 882 trbe_init_el2_unused(); 883 } 884 885 if (is_feat_sys_reg_trace_supported()) { 886 sys_reg_trace_init_el2_unused(); 887 } 888 889 if (is_feat_trf_supported()) { 890 trf_init_el2_unused(); 891 } 892 893 pmuv3_init_el2_unused(); 894 895 if (is_feat_sve_supported()) { 896 sve_init_el2_unused(); 897 } 898 899 if (is_feat_sme_supported()) { 900 sme_init_el2_unused(); 901 } 902 903 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 904 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 905 } 906 907 #if ENABLE_PAUTH 908 enable_pauth_el2(); 909 #endif /* ENABLE_PAUTH */ 910 #endif /* IMAGE_BL31 */ 911 } 912 #endif /* INIT_UNUSED_NS_EL2 */ 913 914 /******************************************************************************* 915 * Enable architecture extensions on first entry to Secure world. 916 ******************************************************************************/ 917 static void manage_extensions_secure(cpu_context_t *ctx) 918 { 919 #if IMAGE_BL31 920 if (is_feat_sme_supported()) { 921 if (ENABLE_SME_FOR_SWD) { 922 /* 923 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 924 * must ensure SME, SVE, and FPU/SIMD context properly managed. 925 */ 926 sme_init_el3(); 927 sme_enable(ctx); 928 } else { 929 /* 930 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 931 * world can safely use the associated registers. 932 */ 933 sme_disable(ctx); 934 } 935 } 936 937 /* 938 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 939 * sysreg access can. In case the EL1 controls leave them active on 940 * context switch, we want the owning security state to be NS so Secure 941 * can't be DOSed. 942 */ 943 if (is_feat_spe_supported()) { 944 spe_disable(ctx); 945 } 946 947 if (is_feat_trbe_supported()) { 948 trbe_disable(ctx); 949 } 950 #endif /* IMAGE_BL31 */ 951 } 952 953 #if !IMAGE_BL1 954 /******************************************************************************* 955 * The following function initializes the cpu_context for a CPU specified by 956 * its `cpu_idx` for first use, and sets the initial entrypoint state as 957 * specified by the entry_point_info structure. 958 ******************************************************************************/ 959 void cm_init_context_by_index(unsigned int cpu_idx, 960 const entry_point_info_t *ep) 961 { 962 cpu_context_t *ctx; 963 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 964 cm_setup_context(ctx, ep); 965 } 966 #endif /* !IMAGE_BL1 */ 967 968 /******************************************************************************* 969 * The following function initializes the cpu_context for the current CPU 970 * for first use, and sets the initial entrypoint state as specified by the 971 * entry_point_info structure. 972 ******************************************************************************/ 973 void cm_init_my_context(const entry_point_info_t *ep) 974 { 975 cpu_context_t *ctx; 976 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 977 cm_setup_context(ctx, ep); 978 } 979 980 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 981 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 982 { 983 #if INIT_UNUSED_NS_EL2 984 u_register_t hcr_el2 = HCR_RESET_VAL; 985 u_register_t mdcr_el2; 986 u_register_t scr_el3; 987 988 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 989 990 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 991 if ((scr_el3 & SCR_RW_BIT) != 0U) { 992 hcr_el2 |= HCR_RW_BIT; 993 } 994 995 write_hcr_el2(hcr_el2); 996 997 /* 998 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 999 * All fields have architecturally UNKNOWN reset values. 1000 */ 1001 write_cptr_el2(CPTR_EL2_RESET_VAL); 1002 1003 /* 1004 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1005 * reset and are set to zero except for field(s) listed below. 1006 * 1007 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1008 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1009 * 1010 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1011 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1012 */ 1013 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1014 1015 /* 1016 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1017 * UNKNOWN value. 1018 */ 1019 write_cntvoff_el2(0); 1020 1021 /* 1022 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1023 * respectively. 1024 */ 1025 write_vpidr_el2(read_midr_el1()); 1026 write_vmpidr_el2(read_mpidr_el1()); 1027 1028 /* 1029 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1030 * 1031 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1032 * translation is disabled, cache maintenance operations depend on the 1033 * VMID. 1034 * 1035 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1036 * disabled. 1037 */ 1038 write_vttbr_el2(VTTBR_RESET_VAL & 1039 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1040 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1041 1042 /* 1043 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1044 * Some fields are architecturally UNKNOWN on reset. 1045 * 1046 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1047 * register accesses to the Debug ROM registers are not trapped to EL2. 1048 * 1049 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1050 * accesses to the powerdown debug registers are not trapped to EL2. 1051 * 1052 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1053 * debug registers do not trap to EL2. 1054 * 1055 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1056 * EL2. 1057 */ 1058 mdcr_el2 = MDCR_EL2_RESET_VAL & 1059 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1060 MDCR_EL2_TDE_BIT); 1061 1062 write_mdcr_el2(mdcr_el2); 1063 1064 /* 1065 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1066 * 1067 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1068 * EL1 accesses to System registers do not trap to EL2. 1069 */ 1070 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1071 1072 /* 1073 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1074 * reset. 1075 * 1076 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1077 * and prevent timer interrupts. 1078 */ 1079 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1080 1081 manage_extensions_nonsecure_el2_unused(); 1082 #endif /* INIT_UNUSED_NS_EL2 */ 1083 } 1084 1085 /******************************************************************************* 1086 * Prepare the CPU system registers for first entry into realm, secure, or 1087 * normal world. 1088 * 1089 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1090 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1091 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1092 * For all entries, the EL1 registers are initialized from the cpu_context 1093 ******************************************************************************/ 1094 void cm_prepare_el3_exit(uint32_t security_state) 1095 { 1096 u_register_t sctlr_el2, scr_el3; 1097 cpu_context_t *ctx = cm_get_context(security_state); 1098 1099 assert(ctx != NULL); 1100 1101 if (security_state == NON_SECURE) { 1102 uint64_t el2_implemented = el_implemented(2); 1103 1104 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1105 CTX_SCR_EL3); 1106 1107 if (el2_implemented != EL_IMPL_NONE) { 1108 1109 /* 1110 * If context is not being used for EL2, initialize 1111 * HCRX_EL2 with its init value here. 1112 */ 1113 if (is_feat_hcx_supported()) { 1114 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1115 } 1116 1117 /* 1118 * Initialize Fine-grained trap registers introduced 1119 * by FEAT_FGT so all traps are initially disabled when 1120 * switching to EL2 or a lower EL, preventing undesired 1121 * behavior. 1122 */ 1123 if (is_feat_fgt_supported()) { 1124 /* 1125 * Initialize HFG*_EL2 registers with a default 1126 * value so legacy systems unaware of FEAT_FGT 1127 * do not get trapped due to their lack of 1128 * initialization for this feature. 1129 */ 1130 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1131 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1132 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1133 } 1134 1135 /* Condition to ensure EL2 is being used. */ 1136 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1137 /* Initialize SCTLR_EL2 register with reset value. */ 1138 sctlr_el2 = SCTLR_EL2_RES1; 1139 1140 /* 1141 * If workaround of errata 764081 for Cortex-A75 1142 * is used then set SCTLR_EL2.IESB to enable 1143 * Implicit Error Synchronization Barrier. 1144 */ 1145 if (errata_a75_764081_applies()) { 1146 sctlr_el2 |= SCTLR_IESB_BIT; 1147 } 1148 1149 write_sctlr_el2(sctlr_el2); 1150 } else { 1151 /* 1152 * (scr_el3 & SCR_HCE_BIT==0) 1153 * EL2 implemented but unused. 1154 */ 1155 init_nonsecure_el2_unused(ctx); 1156 } 1157 } 1158 } 1159 #if (!CTX_INCLUDE_EL2_REGS) 1160 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1161 cm_el1_sysregs_context_restore(security_state); 1162 #endif 1163 cm_set_next_eret_context(security_state); 1164 } 1165 1166 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1167 1168 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1169 { 1170 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1171 if (is_feat_amu_supported()) { 1172 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1173 } 1174 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1175 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1176 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1177 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1178 } 1179 1180 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1181 { 1182 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1183 if (is_feat_amu_supported()) { 1184 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1185 } 1186 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1187 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1188 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1189 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1190 } 1191 1192 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1193 { 1194 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1195 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1196 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1197 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1198 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1199 } 1200 1201 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1202 { 1203 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1204 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1205 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1206 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1207 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1208 } 1209 1210 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1211 { 1212 u_register_t mpam_idr = read_mpamidr_el1(); 1213 1214 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1215 1216 /* 1217 * The context registers that we intend to save would be part of the 1218 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1219 */ 1220 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1221 return; 1222 } 1223 1224 /* 1225 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1226 * MPAMIDR_HAS_HCR_BIT == 1. 1227 */ 1228 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1229 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1230 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1231 1232 /* 1233 * The number of MPAMVPM registers is implementation defined, their 1234 * number is stored in the MPAMIDR_EL1 register. 1235 */ 1236 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1237 case 7: 1238 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1239 __fallthrough; 1240 case 6: 1241 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1242 __fallthrough; 1243 case 5: 1244 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1245 __fallthrough; 1246 case 4: 1247 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1248 __fallthrough; 1249 case 3: 1250 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1251 __fallthrough; 1252 case 2: 1253 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1254 __fallthrough; 1255 case 1: 1256 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1257 break; 1258 } 1259 } 1260 1261 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1262 { 1263 u_register_t mpam_idr = read_mpamidr_el1(); 1264 1265 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1266 1267 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1268 return; 1269 } 1270 1271 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1272 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1273 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1274 1275 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1276 case 7: 1277 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1278 __fallthrough; 1279 case 6: 1280 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1281 __fallthrough; 1282 case 5: 1283 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1284 __fallthrough; 1285 case 4: 1286 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1287 __fallthrough; 1288 case 3: 1289 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1290 __fallthrough; 1291 case 2: 1292 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1293 __fallthrough; 1294 case 1: 1295 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1296 break; 1297 } 1298 } 1299 1300 /* --------------------------------------------------------------------------- 1301 * The following registers are not added: 1302 * ICH_AP0R<n>_EL2 1303 * ICH_AP1R<n>_EL2 1304 * ICH_LR<n>_EL2 1305 * 1306 * NOTE: For a system with S-EL2 present but not enabled, accessing 1307 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1308 * SCR_EL3.NS = 1 before accessing this register. 1309 * --------------------------------------------------------------------------- 1310 */ 1311 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1312 { 1313 u_register_t scr_el3 = read_scr_el3(); 1314 1315 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1316 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1317 #else 1318 write_scr_el3(scr_el3 | SCR_NS_BIT); 1319 isb(); 1320 1321 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1322 1323 write_scr_el3(scr_el3); 1324 isb(); 1325 #endif 1326 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1327 1328 if (errata_ich_vmcr_el2_applies()) { 1329 if (security_state == SECURE) { 1330 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1331 } else { 1332 write_scr_el3(scr_el3 | SCR_NS_BIT); 1333 } 1334 isb(); 1335 } 1336 1337 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1338 1339 if (errata_ich_vmcr_el2_applies()) { 1340 write_scr_el3(scr_el3); 1341 isb(); 1342 } 1343 } 1344 1345 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1346 { 1347 u_register_t scr_el3 = read_scr_el3(); 1348 1349 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1350 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1351 #else 1352 write_scr_el3(scr_el3 | SCR_NS_BIT); 1353 isb(); 1354 1355 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1356 1357 write_scr_el3(scr_el3); 1358 isb(); 1359 #endif 1360 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1361 1362 if (errata_ich_vmcr_el2_applies()) { 1363 if (security_state == SECURE) { 1364 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1365 } else { 1366 write_scr_el3(scr_el3 | SCR_NS_BIT); 1367 } 1368 isb(); 1369 } 1370 1371 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1372 1373 if (errata_ich_vmcr_el2_applies()) { 1374 write_scr_el3(scr_el3); 1375 isb(); 1376 } 1377 } 1378 1379 /* ----------------------------------------------------- 1380 * The following registers are not added: 1381 * AMEVCNTVOFF0<n>_EL2 1382 * AMEVCNTVOFF1<n>_EL2 1383 * ----------------------------------------------------- 1384 */ 1385 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1386 { 1387 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1388 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1389 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1390 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1391 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1392 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1393 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1394 if (CTX_INCLUDE_AARCH32_REGS) { 1395 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1396 } 1397 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1398 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1399 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1400 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1401 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1402 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1403 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1404 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1405 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1406 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1407 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1408 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1409 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1410 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1411 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1412 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1413 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1414 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1415 1416 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1417 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1418 } 1419 1420 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1421 { 1422 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1423 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1424 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1425 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1426 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1427 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1428 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1429 if (CTX_INCLUDE_AARCH32_REGS) { 1430 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1431 } 1432 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1433 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1434 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1435 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1436 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1437 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1438 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1439 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1440 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1441 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1442 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1443 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1444 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1445 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1446 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1447 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1448 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1449 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1450 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1451 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1452 } 1453 1454 /******************************************************************************* 1455 * Save EL2 sysreg context 1456 ******************************************************************************/ 1457 void cm_el2_sysregs_context_save(uint32_t security_state) 1458 { 1459 cpu_context_t *ctx; 1460 el2_sysregs_t *el2_sysregs_ctx; 1461 1462 ctx = cm_get_context(security_state); 1463 assert(ctx != NULL); 1464 1465 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1466 1467 el2_sysregs_context_save_common(el2_sysregs_ctx); 1468 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1469 1470 if (is_feat_mte2_supported()) { 1471 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1472 } 1473 1474 if (is_feat_mpam_supported()) { 1475 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1476 } 1477 1478 if (is_feat_fgt_supported()) { 1479 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1480 } 1481 1482 if (is_feat_fgt2_supported()) { 1483 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1484 } 1485 1486 if (is_feat_ecv_v2_supported()) { 1487 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1488 } 1489 1490 if (is_feat_vhe_supported()) { 1491 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1492 read_contextidr_el2()); 1493 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1494 } 1495 1496 if (is_feat_ras_supported()) { 1497 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1498 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1499 } 1500 1501 if (is_feat_nv2_supported()) { 1502 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1503 } 1504 1505 if (is_feat_trf_supported()) { 1506 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1507 } 1508 1509 if (is_feat_csv2_2_supported()) { 1510 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1511 read_scxtnum_el2()); 1512 } 1513 1514 if (is_feat_hcx_supported()) { 1515 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1516 } 1517 1518 if (is_feat_tcr2_supported()) { 1519 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1520 } 1521 1522 if (is_feat_sxpie_supported()) { 1523 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1524 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1525 } 1526 1527 if (is_feat_sxpoe_supported()) { 1528 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1529 } 1530 1531 if (is_feat_brbe_supported()) { 1532 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1533 } 1534 1535 if (is_feat_s2pie_supported()) { 1536 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1537 } 1538 1539 if (is_feat_gcs_supported()) { 1540 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1541 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1542 } 1543 1544 if (is_feat_sctlr2_supported()) { 1545 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1546 } 1547 } 1548 1549 /******************************************************************************* 1550 * Restore EL2 sysreg context 1551 ******************************************************************************/ 1552 void cm_el2_sysregs_context_restore(uint32_t security_state) 1553 { 1554 cpu_context_t *ctx; 1555 el2_sysregs_t *el2_sysregs_ctx; 1556 1557 ctx = cm_get_context(security_state); 1558 assert(ctx != NULL); 1559 1560 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1561 1562 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1563 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1564 1565 if (is_feat_mte2_supported()) { 1566 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1567 } 1568 1569 if (is_feat_mpam_supported()) { 1570 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1571 } 1572 1573 if (is_feat_fgt_supported()) { 1574 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1575 } 1576 1577 if (is_feat_fgt2_supported()) { 1578 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1579 } 1580 1581 if (is_feat_ecv_v2_supported()) { 1582 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1583 } 1584 1585 if (is_feat_vhe_supported()) { 1586 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1587 contextidr_el2)); 1588 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1589 } 1590 1591 if (is_feat_ras_supported()) { 1592 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1593 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1594 } 1595 1596 if (is_feat_nv2_supported()) { 1597 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1598 } 1599 1600 if (is_feat_trf_supported()) { 1601 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1602 } 1603 1604 if (is_feat_csv2_2_supported()) { 1605 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1606 scxtnum_el2)); 1607 } 1608 1609 if (is_feat_hcx_supported()) { 1610 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1611 } 1612 1613 if (is_feat_tcr2_supported()) { 1614 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1615 } 1616 1617 if (is_feat_sxpie_supported()) { 1618 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1619 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1620 } 1621 1622 if (is_feat_sxpoe_supported()) { 1623 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1624 } 1625 1626 if (is_feat_s2pie_supported()) { 1627 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1628 } 1629 1630 if (is_feat_gcs_supported()) { 1631 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1632 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1633 } 1634 1635 if (is_feat_sctlr2_supported()) { 1636 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1637 } 1638 1639 if (is_feat_brbe_supported()) { 1640 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1641 } 1642 } 1643 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1644 1645 #if IMAGE_BL31 1646 /********************************************************************************* 1647 * This function allows Architecture features asymmetry among cores. 1648 * TF-A assumes that all the cores in the platform has architecture feature parity 1649 * and hence the context is setup on different core (e.g. primary sets up the 1650 * context for secondary cores).This assumption may not be true for systems where 1651 * cores are not conforming to same Arch version or there is CPU Erratum which 1652 * requires certain feature to be be disabled only on a given core. 1653 * 1654 * This function is called on secondary cores to override any disparity in context 1655 * setup by primary, this would be called during warmboot path. 1656 *********************************************************************************/ 1657 void cm_handle_asymmetric_features(void) 1658 { 1659 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1660 1661 assert(ctx != NULL); 1662 1663 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1664 if (is_feat_spe_supported()) { 1665 spe_enable(ctx); 1666 } else { 1667 spe_disable(ctx); 1668 } 1669 #endif 1670 1671 if (check_if_trbe_disable_affected_core()) { 1672 if (is_feat_trbe_supported()) { 1673 trbe_disable(ctx); 1674 } 1675 } 1676 1677 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1678 el3_state_t *el3_state = get_el3state_ctx(ctx); 1679 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1680 1681 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1682 tcr2_enable(ctx); 1683 } else { 1684 tcr2_disable(ctx); 1685 } 1686 #endif 1687 1688 } 1689 #endif 1690 1691 /******************************************************************************* 1692 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1693 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1694 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1695 * cm_prepare_el3_exit function. 1696 ******************************************************************************/ 1697 void cm_prepare_el3_exit_ns(void) 1698 { 1699 #if IMAGE_BL31 1700 /* 1701 * Check and handle Architecture feature asymmetry among cores. 1702 * 1703 * In warmboot path secondary cores context is initialized on core which 1704 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1705 * it in this function call. 1706 * For Symmetric cores this is an empty function. 1707 */ 1708 cm_handle_asymmetric_features(); 1709 #endif 1710 1711 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1712 #if ENABLE_ASSERTIONS 1713 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1714 assert(ctx != NULL); 1715 1716 /* Assert that EL2 is used. */ 1717 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1718 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1719 (el_implemented(2U) != EL_IMPL_NONE)); 1720 #endif /* ENABLE_ASSERTIONS */ 1721 1722 /* Restore EL2 sysreg contexts */ 1723 cm_el2_sysregs_context_restore(NON_SECURE); 1724 cm_set_next_eret_context(NON_SECURE); 1725 #else 1726 cm_prepare_el3_exit(NON_SECURE); 1727 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1728 } 1729 1730 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1731 /******************************************************************************* 1732 * The next set of six functions are used by runtime services to save and restore 1733 * EL1 context on the 'cpu_context' structure for the specified security state. 1734 ******************************************************************************/ 1735 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1736 { 1737 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1738 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1739 1740 #if (!ERRATA_SPECULATIVE_AT) 1741 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1742 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1743 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1744 1745 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1746 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1747 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1748 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1749 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1750 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1751 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1752 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1753 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1754 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1755 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1756 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1757 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1758 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1759 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1760 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1761 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1762 1763 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1764 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1765 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1766 1767 if (CTX_INCLUDE_AARCH32_REGS) { 1768 /* Save Aarch32 registers */ 1769 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1770 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1771 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1772 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1773 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1774 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1775 } 1776 1777 if (NS_TIMER_SWITCH) { 1778 /* Save NS Timer registers */ 1779 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1780 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1781 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1782 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1783 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1784 } 1785 1786 if (is_feat_mte2_supported()) { 1787 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1788 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1789 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1790 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1791 } 1792 1793 if (is_feat_ras_supported()) { 1794 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1795 } 1796 1797 if (is_feat_s1pie_supported()) { 1798 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1799 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1800 } 1801 1802 if (is_feat_s1poe_supported()) { 1803 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1804 } 1805 1806 if (is_feat_s2poe_supported()) { 1807 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1808 } 1809 1810 if (is_feat_tcr2_supported()) { 1811 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1812 } 1813 1814 if (is_feat_trf_supported()) { 1815 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1816 } 1817 1818 if (is_feat_csv2_2_supported()) { 1819 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1820 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1821 } 1822 1823 if (is_feat_gcs_supported()) { 1824 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1825 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1826 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1827 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1828 } 1829 1830 if (is_feat_the_supported()) { 1831 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1832 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1833 } 1834 1835 if (is_feat_sctlr2_supported()) { 1836 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1837 } 1838 1839 if (is_feat_ls64_accdata_supported()) { 1840 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1841 } 1842 } 1843 1844 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1845 { 1846 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1847 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1848 1849 #if (!ERRATA_SPECULATIVE_AT) 1850 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1851 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1852 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1853 1854 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1855 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1856 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1857 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1858 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1859 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1860 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1861 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1862 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1863 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1864 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1865 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1866 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1867 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1868 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1869 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1870 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1871 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1872 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1873 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1874 1875 if (CTX_INCLUDE_AARCH32_REGS) { 1876 /* Restore Aarch32 registers */ 1877 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1878 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1879 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1880 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1881 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1882 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1883 } 1884 1885 if (NS_TIMER_SWITCH) { 1886 /* Restore NS Timer registers */ 1887 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1888 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1889 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1890 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1891 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1892 } 1893 1894 if (is_feat_mte2_supported()) { 1895 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1896 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1897 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1898 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1899 } 1900 1901 if (is_feat_ras_supported()) { 1902 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1903 } 1904 1905 if (is_feat_s1pie_supported()) { 1906 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1907 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1908 } 1909 1910 if (is_feat_s1poe_supported()) { 1911 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1912 } 1913 1914 if (is_feat_s2poe_supported()) { 1915 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1916 } 1917 1918 if (is_feat_tcr2_supported()) { 1919 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1920 } 1921 1922 if (is_feat_trf_supported()) { 1923 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1924 } 1925 1926 if (is_feat_csv2_2_supported()) { 1927 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1928 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1929 } 1930 1931 if (is_feat_gcs_supported()) { 1932 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1933 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1934 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1935 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1936 } 1937 1938 if (is_feat_the_supported()) { 1939 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1940 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1941 } 1942 1943 if (is_feat_sctlr2_supported()) { 1944 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1945 } 1946 1947 if (is_feat_ls64_accdata_supported()) { 1948 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1949 } 1950 } 1951 1952 /******************************************************************************* 1953 * The next couple of functions are used by runtime services to save and restore 1954 * EL1 context on the 'cpu_context' structure for the specified security state. 1955 ******************************************************************************/ 1956 void cm_el1_sysregs_context_save(uint32_t security_state) 1957 { 1958 cpu_context_t *ctx; 1959 1960 ctx = cm_get_context(security_state); 1961 assert(ctx != NULL); 1962 1963 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1964 1965 #if IMAGE_BL31 1966 if (security_state == SECURE) { 1967 PUBLISH_EVENT(cm_exited_secure_world); 1968 } else { 1969 PUBLISH_EVENT(cm_exited_normal_world); 1970 } 1971 #endif 1972 } 1973 1974 void cm_el1_sysregs_context_restore(uint32_t security_state) 1975 { 1976 cpu_context_t *ctx; 1977 1978 ctx = cm_get_context(security_state); 1979 assert(ctx != NULL); 1980 1981 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1982 1983 #if IMAGE_BL31 1984 if (security_state == SECURE) { 1985 PUBLISH_EVENT(cm_entering_secure_world); 1986 } else { 1987 PUBLISH_EVENT(cm_entering_normal_world); 1988 } 1989 #endif 1990 } 1991 1992 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1993 1994 /******************************************************************************* 1995 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1996 * given security state with the given entrypoint 1997 ******************************************************************************/ 1998 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1999 { 2000 cpu_context_t *ctx; 2001 el3_state_t *state; 2002 2003 ctx = cm_get_context(security_state); 2004 assert(ctx != NULL); 2005 2006 /* Populate EL3 state so that ERET jumps to the correct entry */ 2007 state = get_el3state_ctx(ctx); 2008 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2009 } 2010 2011 /******************************************************************************* 2012 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 2013 * pertaining to the given security state 2014 ******************************************************************************/ 2015 void cm_set_elr_spsr_el3(uint32_t security_state, 2016 uintptr_t entrypoint, uint32_t spsr) 2017 { 2018 cpu_context_t *ctx; 2019 el3_state_t *state; 2020 2021 ctx = cm_get_context(security_state); 2022 assert(ctx != NULL); 2023 2024 /* Populate EL3 state so that ERET jumps to the correct entry */ 2025 state = get_el3state_ctx(ctx); 2026 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2027 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2028 } 2029 2030 /******************************************************************************* 2031 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2032 * pertaining to the given security state using the value and bit position 2033 * specified in the parameters. It preserves all other bits. 2034 ******************************************************************************/ 2035 void cm_write_scr_el3_bit(uint32_t security_state, 2036 uint32_t bit_pos, 2037 uint32_t value) 2038 { 2039 cpu_context_t *ctx; 2040 el3_state_t *state; 2041 u_register_t scr_el3; 2042 2043 ctx = cm_get_context(security_state); 2044 assert(ctx != NULL); 2045 2046 /* Ensure that the bit position is a valid one */ 2047 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2048 2049 /* Ensure that the 'value' is only a bit wide */ 2050 assert(value <= 1U); 2051 2052 /* 2053 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2054 * and set it to its new value. 2055 */ 2056 state = get_el3state_ctx(ctx); 2057 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2058 scr_el3 &= ~(1UL << bit_pos); 2059 scr_el3 |= (u_register_t)value << bit_pos; 2060 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2061 } 2062 2063 /******************************************************************************* 2064 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2065 * given security state. 2066 ******************************************************************************/ 2067 u_register_t cm_get_scr_el3(uint32_t security_state) 2068 { 2069 const cpu_context_t *ctx; 2070 const el3_state_t *state; 2071 2072 ctx = cm_get_context(security_state); 2073 assert(ctx != NULL); 2074 2075 /* Populate EL3 state so that ERET jumps to the correct entry */ 2076 state = get_el3state_ctx(ctx); 2077 return read_ctx_reg(state, CTX_SCR_EL3); 2078 } 2079 2080 /******************************************************************************* 2081 * This function is used to program the context that's used for exception 2082 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2083 * the required security state 2084 ******************************************************************************/ 2085 void cm_set_next_eret_context(uint32_t security_state) 2086 { 2087 cpu_context_t *ctx; 2088 2089 ctx = cm_get_context(security_state); 2090 assert(ctx != NULL); 2091 2092 cm_set_next_context(ctx); 2093 } 2094