1 /* 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <drivers/arm/gicv3.h> 20 #include <lib/el3_runtime/context_mgmt.h> 21 #include <lib/el3_runtime/pubsub_events.h> 22 #include <lib/extensions/amu.h> 23 #include <lib/extensions/brbe.h> 24 #include <lib/extensions/mpam.h> 25 #include <lib/extensions/sme.h> 26 #include <lib/extensions/spe.h> 27 #include <lib/extensions/sve.h> 28 #include <lib/extensions/sys_reg_trace.h> 29 #include <lib/extensions/trbe.h> 30 #include <lib/extensions/trf.h> 31 #include <lib/utils.h> 32 33 #if ENABLE_FEAT_TWED 34 /* Make sure delay value fits within the range(0-15) */ 35 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 36 #endif /* ENABLE_FEAT_TWED */ 37 38 static void manage_extensions_secure(cpu_context_t *ctx); 39 /****************************************************************************** 40 * This function performs initializations that are specific to SECURE state 41 * and updates the cpu context specified by 'ctx'. 42 *****************************************************************************/ 43 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 44 { 45 u_register_t scr_el3; 46 el3_state_t *state; 47 48 state = get_el3state_ctx(ctx); 49 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 50 51 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 52 /* 53 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 54 * indicated by the interrupt routing model for BL31. 55 */ 56 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 57 #endif 58 59 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 60 /* Get Memory Tagging Extension support level */ 61 unsigned int mte = get_armv8_5_mte_support(); 62 #endif 63 /* 64 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 65 * is set, or when MTE is only implemented at EL0. 66 */ 67 #if CTX_INCLUDE_MTE_REGS 68 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 69 scr_el3 |= SCR_ATA_BIT; 70 #else 71 if (mte == MTE_IMPLEMENTED_EL0) { 72 scr_el3 |= SCR_ATA_BIT; 73 } 74 #endif /* CTX_INCLUDE_MTE_REGS */ 75 76 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 77 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) { 78 if (GET_RW(ep->spsr) != MODE_RW_64) { 79 ERROR("S-EL2 can not be used in AArch32\n."); 80 panic(); 81 } 82 83 scr_el3 |= SCR_EEL2_BIT; 84 } 85 86 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 87 88 manage_extensions_secure(ctx); 89 } 90 91 #if ENABLE_RME 92 /****************************************************************************** 93 * This function performs initializations that are specific to REALM state 94 * and updates the cpu context specified by 'ctx'. 95 *****************************************************************************/ 96 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 97 { 98 u_register_t scr_el3; 99 el3_state_t *state; 100 101 state = get_el3state_ctx(ctx); 102 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 103 104 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT; 105 106 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 107 } 108 #endif /* ENABLE_RME */ 109 110 /****************************************************************************** 111 * This function performs initializations that are specific to NON-SECURE state 112 * and updates the cpu context specified by 'ctx'. 113 *****************************************************************************/ 114 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 115 { 116 u_register_t scr_el3; 117 el3_state_t *state; 118 119 state = get_el3state_ctx(ctx); 120 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 121 122 /* SCR_NS: Set the NS bit */ 123 scr_el3 |= SCR_NS_BIT; 124 125 #if !CTX_INCLUDE_PAUTH_REGS 126 /* 127 * If the pointer authentication registers aren't saved during world 128 * switches the value of the registers can be leaked from the Secure to 129 * the Non-secure world. To prevent this, rather than enabling pointer 130 * authentication everywhere, we only enable it in the Non-secure world. 131 * 132 * If the Secure world wants to use pointer authentication, 133 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 134 */ 135 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 136 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 137 138 /* Allow access to Allocation Tags when MTE is implemented. */ 139 scr_el3 |= SCR_ATA_BIT; 140 141 #ifdef IMAGE_BL31 142 /* 143 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 144 * indicated by the interrupt routing model for BL31. 145 */ 146 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 147 #endif 148 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 149 150 /* Initialize EL2 context registers */ 151 #if CTX_INCLUDE_EL2_REGS 152 153 /* 154 * Initialize SCTLR_EL2 context register using Endianness value 155 * taken from the entrypoint attribute. 156 */ 157 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 158 sctlr_el2 |= SCTLR_EL2_RES1; 159 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 160 sctlr_el2); 161 162 /* 163 * The GICv3 driver initializes the ICC_SRE_EL2 register during 164 * platform setup. Use the same setting for the corresponding 165 * context register to make sure the correct bits are set when 166 * restoring NS context. 167 */ 168 u_register_t icc_sre_el2 = read_icc_sre_el2(); 169 icc_sre_el2 |= (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT); 170 icc_sre_el2 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 171 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 172 icc_sre_el2); 173 #endif /* CTX_INCLUDE_EL2_REGS */ 174 } 175 176 /******************************************************************************* 177 * The following function performs initialization of the cpu_context 'ctx' 178 * for first use that is common to all security states, and sets the 179 * initial entrypoint state as specified by the entry_point_info structure. 180 * 181 * The EE and ST attributes are used to configure the endianness and secure 182 * timer availability for the new execution context. 183 ******************************************************************************/ 184 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 185 { 186 u_register_t scr_el3; 187 el3_state_t *state; 188 gp_regs_t *gp_regs; 189 u_register_t sctlr_elx, actlr_elx; 190 191 /* Clear any residual register values from the context */ 192 zeromem(ctx, sizeof(*ctx)); 193 194 /* 195 * SCR_EL3 was initialised during reset sequence in macro 196 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 197 * affect the next EL. 198 * 199 * The following fields are initially set to zero and then updated to 200 * the required value depending on the state of the SPSR_EL3 and the 201 * Security state and entrypoint attributes of the next EL. 202 */ 203 scr_el3 = read_scr(); 204 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 205 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 206 207 /* 208 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 209 * Exception level as specified by SPSR. 210 */ 211 if (GET_RW(ep->spsr) == MODE_RW_64) { 212 scr_el3 |= SCR_RW_BIT; 213 } 214 215 /* 216 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 217 * Secure timer registers to EL3, from AArch64 state only, if specified 218 * by the entrypoint attributes. 219 */ 220 if (EP_GET_ST(ep->h.attr) != 0U) { 221 scr_el3 |= SCR_ST_BIT; 222 } 223 224 /* 225 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 226 * SCR_EL3.HXEn. 227 */ 228 #if ENABLE_FEAT_HCX 229 scr_el3 |= SCR_HXEn_BIT; 230 #endif 231 232 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 233 /* 234 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 235 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 236 */ 237 scr_el3 |= SCR_TERR_BIT; 238 #endif 239 240 #if !HANDLE_EA_EL3_FIRST 241 /* 242 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 243 * to EL3 when executing at a lower EL. When executing at EL3, External 244 * Aborts are taken to EL3. 245 */ 246 scr_el3 &= ~SCR_EA_BIT; 247 #endif 248 249 #if FAULT_INJECTION_SUPPORT 250 /* Enable fault injection from lower ELs */ 251 scr_el3 |= SCR_FIEN_BIT; 252 #endif 253 254 /* 255 * CPTR_EL3 was initialized out of reset, copy that value to the 256 * context register. 257 */ 258 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 259 260 /* 261 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 262 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 263 * next mode is Hyp. 264 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 265 * same conditions as HVC instructions and when the processor supports 266 * ARMv8.6-FGT. 267 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 268 * CNTPOFF_EL2 register under the same conditions as HVC instructions 269 * and when the processor supports ECV. 270 */ 271 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 272 || ((GET_RW(ep->spsr) != MODE_RW_64) 273 && (GET_M32(ep->spsr) == MODE32_hyp))) { 274 scr_el3 |= SCR_HCE_BIT; 275 276 if (is_armv8_6_fgt_present()) { 277 scr_el3 |= SCR_FGTEN_BIT; 278 } 279 280 if (get_armv8_6_ecv_support() 281 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 282 scr_el3 |= SCR_ECVEN_BIT; 283 } 284 } 285 286 /* 287 * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3 288 * and EL2, when clear, this bit traps accesses from EL2 so we set it 289 * to 1 when EL2 is present. 290 */ 291 if (is_armv8_6_feat_amuv1p1_present() && 292 (el_implemented(2) != EL_IMPL_NONE)) { 293 scr_el3 |= SCR_AMVOFFEN_BIT; 294 } 295 296 /* 297 * Initialise SCTLR_EL1 to the reset value corresponding to the target 298 * execution state setting all fields rather than relying of the hw. 299 * Some fields have architecturally UNKNOWN reset values and these are 300 * set to zero. 301 * 302 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 303 * 304 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 305 * required by PSCI specification) 306 */ 307 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 308 if (GET_RW(ep->spsr) == MODE_RW_64) { 309 sctlr_elx |= SCTLR_EL1_RES1; 310 } else { 311 /* 312 * If the target execution state is AArch32 then the following 313 * fields need to be set. 314 * 315 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 316 * instructions are not trapped to EL1. 317 * 318 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 319 * instructions are not trapped to EL1. 320 * 321 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 322 * CP15DMB, CP15DSB, and CP15ISB instructions. 323 */ 324 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 325 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 326 } 327 328 #if ERRATA_A75_764081 329 /* 330 * If workaround of errata 764081 for Cortex-A75 is used then set 331 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 332 */ 333 sctlr_elx |= SCTLR_IESB_BIT; 334 #endif 335 336 #if ENABLE_FEAT_TWED 337 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 338 /* Set delay in SCR_EL3 */ 339 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 340 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 341 << SCR_TWEDEL_SHIFT); 342 343 /* Enable WFE delay */ 344 scr_el3 |= SCR_TWEDEn_BIT; 345 #endif /* ENABLE_FEAT_TWED */ 346 347 /* 348 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 349 * and other EL2 registers are set up by cm_prepare_el3_exit() as they 350 * are not part of the stored cpu_context. 351 */ 352 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 353 354 /* 355 * Base the context ACTLR_EL1 on the current value, as it is 356 * implementation defined. The context restore process will write 357 * the value from the context to the actual register and can cause 358 * problems for processor cores that don't expect certain bits to 359 * be zero. 360 */ 361 actlr_elx = read_actlr_el1(); 362 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 363 364 /* 365 * Populate EL3 state so that we've the right context 366 * before doing ERET 367 */ 368 state = get_el3state_ctx(ctx); 369 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 370 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 371 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 372 373 /* 374 * Store the X0-X7 value from the entrypoint into the context 375 * Use memcpy as we are in control of the layout of the structures 376 */ 377 gp_regs = get_gpregs_ctx(ctx); 378 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 379 } 380 381 /******************************************************************************* 382 * Context management library initialization routine. This library is used by 383 * runtime services to share pointers to 'cpu_context' structures for secure 384 * non-secure and realm states. Management of the structures and their associated 385 * memory is not done by the context management library e.g. the PSCI service 386 * manages the cpu context used for entry from and exit to the non-secure state. 387 * The Secure payload dispatcher service manages the context(s) corresponding to 388 * the secure state. It also uses this library to get access to the non-secure 389 * state cpu context pointers. 390 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 391 * which will be used for programming an entry into a lower EL. The same context 392 * will be used to save state upon exception entry from that EL. 393 ******************************************************************************/ 394 void __init cm_init(void) 395 { 396 /* 397 * The context management library has only global data to intialize, but 398 * that will be done when the BSS is zeroed out. 399 */ 400 } 401 402 /******************************************************************************* 403 * This is the high-level function used to initialize the cpu_context 'ctx' for 404 * first use. It performs initializations that are common to all security states 405 * and initializations specific to the security state specified in 'ep' 406 ******************************************************************************/ 407 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 408 { 409 unsigned int security_state; 410 411 assert(ctx != NULL); 412 413 /* 414 * Perform initializations that are common 415 * to all security states 416 */ 417 setup_context_common(ctx, ep); 418 419 security_state = GET_SECURITY_STATE(ep->h.attr); 420 421 /* Perform security state specific initializations */ 422 switch (security_state) { 423 case SECURE: 424 setup_secure_context(ctx, ep); 425 break; 426 #if ENABLE_RME 427 case REALM: 428 setup_realm_context(ctx, ep); 429 break; 430 #endif 431 case NON_SECURE: 432 setup_ns_context(ctx, ep); 433 break; 434 default: 435 ERROR("Invalid security state\n"); 436 panic(); 437 break; 438 } 439 } 440 441 /******************************************************************************* 442 * Enable architecture extensions on first entry to Non-secure world. 443 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 444 * it is zero. 445 ******************************************************************************/ 446 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 447 { 448 #if IMAGE_BL31 449 #if ENABLE_SPE_FOR_LOWER_ELS 450 spe_enable(el2_unused); 451 #endif 452 453 #if ENABLE_AMU 454 amu_enable(el2_unused, ctx); 455 #endif 456 457 #if ENABLE_SME_FOR_NS 458 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 459 sme_enable(ctx); 460 #elif ENABLE_SVE_FOR_NS 461 /* Enable SVE and FPU/SIMD for non-secure world. */ 462 sve_enable(ctx); 463 #endif 464 465 #if ENABLE_MPAM_FOR_LOWER_ELS 466 mpam_enable(el2_unused); 467 #endif 468 469 #if ENABLE_TRBE_FOR_NS 470 trbe_enable(); 471 #endif /* ENABLE_TRBE_FOR_NS */ 472 473 #if ENABLE_BRBE_FOR_NS 474 brbe_enable(); 475 #endif /* ENABLE_BRBE_FOR_NS */ 476 477 #if ENABLE_SYS_REG_TRACE_FOR_NS 478 sys_reg_trace_enable(ctx); 479 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 480 481 #if ENABLE_TRF_FOR_NS 482 trf_enable(); 483 #endif /* ENABLE_TRF_FOR_NS */ 484 #endif 485 } 486 487 /******************************************************************************* 488 * Enable architecture extensions on first entry to Secure world. 489 ******************************************************************************/ 490 static void manage_extensions_secure(cpu_context_t *ctx) 491 { 492 #if IMAGE_BL31 493 #if ENABLE_SME_FOR_NS 494 #if ENABLE_SME_FOR_SWD 495 /* 496 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must 497 * ensure SME, SVE, and FPU/SIMD context properly managed. 498 */ 499 sme_enable(ctx); 500 #else /* ENABLE_SME_FOR_SWD */ 501 /* 502 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can 503 * safely use the associated registers. 504 */ 505 sme_disable(ctx); 506 #endif /* ENABLE_SME_FOR_SWD */ 507 #elif ENABLE_SVE_FOR_NS 508 #if ENABLE_SVE_FOR_SWD 509 /* 510 * Enable SVE and FPU in secure context, secure manager must ensure that 511 * the SVE and FPU register contexts are properly managed. 512 */ 513 sve_enable(ctx); 514 #else /* ENABLE_SVE_FOR_SWD */ 515 /* 516 * Disable SVE and FPU in secure context so non-secure world can safely 517 * use them. 518 */ 519 sve_disable(ctx); 520 #endif /* ENABLE_SVE_FOR_SWD */ 521 #endif /* ENABLE_SVE_FOR_NS */ 522 #endif /* IMAGE_BL31 */ 523 } 524 525 /******************************************************************************* 526 * The following function initializes the cpu_context for a CPU specified by 527 * its `cpu_idx` for first use, and sets the initial entrypoint state as 528 * specified by the entry_point_info structure. 529 ******************************************************************************/ 530 void cm_init_context_by_index(unsigned int cpu_idx, 531 const entry_point_info_t *ep) 532 { 533 cpu_context_t *ctx; 534 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 535 cm_setup_context(ctx, ep); 536 } 537 538 /******************************************************************************* 539 * The following function initializes the cpu_context for the current CPU 540 * for first use, and sets the initial entrypoint state as specified by the 541 * entry_point_info structure. 542 ******************************************************************************/ 543 void cm_init_my_context(const entry_point_info_t *ep) 544 { 545 cpu_context_t *ctx; 546 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 547 cm_setup_context(ctx, ep); 548 } 549 550 /******************************************************************************* 551 * Prepare the CPU system registers for first entry into realm, secure, or 552 * normal world. 553 * 554 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 555 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 556 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 557 * For all entries, the EL1 registers are initialized from the cpu_context 558 ******************************************************************************/ 559 void cm_prepare_el3_exit(uint32_t security_state) 560 { 561 u_register_t sctlr_elx, scr_el3, mdcr_el2; 562 cpu_context_t *ctx = cm_get_context(security_state); 563 bool el2_unused = false; 564 uint64_t hcr_el2 = 0U; 565 566 assert(ctx != NULL); 567 568 if (security_state == NON_SECURE) { 569 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 570 CTX_SCR_EL3); 571 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 572 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 573 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 574 CTX_SCTLR_EL1); 575 sctlr_elx &= SCTLR_EE_BIT; 576 sctlr_elx |= SCTLR_EL2_RES1; 577 #if ERRATA_A75_764081 578 /* 579 * If workaround of errata 764081 for Cortex-A75 is used 580 * then set SCTLR_EL2.IESB to enable Implicit Error 581 * Synchronization Barrier. 582 */ 583 sctlr_elx |= SCTLR_IESB_BIT; 584 #endif 585 write_sctlr_el2(sctlr_elx); 586 } else if (el_implemented(2) != EL_IMPL_NONE) { 587 el2_unused = true; 588 589 /* 590 * EL2 present but unused, need to disable safely. 591 * SCTLR_EL2 can be ignored in this case. 592 * 593 * Set EL2 register width appropriately: Set HCR_EL2 594 * field to match SCR_EL3.RW. 595 */ 596 if ((scr_el3 & SCR_RW_BIT) != 0U) 597 hcr_el2 |= HCR_RW_BIT; 598 599 /* 600 * For Armv8.3 pointer authentication feature, disable 601 * traps to EL2 when accessing key registers or using 602 * pointer authentication instructions from lower ELs. 603 */ 604 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 605 606 write_hcr_el2(hcr_el2); 607 608 /* 609 * Initialise CPTR_EL2 setting all fields rather than 610 * relying on the hw. All fields have architecturally 611 * UNKNOWN reset values. 612 * 613 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 614 * accesses to the CPACR_EL1 or CPACR from both 615 * Execution states do not trap to EL2. 616 * 617 * CPTR_EL2.TTA: Set to zero so that Non-secure System 618 * register accesses to the trace registers from both 619 * Execution states do not trap to EL2. 620 * If PE trace unit System registers are not implemented 621 * then this bit is reserved, and must be set to zero. 622 * 623 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 624 * to SIMD and floating-point functionality from both 625 * Execution states do not trap to EL2. 626 */ 627 write_cptr_el2(CPTR_EL2_RESET_VAL & 628 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 629 | CPTR_EL2_TFP_BIT)); 630 631 /* 632 * Initialise CNTHCTL_EL2. All fields are 633 * architecturally UNKNOWN on reset and are set to zero 634 * except for field(s) listed below. 635 * 636 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 637 * Hyp mode of Non-secure EL0 and EL1 accesses to the 638 * physical timer registers. 639 * 640 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 641 * Hyp mode of Non-secure EL0 and EL1 accesses to the 642 * physical counter registers. 643 */ 644 write_cnthctl_el2(CNTHCTL_RESET_VAL | 645 EL1PCEN_BIT | EL1PCTEN_BIT); 646 647 /* 648 * Initialise CNTVOFF_EL2 to zero as it resets to an 649 * architecturally UNKNOWN value. 650 */ 651 write_cntvoff_el2(0); 652 653 /* 654 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 655 * MPIDR_EL1 respectively. 656 */ 657 write_vpidr_el2(read_midr_el1()); 658 write_vmpidr_el2(read_mpidr_el1()); 659 660 /* 661 * Initialise VTTBR_EL2. All fields are architecturally 662 * UNKNOWN on reset. 663 * 664 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 665 * 2 address translation is disabled, cache maintenance 666 * operations depend on the VMID. 667 * 668 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 669 * translation is disabled. 670 */ 671 write_vttbr_el2(VTTBR_RESET_VAL & 672 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 673 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 674 675 /* 676 * Initialise MDCR_EL2, setting all fields rather than 677 * relying on hw. Some fields are architecturally 678 * UNKNOWN on reset. 679 * 680 * MDCR_EL2.HLP: Set to one so that event counter 681 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 682 * occurs on the increment that changes 683 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 684 * implemented. This bit is RES0 in versions of the 685 * architecture earlier than ARMv8.5, setting it to 1 686 * doesn't have any effect on them. 687 * 688 * MDCR_EL2.TTRF: Set to zero so that access to Trace 689 * Filter Control register TRFCR_EL1 at EL1 is not 690 * trapped to EL2. This bit is RES0 in versions of 691 * the architecture earlier than ARMv8.4. 692 * 693 * MDCR_EL2.HPMD: Set to one so that event counting is 694 * prohibited at EL2. This bit is RES0 in versions of 695 * the architecture earlier than ARMv8.1, setting it 696 * to 1 doesn't have any effect on them. 697 * 698 * MDCR_EL2.TPMS: Set to zero so that accesses to 699 * Statistical Profiling control registers from EL1 700 * do not trap to EL2. This bit is RES0 when SPE is 701 * not implemented. 702 * 703 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 704 * EL1 System register accesses to the Debug ROM 705 * registers are not trapped to EL2. 706 * 707 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 708 * System register accesses to the powerdown debug 709 * registers are not trapped to EL2. 710 * 711 * MDCR_EL2.TDA: Set to zero so that System register 712 * accesses to the debug registers do not trap to EL2. 713 * 714 * MDCR_EL2.TDE: Set to zero so that debug exceptions 715 * are not routed to EL2. 716 * 717 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 718 * Monitors. 719 * 720 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 721 * EL1 accesses to all Performance Monitors registers 722 * are not trapped to EL2. 723 * 724 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 725 * and EL1 accesses to the PMCR_EL0 or PMCR are not 726 * trapped to EL2. 727 * 728 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 729 * architecturally-defined reset value. 730 * 731 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 732 * owning exception level is NS-EL1 and, tracing is 733 * prohibited at NS-EL2. These bits are RES0 when 734 * FEAT_TRBE is not implemented. 735 */ 736 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 737 MDCR_EL2_HPMD) | 738 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 739 >> PMCR_EL0_N_SHIFT)) & 740 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 741 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 742 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 743 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 744 MDCR_EL2_TPMCR_BIT | 745 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 746 747 write_mdcr_el2(mdcr_el2); 748 749 /* 750 * Initialise HSTR_EL2. All fields are architecturally 751 * UNKNOWN on reset. 752 * 753 * HSTR_EL2.T<n>: Set all these fields to zero so that 754 * Non-secure EL0 or EL1 accesses to System registers 755 * do not trap to EL2. 756 */ 757 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 758 /* 759 * Initialise CNTHP_CTL_EL2. All fields are 760 * architecturally UNKNOWN on reset. 761 * 762 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 763 * physical timer and prevent timer interrupts. 764 */ 765 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 766 ~(CNTHP_CTL_ENABLE_BIT)); 767 } 768 manage_extensions_nonsecure(el2_unused, ctx); 769 } 770 771 cm_el1_sysregs_context_restore(security_state); 772 cm_set_next_eret_context(security_state); 773 } 774 775 #if CTX_INCLUDE_EL2_REGS 776 /******************************************************************************* 777 * Save EL2 sysreg context 778 ******************************************************************************/ 779 void cm_el2_sysregs_context_save(uint32_t security_state) 780 { 781 u_register_t scr_el3 = read_scr(); 782 783 /* 784 * Always save the non-secure and realm EL2 context, only save the 785 * S-EL2 context if S-EL2 is enabled. 786 */ 787 if ((security_state != SECURE) || 788 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 789 cpu_context_t *ctx; 790 791 ctx = cm_get_context(security_state); 792 assert(ctx != NULL); 793 794 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 795 } 796 } 797 798 /******************************************************************************* 799 * Restore EL2 sysreg context 800 ******************************************************************************/ 801 void cm_el2_sysregs_context_restore(uint32_t security_state) 802 { 803 u_register_t scr_el3 = read_scr(); 804 805 /* 806 * Always restore the non-secure and realm EL2 context, only restore the 807 * S-EL2 context if S-EL2 is enabled. 808 */ 809 if ((security_state != SECURE) || 810 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 811 cpu_context_t *ctx; 812 813 ctx = cm_get_context(security_state); 814 assert(ctx != NULL); 815 816 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 817 } 818 } 819 #endif /* CTX_INCLUDE_EL2_REGS */ 820 821 /******************************************************************************* 822 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 823 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 824 * updating EL1 and EL2 registers. Otherwise, it calls the generic 825 * cm_prepare_el3_exit function. 826 ******************************************************************************/ 827 void cm_prepare_el3_exit_ns(void) 828 { 829 #if CTX_INCLUDE_EL2_REGS 830 cpu_context_t *ctx = cm_get_context(NON_SECURE); 831 assert(ctx != NULL); 832 833 /* 834 * Currently some extensions are configured using 835 * direct register updates. Therefore, do this here 836 * instead of when setting up context. 837 */ 838 manage_extensions_nonsecure(0, ctx); 839 840 /* 841 * Set the NS bit to be able to access the ICC_SRE_EL2 842 * register when restoring context. 843 */ 844 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 845 846 /* Restore EL2 and EL1 sysreg contexts */ 847 cm_el2_sysregs_context_restore(NON_SECURE); 848 cm_el1_sysregs_context_restore(NON_SECURE); 849 cm_set_next_eret_context(NON_SECURE); 850 #else 851 cm_prepare_el3_exit(NON_SECURE); 852 #endif /* CTX_INCLUDE_EL2_REGS */ 853 } 854 855 /******************************************************************************* 856 * The next four functions are used by runtime services to save and restore 857 * EL1 context on the 'cpu_context' structure for the specified security 858 * state. 859 ******************************************************************************/ 860 void cm_el1_sysregs_context_save(uint32_t security_state) 861 { 862 cpu_context_t *ctx; 863 864 ctx = cm_get_context(security_state); 865 assert(ctx != NULL); 866 867 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 868 869 #if IMAGE_BL31 870 if (security_state == SECURE) 871 PUBLISH_EVENT(cm_exited_secure_world); 872 else 873 PUBLISH_EVENT(cm_exited_normal_world); 874 #endif 875 } 876 877 void cm_el1_sysregs_context_restore(uint32_t security_state) 878 { 879 cpu_context_t *ctx; 880 881 ctx = cm_get_context(security_state); 882 assert(ctx != NULL); 883 884 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 885 886 #if IMAGE_BL31 887 if (security_state == SECURE) 888 PUBLISH_EVENT(cm_entering_secure_world); 889 else 890 PUBLISH_EVENT(cm_entering_normal_world); 891 #endif 892 } 893 894 /******************************************************************************* 895 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 896 * given security state with the given entrypoint 897 ******************************************************************************/ 898 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 899 { 900 cpu_context_t *ctx; 901 el3_state_t *state; 902 903 ctx = cm_get_context(security_state); 904 assert(ctx != NULL); 905 906 /* Populate EL3 state so that ERET jumps to the correct entry */ 907 state = get_el3state_ctx(ctx); 908 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 909 } 910 911 /******************************************************************************* 912 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 913 * pertaining to the given security state 914 ******************************************************************************/ 915 void cm_set_elr_spsr_el3(uint32_t security_state, 916 uintptr_t entrypoint, uint32_t spsr) 917 { 918 cpu_context_t *ctx; 919 el3_state_t *state; 920 921 ctx = cm_get_context(security_state); 922 assert(ctx != NULL); 923 924 /* Populate EL3 state so that ERET jumps to the correct entry */ 925 state = get_el3state_ctx(ctx); 926 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 927 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 928 } 929 930 /******************************************************************************* 931 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 932 * pertaining to the given security state using the value and bit position 933 * specified in the parameters. It preserves all other bits. 934 ******************************************************************************/ 935 void cm_write_scr_el3_bit(uint32_t security_state, 936 uint32_t bit_pos, 937 uint32_t value) 938 { 939 cpu_context_t *ctx; 940 el3_state_t *state; 941 u_register_t scr_el3; 942 943 ctx = cm_get_context(security_state); 944 assert(ctx != NULL); 945 946 /* Ensure that the bit position is a valid one */ 947 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 948 949 /* Ensure that the 'value' is only a bit wide */ 950 assert(value <= 1U); 951 952 /* 953 * Get the SCR_EL3 value from the cpu context, clear the desired bit 954 * and set it to its new value. 955 */ 956 state = get_el3state_ctx(ctx); 957 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 958 scr_el3 &= ~(1UL << bit_pos); 959 scr_el3 |= (u_register_t)value << bit_pos; 960 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 961 } 962 963 /******************************************************************************* 964 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 965 * given security state. 966 ******************************************************************************/ 967 u_register_t cm_get_scr_el3(uint32_t security_state) 968 { 969 cpu_context_t *ctx; 970 el3_state_t *state; 971 972 ctx = cm_get_context(security_state); 973 assert(ctx != NULL); 974 975 /* Populate EL3 state so that ERET jumps to the correct entry */ 976 state = get_el3state_ctx(ctx); 977 return read_ctx_reg(state, CTX_SCR_EL3); 978 } 979 980 /******************************************************************************* 981 * This function is used to program the context that's used for exception 982 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 983 * the required security state 984 ******************************************************************************/ 985 void cm_set_next_eret_context(uint32_t security_state) 986 { 987 cpu_context_t *ctx; 988 989 ctx = cm_get_context(security_state); 990 assert(ctx != NULL); 991 992 cm_set_next_context(ctx); 993 } 994