1 /* 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <drivers/arm/gicv3.h> 20 #include <lib/el3_runtime/context_mgmt.h> 21 #include <lib/el3_runtime/pubsub_events.h> 22 #include <lib/extensions/amu.h> 23 #include <lib/extensions/mpam.h> 24 #include <lib/extensions/sme.h> 25 #include <lib/extensions/spe.h> 26 #include <lib/extensions/sve.h> 27 #include <lib/extensions/sys_reg_trace.h> 28 #include <lib/extensions/trbe.h> 29 #include <lib/extensions/trf.h> 30 #include <lib/utils.h> 31 32 #if ENABLE_FEAT_TWED 33 /* Make sure delay value fits within the range(0-15) */ 34 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 35 #endif /* ENABLE_FEAT_TWED */ 36 37 static void manage_extensions_secure(cpu_context_t *ctx); 38 /****************************************************************************** 39 * This function performs initializations that are specific to SECURE state 40 * and updates the cpu context specified by 'ctx'. 41 *****************************************************************************/ 42 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 43 { 44 u_register_t scr_el3; 45 el3_state_t *state; 46 47 state = get_el3state_ctx(ctx); 48 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 49 50 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 51 /* 52 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 53 * indicated by the interrupt routing model for BL31. 54 */ 55 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 56 #endif 57 58 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 59 /* Get Memory Tagging Extension support level */ 60 unsigned int mte = get_armv8_5_mte_support(); 61 #endif 62 /* 63 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 64 * is set, or when MTE is only implemented at EL0. 65 */ 66 #if CTX_INCLUDE_MTE_REGS 67 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 68 scr_el3 |= SCR_ATA_BIT; 69 #else 70 if (mte == MTE_IMPLEMENTED_EL0) { 71 scr_el3 |= SCR_ATA_BIT; 72 } 73 #endif /* CTX_INCLUDE_MTE_REGS */ 74 75 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 76 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) { 77 if (GET_RW(ep->spsr) != MODE_RW_64) { 78 ERROR("S-EL2 can not be used in AArch32\n."); 79 panic(); 80 } 81 82 scr_el3 |= SCR_EEL2_BIT; 83 } 84 85 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 86 87 manage_extensions_secure(ctx); 88 } 89 90 #if ENABLE_RME 91 /****************************************************************************** 92 * This function performs initializations that are specific to REALM state 93 * and updates the cpu context specified by 'ctx'. 94 *****************************************************************************/ 95 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 96 { 97 u_register_t scr_el3; 98 el3_state_t *state; 99 100 state = get_el3state_ctx(ctx); 101 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 102 103 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT; 104 105 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 106 } 107 #endif /* ENABLE_RME */ 108 109 /****************************************************************************** 110 * This function performs initializations that are specific to NON-SECURE state 111 * and updates the cpu context specified by 'ctx'. 112 *****************************************************************************/ 113 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 114 { 115 u_register_t scr_el3; 116 el3_state_t *state; 117 118 state = get_el3state_ctx(ctx); 119 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 120 121 /* SCR_NS: Set the NS bit */ 122 scr_el3 |= SCR_NS_BIT; 123 124 #if !CTX_INCLUDE_PAUTH_REGS 125 /* 126 * If the pointer authentication registers aren't saved during world 127 * switches the value of the registers can be leaked from the Secure to 128 * the Non-secure world. To prevent this, rather than enabling pointer 129 * authentication everywhere, we only enable it in the Non-secure world. 130 * 131 * If the Secure world wants to use pointer authentication, 132 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 133 */ 134 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 135 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 136 137 /* Allow access to Allocation Tags when MTE is implemented. */ 138 scr_el3 |= SCR_ATA_BIT; 139 140 #ifdef IMAGE_BL31 141 /* 142 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 143 * indicated by the interrupt routing model for BL31. 144 */ 145 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 146 #endif 147 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 148 149 /* Initialize EL2 context registers */ 150 #if CTX_INCLUDE_EL2_REGS 151 152 /* 153 * Initialize SCTLR_EL2 context register using Endianness value 154 * taken from the entrypoint attribute. 155 */ 156 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 157 sctlr_el2 |= SCTLR_EL2_RES1; 158 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 159 sctlr_el2); 160 161 /* 162 * The GICv3 driver initializes the ICC_SRE_EL2 register during 163 * platform setup. Use the same setting for the corresponding 164 * context register to make sure the correct bits are set when 165 * restoring NS context. 166 */ 167 u_register_t icc_sre_el2 = read_icc_sre_el2(); 168 icc_sre_el2 |= (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT); 169 icc_sre_el2 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 170 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 171 icc_sre_el2); 172 #endif /* CTX_INCLUDE_EL2_REGS */ 173 } 174 175 /******************************************************************************* 176 * The following function performs initialization of the cpu_context 'ctx' 177 * for first use that is common to all security states, and sets the 178 * initial entrypoint state as specified by the entry_point_info structure. 179 * 180 * The EE and ST attributes are used to configure the endianness and secure 181 * timer availability for the new execution context. 182 ******************************************************************************/ 183 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 184 { 185 u_register_t scr_el3; 186 el3_state_t *state; 187 gp_regs_t *gp_regs; 188 u_register_t sctlr_elx, actlr_elx; 189 190 /* Clear any residual register values from the context */ 191 zeromem(ctx, sizeof(*ctx)); 192 193 /* 194 * SCR_EL3 was initialised during reset sequence in macro 195 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 196 * affect the next EL. 197 * 198 * The following fields are initially set to zero and then updated to 199 * the required value depending on the state of the SPSR_EL3 and the 200 * Security state and entrypoint attributes of the next EL. 201 */ 202 scr_el3 = read_scr(); 203 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 204 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 205 206 /* 207 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 208 * Exception level as specified by SPSR. 209 */ 210 if (GET_RW(ep->spsr) == MODE_RW_64) { 211 scr_el3 |= SCR_RW_BIT; 212 } 213 214 /* 215 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 216 * Secure timer registers to EL3, from AArch64 state only, if specified 217 * by the entrypoint attributes. 218 */ 219 if (EP_GET_ST(ep->h.attr) != 0U) { 220 scr_el3 |= SCR_ST_BIT; 221 } 222 223 /* 224 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 225 * SCR_EL3.HXEn. 226 */ 227 #if ENABLE_FEAT_HCX 228 scr_el3 |= SCR_HXEn_BIT; 229 #endif 230 231 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 232 /* 233 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 234 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 235 */ 236 scr_el3 |= SCR_TERR_BIT; 237 #endif 238 239 #if !HANDLE_EA_EL3_FIRST 240 /* 241 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 242 * to EL3 when executing at a lower EL. When executing at EL3, External 243 * Aborts are taken to EL3. 244 */ 245 scr_el3 &= ~SCR_EA_BIT; 246 #endif 247 248 #if FAULT_INJECTION_SUPPORT 249 /* Enable fault injection from lower ELs */ 250 scr_el3 |= SCR_FIEN_BIT; 251 #endif 252 253 /* 254 * CPTR_EL3 was initialized out of reset, copy that value to the 255 * context register. 256 */ 257 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 258 259 /* 260 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 261 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 262 * next mode is Hyp. 263 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 264 * same conditions as HVC instructions and when the processor supports 265 * ARMv8.6-FGT. 266 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 267 * CNTPOFF_EL2 register under the same conditions as HVC instructions 268 * and when the processor supports ECV. 269 */ 270 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 271 || ((GET_RW(ep->spsr) != MODE_RW_64) 272 && (GET_M32(ep->spsr) == MODE32_hyp))) { 273 scr_el3 |= SCR_HCE_BIT; 274 275 if (is_armv8_6_fgt_present()) { 276 scr_el3 |= SCR_FGTEN_BIT; 277 } 278 279 if (get_armv8_6_ecv_support() 280 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 281 scr_el3 |= SCR_ECVEN_BIT; 282 } 283 } 284 285 /* 286 * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3 287 * and EL2, when clear, this bit traps accesses from EL2 so we set it 288 * to 1 when EL2 is present. 289 */ 290 if (is_armv8_6_feat_amuv1p1_present() && 291 (el_implemented(2) != EL_IMPL_NONE)) { 292 scr_el3 |= SCR_AMVOFFEN_BIT; 293 } 294 295 /* 296 * Initialise SCTLR_EL1 to the reset value corresponding to the target 297 * execution state setting all fields rather than relying of the hw. 298 * Some fields have architecturally UNKNOWN reset values and these are 299 * set to zero. 300 * 301 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 302 * 303 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 304 * required by PSCI specification) 305 */ 306 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 307 if (GET_RW(ep->spsr) == MODE_RW_64) { 308 sctlr_elx |= SCTLR_EL1_RES1; 309 } else { 310 /* 311 * If the target execution state is AArch32 then the following 312 * fields need to be set. 313 * 314 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 315 * instructions are not trapped to EL1. 316 * 317 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 318 * instructions are not trapped to EL1. 319 * 320 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 321 * CP15DMB, CP15DSB, and CP15ISB instructions. 322 */ 323 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 324 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 325 } 326 327 #if ERRATA_A75_764081 328 /* 329 * If workaround of errata 764081 for Cortex-A75 is used then set 330 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 331 */ 332 sctlr_elx |= SCTLR_IESB_BIT; 333 #endif 334 335 #if ENABLE_FEAT_TWED 336 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 337 /* Set delay in SCR_EL3 */ 338 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 339 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 340 << SCR_TWEDEL_SHIFT); 341 342 /* Enable WFE delay */ 343 scr_el3 |= SCR_TWEDEn_BIT; 344 #endif /* ENABLE_FEAT_TWED */ 345 346 /* 347 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 348 * and other EL2 registers are set up by cm_prepare_el3_exit() as they 349 * are not part of the stored cpu_context. 350 */ 351 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 352 353 /* 354 * Base the context ACTLR_EL1 on the current value, as it is 355 * implementation defined. The context restore process will write 356 * the value from the context to the actual register and can cause 357 * problems for processor cores that don't expect certain bits to 358 * be zero. 359 */ 360 actlr_elx = read_actlr_el1(); 361 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 362 363 /* 364 * Populate EL3 state so that we've the right context 365 * before doing ERET 366 */ 367 state = get_el3state_ctx(ctx); 368 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 369 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 370 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 371 372 /* 373 * Store the X0-X7 value from the entrypoint into the context 374 * Use memcpy as we are in control of the layout of the structures 375 */ 376 gp_regs = get_gpregs_ctx(ctx); 377 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 378 } 379 380 /******************************************************************************* 381 * Context management library initialization routine. This library is used by 382 * runtime services to share pointers to 'cpu_context' structures for secure 383 * non-secure and realm states. Management of the structures and their associated 384 * memory is not done by the context management library e.g. the PSCI service 385 * manages the cpu context used for entry from and exit to the non-secure state. 386 * The Secure payload dispatcher service manages the context(s) corresponding to 387 * the secure state. It also uses this library to get access to the non-secure 388 * state cpu context pointers. 389 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 390 * which will be used for programming an entry into a lower EL. The same context 391 * will be used to save state upon exception entry from that EL. 392 ******************************************************************************/ 393 void __init cm_init(void) 394 { 395 /* 396 * The context management library has only global data to intialize, but 397 * that will be done when the BSS is zeroed out. 398 */ 399 } 400 401 /******************************************************************************* 402 * This is the high-level function used to initialize the cpu_context 'ctx' for 403 * first use. It performs initializations that are common to all security states 404 * and initializations specific to the security state specified in 'ep' 405 ******************************************************************************/ 406 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 407 { 408 unsigned int security_state; 409 410 assert(ctx != NULL); 411 412 /* 413 * Perform initializations that are common 414 * to all security states 415 */ 416 setup_context_common(ctx, ep); 417 418 security_state = GET_SECURITY_STATE(ep->h.attr); 419 420 /* Perform security state specific initializations */ 421 switch (security_state) { 422 case SECURE: 423 setup_secure_context(ctx, ep); 424 break; 425 #if ENABLE_RME 426 case REALM: 427 setup_realm_context(ctx, ep); 428 break; 429 #endif 430 case NON_SECURE: 431 setup_ns_context(ctx, ep); 432 break; 433 default: 434 ERROR("Invalid security state\n"); 435 panic(); 436 break; 437 } 438 } 439 440 /******************************************************************************* 441 * Enable architecture extensions on first entry to Non-secure world. 442 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 443 * it is zero. 444 ******************************************************************************/ 445 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 446 { 447 #if IMAGE_BL31 448 #if ENABLE_SPE_FOR_LOWER_ELS 449 spe_enable(el2_unused); 450 #endif 451 452 #if ENABLE_AMU 453 amu_enable(el2_unused, ctx); 454 #endif 455 456 #if ENABLE_SME_FOR_NS 457 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 458 sme_enable(ctx); 459 #elif ENABLE_SVE_FOR_NS 460 /* Enable SVE and FPU/SIMD for non-secure world. */ 461 sve_enable(ctx); 462 #endif 463 464 #if ENABLE_MPAM_FOR_LOWER_ELS 465 mpam_enable(el2_unused); 466 #endif 467 468 #if ENABLE_TRBE_FOR_NS 469 trbe_enable(); 470 #endif /* ENABLE_TRBE_FOR_NS */ 471 472 #if ENABLE_SYS_REG_TRACE_FOR_NS 473 sys_reg_trace_enable(ctx); 474 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 475 476 #if ENABLE_TRF_FOR_NS 477 trf_enable(); 478 #endif /* ENABLE_TRF_FOR_NS */ 479 #endif 480 } 481 482 /******************************************************************************* 483 * Enable architecture extensions on first entry to Secure world. 484 ******************************************************************************/ 485 static void manage_extensions_secure(cpu_context_t *ctx) 486 { 487 #if IMAGE_BL31 488 #if ENABLE_SME_FOR_NS 489 #if ENABLE_SME_FOR_SWD 490 /* 491 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must 492 * ensure SME, SVE, and FPU/SIMD context properly managed. 493 */ 494 sme_enable(ctx); 495 #else /* ENABLE_SME_FOR_SWD */ 496 /* 497 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can 498 * safely use the associated registers. 499 */ 500 sme_disable(ctx); 501 #endif /* ENABLE_SME_FOR_SWD */ 502 #elif ENABLE_SVE_FOR_NS 503 #if ENABLE_SVE_FOR_SWD 504 /* 505 * Enable SVE and FPU in secure context, secure manager must ensure that 506 * the SVE and FPU register contexts are properly managed. 507 */ 508 sve_enable(ctx); 509 #else /* ENABLE_SVE_FOR_SWD */ 510 /* 511 * Disable SVE and FPU in secure context so non-secure world can safely 512 * use them. 513 */ 514 sve_disable(ctx); 515 #endif /* ENABLE_SVE_FOR_SWD */ 516 #endif /* ENABLE_SVE_FOR_NS */ 517 #endif /* IMAGE_BL31 */ 518 } 519 520 /******************************************************************************* 521 * The following function initializes the cpu_context for a CPU specified by 522 * its `cpu_idx` for first use, and sets the initial entrypoint state as 523 * specified by the entry_point_info structure. 524 ******************************************************************************/ 525 void cm_init_context_by_index(unsigned int cpu_idx, 526 const entry_point_info_t *ep) 527 { 528 cpu_context_t *ctx; 529 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 530 cm_setup_context(ctx, ep); 531 } 532 533 /******************************************************************************* 534 * The following function initializes the cpu_context for the current CPU 535 * for first use, and sets the initial entrypoint state as specified by the 536 * entry_point_info structure. 537 ******************************************************************************/ 538 void cm_init_my_context(const entry_point_info_t *ep) 539 { 540 cpu_context_t *ctx; 541 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 542 cm_setup_context(ctx, ep); 543 } 544 545 /******************************************************************************* 546 * Prepare the CPU system registers for first entry into realm, secure, or 547 * normal world. 548 * 549 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 550 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 551 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 552 * For all entries, the EL1 registers are initialized from the cpu_context 553 ******************************************************************************/ 554 void cm_prepare_el3_exit(uint32_t security_state) 555 { 556 u_register_t sctlr_elx, scr_el3, mdcr_el2; 557 cpu_context_t *ctx = cm_get_context(security_state); 558 bool el2_unused = false; 559 uint64_t hcr_el2 = 0U; 560 561 assert(ctx != NULL); 562 563 if (security_state == NON_SECURE) { 564 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 565 CTX_SCR_EL3); 566 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 567 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 568 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 569 CTX_SCTLR_EL1); 570 sctlr_elx &= SCTLR_EE_BIT; 571 sctlr_elx |= SCTLR_EL2_RES1; 572 #if ERRATA_A75_764081 573 /* 574 * If workaround of errata 764081 for Cortex-A75 is used 575 * then set SCTLR_EL2.IESB to enable Implicit Error 576 * Synchronization Barrier. 577 */ 578 sctlr_elx |= SCTLR_IESB_BIT; 579 #endif 580 write_sctlr_el2(sctlr_elx); 581 } else if (el_implemented(2) != EL_IMPL_NONE) { 582 el2_unused = true; 583 584 /* 585 * EL2 present but unused, need to disable safely. 586 * SCTLR_EL2 can be ignored in this case. 587 * 588 * Set EL2 register width appropriately: Set HCR_EL2 589 * field to match SCR_EL3.RW. 590 */ 591 if ((scr_el3 & SCR_RW_BIT) != 0U) 592 hcr_el2 |= HCR_RW_BIT; 593 594 /* 595 * For Armv8.3 pointer authentication feature, disable 596 * traps to EL2 when accessing key registers or using 597 * pointer authentication instructions from lower ELs. 598 */ 599 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 600 601 write_hcr_el2(hcr_el2); 602 603 /* 604 * Initialise CPTR_EL2 setting all fields rather than 605 * relying on the hw. All fields have architecturally 606 * UNKNOWN reset values. 607 * 608 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 609 * accesses to the CPACR_EL1 or CPACR from both 610 * Execution states do not trap to EL2. 611 * 612 * CPTR_EL2.TTA: Set to zero so that Non-secure System 613 * register accesses to the trace registers from both 614 * Execution states do not trap to EL2. 615 * If PE trace unit System registers are not implemented 616 * then this bit is reserved, and must be set to zero. 617 * 618 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 619 * to SIMD and floating-point functionality from both 620 * Execution states do not trap to EL2. 621 */ 622 write_cptr_el2(CPTR_EL2_RESET_VAL & 623 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 624 | CPTR_EL2_TFP_BIT)); 625 626 /* 627 * Initialise CNTHCTL_EL2. All fields are 628 * architecturally UNKNOWN on reset and are set to zero 629 * except for field(s) listed below. 630 * 631 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 632 * Hyp mode of Non-secure EL0 and EL1 accesses to the 633 * physical timer registers. 634 * 635 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 636 * Hyp mode of Non-secure EL0 and EL1 accesses to the 637 * physical counter registers. 638 */ 639 write_cnthctl_el2(CNTHCTL_RESET_VAL | 640 EL1PCEN_BIT | EL1PCTEN_BIT); 641 642 /* 643 * Initialise CNTVOFF_EL2 to zero as it resets to an 644 * architecturally UNKNOWN value. 645 */ 646 write_cntvoff_el2(0); 647 648 /* 649 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 650 * MPIDR_EL1 respectively. 651 */ 652 write_vpidr_el2(read_midr_el1()); 653 write_vmpidr_el2(read_mpidr_el1()); 654 655 /* 656 * Initialise VTTBR_EL2. All fields are architecturally 657 * UNKNOWN on reset. 658 * 659 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 660 * 2 address translation is disabled, cache maintenance 661 * operations depend on the VMID. 662 * 663 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 664 * translation is disabled. 665 */ 666 write_vttbr_el2(VTTBR_RESET_VAL & 667 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 668 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 669 670 /* 671 * Initialise MDCR_EL2, setting all fields rather than 672 * relying on hw. Some fields are architecturally 673 * UNKNOWN on reset. 674 * 675 * MDCR_EL2.HLP: Set to one so that event counter 676 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 677 * occurs on the increment that changes 678 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 679 * implemented. This bit is RES0 in versions of the 680 * architecture earlier than ARMv8.5, setting it to 1 681 * doesn't have any effect on them. 682 * 683 * MDCR_EL2.TTRF: Set to zero so that access to Trace 684 * Filter Control register TRFCR_EL1 at EL1 is not 685 * trapped to EL2. This bit is RES0 in versions of 686 * the architecture earlier than ARMv8.4. 687 * 688 * MDCR_EL2.HPMD: Set to one so that event counting is 689 * prohibited at EL2. This bit is RES0 in versions of 690 * the architecture earlier than ARMv8.1, setting it 691 * to 1 doesn't have any effect on them. 692 * 693 * MDCR_EL2.TPMS: Set to zero so that accesses to 694 * Statistical Profiling control registers from EL1 695 * do not trap to EL2. This bit is RES0 when SPE is 696 * not implemented. 697 * 698 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 699 * EL1 System register accesses to the Debug ROM 700 * registers are not trapped to EL2. 701 * 702 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 703 * System register accesses to the powerdown debug 704 * registers are not trapped to EL2. 705 * 706 * MDCR_EL2.TDA: Set to zero so that System register 707 * accesses to the debug registers do not trap to EL2. 708 * 709 * MDCR_EL2.TDE: Set to zero so that debug exceptions 710 * are not routed to EL2. 711 * 712 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 713 * Monitors. 714 * 715 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 716 * EL1 accesses to all Performance Monitors registers 717 * are not trapped to EL2. 718 * 719 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 720 * and EL1 accesses to the PMCR_EL0 or PMCR are not 721 * trapped to EL2. 722 * 723 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 724 * architecturally-defined reset value. 725 * 726 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 727 * owning exception level is NS-EL1 and, tracing is 728 * prohibited at NS-EL2. These bits are RES0 when 729 * FEAT_TRBE is not implemented. 730 */ 731 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 732 MDCR_EL2_HPMD) | 733 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 734 >> PMCR_EL0_N_SHIFT)) & 735 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 736 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 737 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 738 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 739 MDCR_EL2_TPMCR_BIT | 740 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 741 742 write_mdcr_el2(mdcr_el2); 743 744 /* 745 * Initialise HSTR_EL2. All fields are architecturally 746 * UNKNOWN on reset. 747 * 748 * HSTR_EL2.T<n>: Set all these fields to zero so that 749 * Non-secure EL0 or EL1 accesses to System registers 750 * do not trap to EL2. 751 */ 752 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 753 /* 754 * Initialise CNTHP_CTL_EL2. All fields are 755 * architecturally UNKNOWN on reset. 756 * 757 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 758 * physical timer and prevent timer interrupts. 759 */ 760 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 761 ~(CNTHP_CTL_ENABLE_BIT)); 762 } 763 manage_extensions_nonsecure(el2_unused, ctx); 764 } 765 766 cm_el1_sysregs_context_restore(security_state); 767 cm_set_next_eret_context(security_state); 768 } 769 770 #if CTX_INCLUDE_EL2_REGS 771 /******************************************************************************* 772 * Save EL2 sysreg context 773 ******************************************************************************/ 774 void cm_el2_sysregs_context_save(uint32_t security_state) 775 { 776 u_register_t scr_el3 = read_scr(); 777 778 /* 779 * Always save the non-secure and realm EL2 context, only save the 780 * S-EL2 context if S-EL2 is enabled. 781 */ 782 if ((security_state != SECURE) || 783 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 784 cpu_context_t *ctx; 785 786 ctx = cm_get_context(security_state); 787 assert(ctx != NULL); 788 789 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 790 } 791 } 792 793 /******************************************************************************* 794 * Restore EL2 sysreg context 795 ******************************************************************************/ 796 void cm_el2_sysregs_context_restore(uint32_t security_state) 797 { 798 u_register_t scr_el3 = read_scr(); 799 800 /* 801 * Always restore the non-secure and realm EL2 context, only restore the 802 * S-EL2 context if S-EL2 is enabled. 803 */ 804 if ((security_state != SECURE) || 805 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 806 cpu_context_t *ctx; 807 808 ctx = cm_get_context(security_state); 809 assert(ctx != NULL); 810 811 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 812 } 813 } 814 #endif /* CTX_INCLUDE_EL2_REGS */ 815 816 /******************************************************************************* 817 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 818 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 819 * updating EL1 and EL2 registers. Otherwise, it calls the generic 820 * cm_prepare_el3_exit function. 821 ******************************************************************************/ 822 void cm_prepare_el3_exit_ns(void) 823 { 824 #if CTX_INCLUDE_EL2_REGS 825 cpu_context_t *ctx = cm_get_context(NON_SECURE); 826 assert(ctx != NULL); 827 828 /* 829 * Currently some extensions are configured using 830 * direct register updates. Therefore, do this here 831 * instead of when setting up context. 832 */ 833 manage_extensions_nonsecure(0, ctx); 834 835 /* 836 * Set the NS bit to be able to access the ICC_SRE_EL2 837 * register when restoring context. 838 */ 839 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 840 841 /* Restore EL2 and EL1 sysreg contexts */ 842 cm_el2_sysregs_context_restore(NON_SECURE); 843 cm_el1_sysregs_context_restore(NON_SECURE); 844 cm_set_next_eret_context(NON_SECURE); 845 #else 846 cm_prepare_el3_exit(NON_SECURE); 847 #endif /* CTX_INCLUDE_EL2_REGS */ 848 } 849 850 /******************************************************************************* 851 * The next four functions are used by runtime services to save and restore 852 * EL1 context on the 'cpu_context' structure for the specified security 853 * state. 854 ******************************************************************************/ 855 void cm_el1_sysregs_context_save(uint32_t security_state) 856 { 857 cpu_context_t *ctx; 858 859 ctx = cm_get_context(security_state); 860 assert(ctx != NULL); 861 862 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 863 864 #if IMAGE_BL31 865 if (security_state == SECURE) 866 PUBLISH_EVENT(cm_exited_secure_world); 867 else 868 PUBLISH_EVENT(cm_exited_normal_world); 869 #endif 870 } 871 872 void cm_el1_sysregs_context_restore(uint32_t security_state) 873 { 874 cpu_context_t *ctx; 875 876 ctx = cm_get_context(security_state); 877 assert(ctx != NULL); 878 879 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 880 881 #if IMAGE_BL31 882 if (security_state == SECURE) 883 PUBLISH_EVENT(cm_entering_secure_world); 884 else 885 PUBLISH_EVENT(cm_entering_normal_world); 886 #endif 887 } 888 889 /******************************************************************************* 890 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 891 * given security state with the given entrypoint 892 ******************************************************************************/ 893 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 894 { 895 cpu_context_t *ctx; 896 el3_state_t *state; 897 898 ctx = cm_get_context(security_state); 899 assert(ctx != NULL); 900 901 /* Populate EL3 state so that ERET jumps to the correct entry */ 902 state = get_el3state_ctx(ctx); 903 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 904 } 905 906 /******************************************************************************* 907 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 908 * pertaining to the given security state 909 ******************************************************************************/ 910 void cm_set_elr_spsr_el3(uint32_t security_state, 911 uintptr_t entrypoint, uint32_t spsr) 912 { 913 cpu_context_t *ctx; 914 el3_state_t *state; 915 916 ctx = cm_get_context(security_state); 917 assert(ctx != NULL); 918 919 /* Populate EL3 state so that ERET jumps to the correct entry */ 920 state = get_el3state_ctx(ctx); 921 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 922 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 923 } 924 925 /******************************************************************************* 926 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 927 * pertaining to the given security state using the value and bit position 928 * specified in the parameters. It preserves all other bits. 929 ******************************************************************************/ 930 void cm_write_scr_el3_bit(uint32_t security_state, 931 uint32_t bit_pos, 932 uint32_t value) 933 { 934 cpu_context_t *ctx; 935 el3_state_t *state; 936 u_register_t scr_el3; 937 938 ctx = cm_get_context(security_state); 939 assert(ctx != NULL); 940 941 /* Ensure that the bit position is a valid one */ 942 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 943 944 /* Ensure that the 'value' is only a bit wide */ 945 assert(value <= 1U); 946 947 /* 948 * Get the SCR_EL3 value from the cpu context, clear the desired bit 949 * and set it to its new value. 950 */ 951 state = get_el3state_ctx(ctx); 952 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 953 scr_el3 &= ~(1UL << bit_pos); 954 scr_el3 |= (u_register_t)value << bit_pos; 955 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 956 } 957 958 /******************************************************************************* 959 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 960 * given security state. 961 ******************************************************************************/ 962 u_register_t cm_get_scr_el3(uint32_t security_state) 963 { 964 cpu_context_t *ctx; 965 el3_state_t *state; 966 967 ctx = cm_get_context(security_state); 968 assert(ctx != NULL); 969 970 /* Populate EL3 state so that ERET jumps to the correct entry */ 971 state = get_el3state_ctx(ctx); 972 return read_ctx_reg(state, CTX_SCR_EL3); 973 } 974 975 /******************************************************************************* 976 * This function is used to program the context that's used for exception 977 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 978 * the required security state 979 ******************************************************************************/ 980 void cm_set_next_eret_context(uint32_t security_state) 981 { 982 cpu_context_t *ctx; 983 984 ctx = cm_get_context(security_state); 985 assert(ctx != NULL); 986 987 cm_set_next_context(ctx); 988 } 989