1 /* 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <drivers/arm/gicv3.h> 20 #include <lib/el3_runtime/context_mgmt.h> 21 #include <lib/el3_runtime/pubsub_events.h> 22 #include <lib/extensions/amu.h> 23 #include <lib/extensions/mpam.h> 24 #include <lib/extensions/sme.h> 25 #include <lib/extensions/spe.h> 26 #include <lib/extensions/sve.h> 27 #include <lib/extensions/sys_reg_trace.h> 28 #include <lib/extensions/trbe.h> 29 #include <lib/extensions/trf.h> 30 #include <lib/extensions/twed.h> 31 #include <lib/utils.h> 32 33 static void manage_extensions_secure(cpu_context_t *ctx); 34 35 /****************************************************************************** 36 * This function performs initializations that are specific to SECURE state 37 * and updates the cpu context specified by 'ctx'. 38 *****************************************************************************/ 39 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 40 { 41 u_register_t scr_el3; 42 el3_state_t *state; 43 44 state = get_el3state_ctx(ctx); 45 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 46 47 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 48 /* 49 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 50 * indicated by the interrupt routing model for BL31. 51 */ 52 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 53 #endif 54 55 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 56 /* Get Memory Tagging Extension support level */ 57 unsigned int mte = get_armv8_5_mte_support(); 58 #endif 59 /* 60 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 61 * is set, or when MTE is only implemented at EL0. 62 */ 63 #if CTX_INCLUDE_MTE_REGS 64 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 65 scr_el3 |= SCR_ATA_BIT; 66 #else 67 if (mte == MTE_IMPLEMENTED_EL0) { 68 scr_el3 |= SCR_ATA_BIT; 69 } 70 #endif /* CTX_INCLUDE_MTE_REGS */ 71 72 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 73 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) { 74 if (GET_RW(ep->spsr) != MODE_RW_64) { 75 ERROR("S-EL2 can not be used in AArch32\n."); 76 panic(); 77 } 78 79 scr_el3 |= SCR_EEL2_BIT; 80 } 81 82 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 83 84 manage_extensions_secure(ctx); 85 } 86 87 #if ENABLE_RME 88 /****************************************************************************** 89 * This function performs initializations that are specific to REALM state 90 * and updates the cpu context specified by 'ctx'. 91 *****************************************************************************/ 92 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 93 { 94 u_register_t scr_el3; 95 el3_state_t *state; 96 97 state = get_el3state_ctx(ctx); 98 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 99 100 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT; 101 102 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 103 } 104 #endif /* ENABLE_RME */ 105 106 /****************************************************************************** 107 * This function performs initializations that are specific to NON-SECURE state 108 * and updates the cpu context specified by 'ctx'. 109 *****************************************************************************/ 110 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 111 { 112 u_register_t scr_el3; 113 el3_state_t *state; 114 115 state = get_el3state_ctx(ctx); 116 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 117 118 /* SCR_NS: Set the NS bit */ 119 scr_el3 |= SCR_NS_BIT; 120 121 #if !CTX_INCLUDE_PAUTH_REGS 122 /* 123 * If the pointer authentication registers aren't saved during world 124 * switches the value of the registers can be leaked from the Secure to 125 * the Non-secure world. To prevent this, rather than enabling pointer 126 * authentication everywhere, we only enable it in the Non-secure world. 127 * 128 * If the Secure world wants to use pointer authentication, 129 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 130 */ 131 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 132 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 133 134 /* Allow access to Allocation Tags when MTE is implemented. */ 135 scr_el3 |= SCR_ATA_BIT; 136 137 #ifdef IMAGE_BL31 138 /* 139 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 140 * indicated by the interrupt routing model for BL31. 141 */ 142 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 143 #endif 144 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 145 146 /* Initialize EL2 context registers */ 147 #if CTX_INCLUDE_EL2_REGS 148 149 /* 150 * Initialize SCTLR_EL2 context register using Endianness value 151 * taken from the entrypoint attribute. 152 */ 153 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 154 sctlr_el2 |= SCTLR_EL2_RES1; 155 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 156 sctlr_el2); 157 158 /* 159 * The GICv3 driver initializes the ICC_SRE_EL2 register during 160 * platform setup. Use the same setting for the corresponding 161 * context register to make sure the correct bits are set when 162 * restoring NS context. 163 */ 164 u_register_t icc_sre_el2 = read_icc_sre_el2(); 165 icc_sre_el2 |= (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT); 166 icc_sre_el2 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 167 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 168 icc_sre_el2); 169 #endif /* CTX_INCLUDE_EL2_REGS */ 170 } 171 172 /******************************************************************************* 173 * The following function performs initialization of the cpu_context 'ctx' 174 * for first use that is common to all security states, and sets the 175 * initial entrypoint state as specified by the entry_point_info structure. 176 * 177 * The EE and ST attributes are used to configure the endianness and secure 178 * timer availability for the new execution context. 179 ******************************************************************************/ 180 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 181 { 182 u_register_t scr_el3; 183 el3_state_t *state; 184 gp_regs_t *gp_regs; 185 u_register_t sctlr_elx, actlr_elx; 186 187 /* Clear any residual register values from the context */ 188 zeromem(ctx, sizeof(*ctx)); 189 190 /* 191 * SCR_EL3 was initialised during reset sequence in macro 192 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 193 * affect the next EL. 194 * 195 * The following fields are initially set to zero and then updated to 196 * the required value depending on the state of the SPSR_EL3 and the 197 * Security state and entrypoint attributes of the next EL. 198 */ 199 scr_el3 = read_scr(); 200 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 201 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 202 203 /* 204 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 205 * Exception level as specified by SPSR. 206 */ 207 if (GET_RW(ep->spsr) == MODE_RW_64) { 208 scr_el3 |= SCR_RW_BIT; 209 } 210 211 /* 212 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 213 * Secure timer registers to EL3, from AArch64 state only, if specified 214 * by the entrypoint attributes. 215 */ 216 if (EP_GET_ST(ep->h.attr) != 0U) { 217 scr_el3 |= SCR_ST_BIT; 218 } 219 220 /* 221 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 222 * SCR_EL3.HXEn. 223 */ 224 #if ENABLE_FEAT_HCX 225 scr_el3 |= SCR_HXEn_BIT; 226 #endif 227 228 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 229 /* 230 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 231 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 232 */ 233 scr_el3 |= SCR_TERR_BIT; 234 #endif 235 236 #if !HANDLE_EA_EL3_FIRST 237 /* 238 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 239 * to EL3 when executing at a lower EL. When executing at EL3, External 240 * Aborts are taken to EL3. 241 */ 242 scr_el3 &= ~SCR_EA_BIT; 243 #endif 244 245 #if FAULT_INJECTION_SUPPORT 246 /* Enable fault injection from lower ELs */ 247 scr_el3 |= SCR_FIEN_BIT; 248 #endif 249 250 /* 251 * CPTR_EL3 was initialized out of reset, copy that value to the 252 * context register. 253 */ 254 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 255 256 /* 257 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 258 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 259 * next mode is Hyp. 260 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 261 * same conditions as HVC instructions and when the processor supports 262 * ARMv8.6-FGT. 263 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 264 * CNTPOFF_EL2 register under the same conditions as HVC instructions 265 * and when the processor supports ECV. 266 */ 267 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 268 || ((GET_RW(ep->spsr) != MODE_RW_64) 269 && (GET_M32(ep->spsr) == MODE32_hyp))) { 270 scr_el3 |= SCR_HCE_BIT; 271 272 if (is_armv8_6_fgt_present()) { 273 scr_el3 |= SCR_FGTEN_BIT; 274 } 275 276 if (get_armv8_6_ecv_support() 277 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 278 scr_el3 |= SCR_ECVEN_BIT; 279 } 280 } 281 282 /* 283 * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3 284 * and EL2, when clear, this bit traps accesses from EL2 so we set it 285 * to 1 when EL2 is present. 286 */ 287 if (is_armv8_6_feat_amuv1p1_present() && 288 (el_implemented(2) != EL_IMPL_NONE)) { 289 scr_el3 |= SCR_AMVOFFEN_BIT; 290 } 291 292 /* 293 * Initialise SCTLR_EL1 to the reset value corresponding to the target 294 * execution state setting all fields rather than relying of the hw. 295 * Some fields have architecturally UNKNOWN reset values and these are 296 * set to zero. 297 * 298 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 299 * 300 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 301 * required by PSCI specification) 302 */ 303 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 304 if (GET_RW(ep->spsr) == MODE_RW_64) { 305 sctlr_elx |= SCTLR_EL1_RES1; 306 } else { 307 /* 308 * If the target execution state is AArch32 then the following 309 * fields need to be set. 310 * 311 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 312 * instructions are not trapped to EL1. 313 * 314 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 315 * instructions are not trapped to EL1. 316 * 317 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 318 * CP15DMB, CP15DSB, and CP15ISB instructions. 319 */ 320 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 321 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 322 } 323 324 #if ERRATA_A75_764081 325 /* 326 * If workaround of errata 764081 for Cortex-A75 is used then set 327 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 328 */ 329 sctlr_elx |= SCTLR_IESB_BIT; 330 #endif 331 332 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 333 if (is_armv8_6_twed_present()) { 334 uint32_t delay = plat_arm_set_twedel_scr_el3(); 335 336 if (delay != TWED_DISABLED) { 337 /* Make sure delay value fits */ 338 assert((delay & ~SCR_TWEDEL_MASK) == 0U); 339 340 /* Set delay in SCR_EL3 */ 341 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 342 scr_el3 |= ((delay & SCR_TWEDEL_MASK) 343 << SCR_TWEDEL_SHIFT); 344 345 /* Enable WFE delay */ 346 scr_el3 |= SCR_TWEDEn_BIT; 347 } 348 } 349 350 /* 351 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 352 * and other EL2 registers are set up by cm_prepare_el3_exit() as they 353 * are not part of the stored cpu_context. 354 */ 355 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 356 357 /* 358 * Base the context ACTLR_EL1 on the current value, as it is 359 * implementation defined. The context restore process will write 360 * the value from the context to the actual register and can cause 361 * problems for processor cores that don't expect certain bits to 362 * be zero. 363 */ 364 actlr_elx = read_actlr_el1(); 365 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 366 367 /* 368 * Populate EL3 state so that we've the right context 369 * before doing ERET 370 */ 371 state = get_el3state_ctx(ctx); 372 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 373 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 374 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 375 376 /* 377 * Store the X0-X7 value from the entrypoint into the context 378 * Use memcpy as we are in control of the layout of the structures 379 */ 380 gp_regs = get_gpregs_ctx(ctx); 381 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 382 } 383 384 /******************************************************************************* 385 * Context management library initialization routine. This library is used by 386 * runtime services to share pointers to 'cpu_context' structures for secure 387 * non-secure and realm states. Management of the structures and their associated 388 * memory is not done by the context management library e.g. the PSCI service 389 * manages the cpu context used for entry from and exit to the non-secure state. 390 * The Secure payload dispatcher service manages the context(s) corresponding to 391 * the secure state. It also uses this library to get access to the non-secure 392 * state cpu context pointers. 393 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 394 * which will be used for programming an entry into a lower EL. The same context 395 * will be used to save state upon exception entry from that EL. 396 ******************************************************************************/ 397 void __init cm_init(void) 398 { 399 /* 400 * The context management library has only global data to intialize, but 401 * that will be done when the BSS is zeroed out. 402 */ 403 } 404 405 /******************************************************************************* 406 * This is the high-level function used to initialize the cpu_context 'ctx' for 407 * first use. It performs initializations that are common to all security states 408 * and initializations specific to the security state specified in 'ep' 409 ******************************************************************************/ 410 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 411 { 412 unsigned int security_state; 413 414 assert(ctx != NULL); 415 416 /* 417 * Perform initializations that are common 418 * to all security states 419 */ 420 setup_context_common(ctx, ep); 421 422 security_state = GET_SECURITY_STATE(ep->h.attr); 423 424 /* Perform security state specific initializations */ 425 switch (security_state) { 426 case SECURE: 427 setup_secure_context(ctx, ep); 428 break; 429 #if ENABLE_RME 430 case REALM: 431 setup_realm_context(ctx, ep); 432 break; 433 #endif 434 case NON_SECURE: 435 setup_ns_context(ctx, ep); 436 break; 437 default: 438 ERROR("Invalid security state\n"); 439 panic(); 440 break; 441 } 442 } 443 444 /******************************************************************************* 445 * Enable architecture extensions on first entry to Non-secure world. 446 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 447 * it is zero. 448 ******************************************************************************/ 449 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 450 { 451 #if IMAGE_BL31 452 #if ENABLE_SPE_FOR_LOWER_ELS 453 spe_enable(el2_unused); 454 #endif 455 456 #if ENABLE_AMU 457 amu_enable(el2_unused, ctx); 458 #endif 459 460 #if ENABLE_SME_FOR_NS 461 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 462 sme_enable(ctx); 463 #elif ENABLE_SVE_FOR_NS 464 /* Enable SVE and FPU/SIMD for non-secure world. */ 465 sve_enable(ctx); 466 #endif 467 468 #if ENABLE_MPAM_FOR_LOWER_ELS 469 mpam_enable(el2_unused); 470 #endif 471 472 #if ENABLE_TRBE_FOR_NS 473 trbe_enable(); 474 #endif /* ENABLE_TRBE_FOR_NS */ 475 476 #if ENABLE_SYS_REG_TRACE_FOR_NS 477 sys_reg_trace_enable(ctx); 478 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 479 480 #if ENABLE_TRF_FOR_NS 481 trf_enable(); 482 #endif /* ENABLE_TRF_FOR_NS */ 483 #endif 484 } 485 486 /******************************************************************************* 487 * Enable architecture extensions on first entry to Secure world. 488 ******************************************************************************/ 489 static void manage_extensions_secure(cpu_context_t *ctx) 490 { 491 #if IMAGE_BL31 492 #if ENABLE_SME_FOR_NS 493 #if ENABLE_SME_FOR_SWD 494 /* 495 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must 496 * ensure SME, SVE, and FPU/SIMD context properly managed. 497 */ 498 sme_enable(ctx); 499 #else /* ENABLE_SME_FOR_SWD */ 500 /* 501 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can 502 * safely use the associated registers. 503 */ 504 sme_disable(ctx); 505 #endif /* ENABLE_SME_FOR_SWD */ 506 #elif ENABLE_SVE_FOR_NS 507 #if ENABLE_SVE_FOR_SWD 508 /* 509 * Enable SVE and FPU in secure context, secure manager must ensure that 510 * the SVE and FPU register contexts are properly managed. 511 */ 512 sve_enable(ctx); 513 #else /* ENABLE_SVE_FOR_SWD */ 514 /* 515 * Disable SVE and FPU in secure context so non-secure world can safely 516 * use them. 517 */ 518 sve_disable(ctx); 519 #endif /* ENABLE_SVE_FOR_SWD */ 520 #endif /* ENABLE_SVE_FOR_NS */ 521 #endif /* IMAGE_BL31 */ 522 } 523 524 /******************************************************************************* 525 * The following function initializes the cpu_context for a CPU specified by 526 * its `cpu_idx` for first use, and sets the initial entrypoint state as 527 * specified by the entry_point_info structure. 528 ******************************************************************************/ 529 void cm_init_context_by_index(unsigned int cpu_idx, 530 const entry_point_info_t *ep) 531 { 532 cpu_context_t *ctx; 533 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 534 cm_setup_context(ctx, ep); 535 } 536 537 /******************************************************************************* 538 * The following function initializes the cpu_context for the current CPU 539 * for first use, and sets the initial entrypoint state as specified by the 540 * entry_point_info structure. 541 ******************************************************************************/ 542 void cm_init_my_context(const entry_point_info_t *ep) 543 { 544 cpu_context_t *ctx; 545 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 546 cm_setup_context(ctx, ep); 547 } 548 549 /******************************************************************************* 550 * Prepare the CPU system registers for first entry into realm, secure, or 551 * normal world. 552 * 553 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 554 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 555 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 556 * For all entries, the EL1 registers are initialized from the cpu_context 557 ******************************************************************************/ 558 void cm_prepare_el3_exit(uint32_t security_state) 559 { 560 u_register_t sctlr_elx, scr_el3, mdcr_el2; 561 cpu_context_t *ctx = cm_get_context(security_state); 562 bool el2_unused = false; 563 uint64_t hcr_el2 = 0U; 564 565 assert(ctx != NULL); 566 567 if (security_state == NON_SECURE) { 568 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 569 CTX_SCR_EL3); 570 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 571 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 572 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 573 CTX_SCTLR_EL1); 574 sctlr_elx &= SCTLR_EE_BIT; 575 sctlr_elx |= SCTLR_EL2_RES1; 576 #if ERRATA_A75_764081 577 /* 578 * If workaround of errata 764081 for Cortex-A75 is used 579 * then set SCTLR_EL2.IESB to enable Implicit Error 580 * Synchronization Barrier. 581 */ 582 sctlr_elx |= SCTLR_IESB_BIT; 583 #endif 584 write_sctlr_el2(sctlr_elx); 585 } else if (el_implemented(2) != EL_IMPL_NONE) { 586 el2_unused = true; 587 588 /* 589 * EL2 present but unused, need to disable safely. 590 * SCTLR_EL2 can be ignored in this case. 591 * 592 * Set EL2 register width appropriately: Set HCR_EL2 593 * field to match SCR_EL3.RW. 594 */ 595 if ((scr_el3 & SCR_RW_BIT) != 0U) 596 hcr_el2 |= HCR_RW_BIT; 597 598 /* 599 * For Armv8.3 pointer authentication feature, disable 600 * traps to EL2 when accessing key registers or using 601 * pointer authentication instructions from lower ELs. 602 */ 603 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 604 605 write_hcr_el2(hcr_el2); 606 607 /* 608 * Initialise CPTR_EL2 setting all fields rather than 609 * relying on the hw. All fields have architecturally 610 * UNKNOWN reset values. 611 * 612 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 613 * accesses to the CPACR_EL1 or CPACR from both 614 * Execution states do not trap to EL2. 615 * 616 * CPTR_EL2.TTA: Set to zero so that Non-secure System 617 * register accesses to the trace registers from both 618 * Execution states do not trap to EL2. 619 * If PE trace unit System registers are not implemented 620 * then this bit is reserved, and must be set to zero. 621 * 622 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 623 * to SIMD and floating-point functionality from both 624 * Execution states do not trap to EL2. 625 */ 626 write_cptr_el2(CPTR_EL2_RESET_VAL & 627 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 628 | CPTR_EL2_TFP_BIT)); 629 630 /* 631 * Initialise CNTHCTL_EL2. All fields are 632 * architecturally UNKNOWN on reset and are set to zero 633 * except for field(s) listed below. 634 * 635 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 636 * Hyp mode of Non-secure EL0 and EL1 accesses to the 637 * physical timer registers. 638 * 639 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 640 * Hyp mode of Non-secure EL0 and EL1 accesses to the 641 * physical counter registers. 642 */ 643 write_cnthctl_el2(CNTHCTL_RESET_VAL | 644 EL1PCEN_BIT | EL1PCTEN_BIT); 645 646 /* 647 * Initialise CNTVOFF_EL2 to zero as it resets to an 648 * architecturally UNKNOWN value. 649 */ 650 write_cntvoff_el2(0); 651 652 /* 653 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 654 * MPIDR_EL1 respectively. 655 */ 656 write_vpidr_el2(read_midr_el1()); 657 write_vmpidr_el2(read_mpidr_el1()); 658 659 /* 660 * Initialise VTTBR_EL2. All fields are architecturally 661 * UNKNOWN on reset. 662 * 663 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 664 * 2 address translation is disabled, cache maintenance 665 * operations depend on the VMID. 666 * 667 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 668 * translation is disabled. 669 */ 670 write_vttbr_el2(VTTBR_RESET_VAL & 671 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 672 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 673 674 /* 675 * Initialise MDCR_EL2, setting all fields rather than 676 * relying on hw. Some fields are architecturally 677 * UNKNOWN on reset. 678 * 679 * MDCR_EL2.HLP: Set to one so that event counter 680 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 681 * occurs on the increment that changes 682 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 683 * implemented. This bit is RES0 in versions of the 684 * architecture earlier than ARMv8.5, setting it to 1 685 * doesn't have any effect on them. 686 * 687 * MDCR_EL2.TTRF: Set to zero so that access to Trace 688 * Filter Control register TRFCR_EL1 at EL1 is not 689 * trapped to EL2. This bit is RES0 in versions of 690 * the architecture earlier than ARMv8.4. 691 * 692 * MDCR_EL2.HPMD: Set to one so that event counting is 693 * prohibited at EL2. This bit is RES0 in versions of 694 * the architecture earlier than ARMv8.1, setting it 695 * to 1 doesn't have any effect on them. 696 * 697 * MDCR_EL2.TPMS: Set to zero so that accesses to 698 * Statistical Profiling control registers from EL1 699 * do not trap to EL2. This bit is RES0 when SPE is 700 * not implemented. 701 * 702 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 703 * EL1 System register accesses to the Debug ROM 704 * registers are not trapped to EL2. 705 * 706 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 707 * System register accesses to the powerdown debug 708 * registers are not trapped to EL2. 709 * 710 * MDCR_EL2.TDA: Set to zero so that System register 711 * accesses to the debug registers do not trap to EL2. 712 * 713 * MDCR_EL2.TDE: Set to zero so that debug exceptions 714 * are not routed to EL2. 715 * 716 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 717 * Monitors. 718 * 719 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 720 * EL1 accesses to all Performance Monitors registers 721 * are not trapped to EL2. 722 * 723 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 724 * and EL1 accesses to the PMCR_EL0 or PMCR are not 725 * trapped to EL2. 726 * 727 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 728 * architecturally-defined reset value. 729 * 730 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 731 * owning exception level is NS-EL1 and, tracing is 732 * prohibited at NS-EL2. These bits are RES0 when 733 * FEAT_TRBE is not implemented. 734 */ 735 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 736 MDCR_EL2_HPMD) | 737 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 738 >> PMCR_EL0_N_SHIFT)) & 739 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 740 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 741 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 742 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 743 MDCR_EL2_TPMCR_BIT | 744 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 745 746 write_mdcr_el2(mdcr_el2); 747 748 /* 749 * Initialise HSTR_EL2. All fields are architecturally 750 * UNKNOWN on reset. 751 * 752 * HSTR_EL2.T<n>: Set all these fields to zero so that 753 * Non-secure EL0 or EL1 accesses to System registers 754 * do not trap to EL2. 755 */ 756 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 757 /* 758 * Initialise CNTHP_CTL_EL2. All fields are 759 * architecturally UNKNOWN on reset. 760 * 761 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 762 * physical timer and prevent timer interrupts. 763 */ 764 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 765 ~(CNTHP_CTL_ENABLE_BIT)); 766 } 767 manage_extensions_nonsecure(el2_unused, ctx); 768 } 769 770 cm_el1_sysregs_context_restore(security_state); 771 cm_set_next_eret_context(security_state); 772 } 773 774 #if CTX_INCLUDE_EL2_REGS 775 /******************************************************************************* 776 * Save EL2 sysreg context 777 ******************************************************************************/ 778 void cm_el2_sysregs_context_save(uint32_t security_state) 779 { 780 u_register_t scr_el3 = read_scr(); 781 782 /* 783 * Always save the non-secure and realm EL2 context, only save the 784 * S-EL2 context if S-EL2 is enabled. 785 */ 786 if ((security_state != SECURE) || 787 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 788 cpu_context_t *ctx; 789 790 ctx = cm_get_context(security_state); 791 assert(ctx != NULL); 792 793 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 794 } 795 } 796 797 /******************************************************************************* 798 * Restore EL2 sysreg context 799 ******************************************************************************/ 800 void cm_el2_sysregs_context_restore(uint32_t security_state) 801 { 802 u_register_t scr_el3 = read_scr(); 803 804 /* 805 * Always restore the non-secure and realm EL2 context, only restore the 806 * S-EL2 context if S-EL2 is enabled. 807 */ 808 if ((security_state != SECURE) || 809 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 810 cpu_context_t *ctx; 811 812 ctx = cm_get_context(security_state); 813 assert(ctx != NULL); 814 815 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 816 } 817 } 818 #endif /* CTX_INCLUDE_EL2_REGS */ 819 820 /******************************************************************************* 821 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 822 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 823 * updating EL1 and EL2 registers. Otherwise, it calls the generic 824 * cm_prepare_el3_exit function. 825 ******************************************************************************/ 826 void cm_prepare_el3_exit_ns(void) 827 { 828 #if CTX_INCLUDE_EL2_REGS 829 cpu_context_t *ctx = cm_get_context(NON_SECURE); 830 assert(ctx != NULL); 831 832 /* 833 * Currently some extensions are configured using 834 * direct register updates. Therefore, do this here 835 * instead of when setting up context. 836 */ 837 manage_extensions_nonsecure(0, ctx); 838 839 /* 840 * Set the NS bit to be able to access the ICC_SRE_EL2 841 * register when restoring context. 842 */ 843 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 844 845 /* Restore EL2 and EL1 sysreg contexts */ 846 cm_el2_sysregs_context_restore(NON_SECURE); 847 cm_el1_sysregs_context_restore(NON_SECURE); 848 cm_set_next_eret_context(NON_SECURE); 849 #else 850 cm_prepare_el3_exit(NON_SECURE); 851 #endif /* CTX_INCLUDE_EL2_REGS */ 852 } 853 854 /******************************************************************************* 855 * The next four functions are used by runtime services to save and restore 856 * EL1 context on the 'cpu_context' structure for the specified security 857 * state. 858 ******************************************************************************/ 859 void cm_el1_sysregs_context_save(uint32_t security_state) 860 { 861 cpu_context_t *ctx; 862 863 ctx = cm_get_context(security_state); 864 assert(ctx != NULL); 865 866 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 867 868 #if IMAGE_BL31 869 if (security_state == SECURE) 870 PUBLISH_EVENT(cm_exited_secure_world); 871 else 872 PUBLISH_EVENT(cm_exited_normal_world); 873 #endif 874 } 875 876 void cm_el1_sysregs_context_restore(uint32_t security_state) 877 { 878 cpu_context_t *ctx; 879 880 ctx = cm_get_context(security_state); 881 assert(ctx != NULL); 882 883 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 884 885 #if IMAGE_BL31 886 if (security_state == SECURE) 887 PUBLISH_EVENT(cm_entering_secure_world); 888 else 889 PUBLISH_EVENT(cm_entering_normal_world); 890 #endif 891 } 892 893 /******************************************************************************* 894 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 895 * given security state with the given entrypoint 896 ******************************************************************************/ 897 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 898 { 899 cpu_context_t *ctx; 900 el3_state_t *state; 901 902 ctx = cm_get_context(security_state); 903 assert(ctx != NULL); 904 905 /* Populate EL3 state so that ERET jumps to the correct entry */ 906 state = get_el3state_ctx(ctx); 907 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 908 } 909 910 /******************************************************************************* 911 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 912 * pertaining to the given security state 913 ******************************************************************************/ 914 void cm_set_elr_spsr_el3(uint32_t security_state, 915 uintptr_t entrypoint, uint32_t spsr) 916 { 917 cpu_context_t *ctx; 918 el3_state_t *state; 919 920 ctx = cm_get_context(security_state); 921 assert(ctx != NULL); 922 923 /* Populate EL3 state so that ERET jumps to the correct entry */ 924 state = get_el3state_ctx(ctx); 925 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 926 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 927 } 928 929 /******************************************************************************* 930 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 931 * pertaining to the given security state using the value and bit position 932 * specified in the parameters. It preserves all other bits. 933 ******************************************************************************/ 934 void cm_write_scr_el3_bit(uint32_t security_state, 935 uint32_t bit_pos, 936 uint32_t value) 937 { 938 cpu_context_t *ctx; 939 el3_state_t *state; 940 u_register_t scr_el3; 941 942 ctx = cm_get_context(security_state); 943 assert(ctx != NULL); 944 945 /* Ensure that the bit position is a valid one */ 946 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 947 948 /* Ensure that the 'value' is only a bit wide */ 949 assert(value <= 1U); 950 951 /* 952 * Get the SCR_EL3 value from the cpu context, clear the desired bit 953 * and set it to its new value. 954 */ 955 state = get_el3state_ctx(ctx); 956 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 957 scr_el3 &= ~(1UL << bit_pos); 958 scr_el3 |= (u_register_t)value << bit_pos; 959 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 960 } 961 962 /******************************************************************************* 963 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 964 * given security state. 965 ******************************************************************************/ 966 u_register_t cm_get_scr_el3(uint32_t security_state) 967 { 968 cpu_context_t *ctx; 969 el3_state_t *state; 970 971 ctx = cm_get_context(security_state); 972 assert(ctx != NULL); 973 974 /* Populate EL3 state so that ERET jumps to the correct entry */ 975 state = get_el3state_ctx(ctx); 976 return read_ctx_reg(state, CTX_SCR_EL3); 977 } 978 979 /******************************************************************************* 980 * This function is used to program the context that's used for exception 981 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 982 * the required security state 983 ******************************************************************************/ 984 void cm_set_next_eret_context(uint32_t security_state) 985 { 986 cpu_context_t *ctx; 987 988 ctx = cm_get_context(security_state); 989 assert(ctx != NULL); 990 991 cm_set_next_context(ctx); 992 } 993