1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pauth.h> 34 #include <lib/extensions/pmuv3.h> 35 #include <lib/extensions/sme.h> 36 #include <lib/extensions/spe.h> 37 #include <lib/extensions/sve.h> 38 #include <lib/extensions/sysreg128.h> 39 #include <lib/extensions/sys_reg_trace.h> 40 #include <lib/extensions/tcr2.h> 41 #include <lib/extensions/trbe.h> 42 #include <lib/extensions/trf.h> 43 #include <lib/utils.h> 44 45 #if ENABLE_FEAT_TWED 46 /* Make sure delay value fits within the range(0-15) */ 47 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 48 #endif /* ENABLE_FEAT_TWED */ 49 50 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 51 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 55 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 56 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 57 { 58 u_register_t sctlr_elx, actlr_elx; 59 60 /* 61 * Initialise SCTLR_EL1 to the reset value corresponding to the target 62 * execution state setting all fields rather than relying on the hw. 63 * Some fields have architecturally UNKNOWN reset values and these are 64 * set to zero. 65 * 66 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 67 * 68 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 69 * required by PSCI specification) 70 */ 71 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 72 if (GET_RW(ep->spsr) == MODE_RW_64) { 73 sctlr_elx |= SCTLR_EL1_RES1; 74 } else { 75 /* 76 * If the target execution state is AArch32 then the following 77 * fields need to be set. 78 * 79 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 80 * instructions are not trapped to EL1. 81 * 82 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 83 * instructions are not trapped to EL1. 84 * 85 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 86 * CP15DMB, CP15DSB, and CP15ISB instructions. 87 */ 88 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 89 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 90 } 91 92 /* 93 * If workaround of errata 764081 for Cortex-A75 is used then set 94 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 95 */ 96 if (errata_a75_764081_applies()) { 97 sctlr_elx |= SCTLR_IESB_BIT; 98 } 99 100 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 101 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 102 103 /* 104 * Base the context ACTLR_EL1 on the current value, as it is 105 * implementation defined. The context restore process will write 106 * the value from the context to the actual register and can cause 107 * problems for processor cores that don't expect certain bits to 108 * be zero. 109 */ 110 actlr_elx = read_actlr_el1(); 111 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 112 } 113 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 114 115 /****************************************************************************** 116 * This function performs initializations that are specific to SECURE state 117 * and updates the cpu context specified by 'ctx'. 118 *****************************************************************************/ 119 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 120 { 121 u_register_t scr_el3; 122 el3_state_t *state; 123 124 state = get_el3state_ctx(ctx); 125 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 126 127 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 128 /* 129 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 130 * indicated by the interrupt routing model for BL31. 131 */ 132 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 133 #endif 134 135 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 136 if (is_feat_mte2_supported()) { 137 scr_el3 |= SCR_ATA_BIT; 138 } 139 140 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 141 142 /* 143 * Initialize EL1 context registers unless SPMC is running 144 * at S-EL2. 145 */ 146 #if (!SPMD_SPM_AT_SEL2) 147 setup_el1_context(ctx, ep); 148 #endif 149 150 manage_extensions_secure(ctx); 151 } 152 153 #if ENABLE_RME && IMAGE_BL31 154 /****************************************************************************** 155 * This function performs initializations that are specific to REALM state 156 * and updates the cpu context specified by 'ctx'. 157 * 158 * NOTE: any changes to this function must be verified by an RMMD maintainer. 159 *****************************************************************************/ 160 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 161 { 162 u_register_t scr_el3; 163 el3_state_t *state; 164 el2_sysregs_t *el2_ctx; 165 166 state = get_el3state_ctx(ctx); 167 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 168 el2_ctx = get_el2_sysregs_ctx(ctx); 169 170 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 171 172 write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM); 173 174 /* CSV2 version 2 and above */ 175 if (is_feat_csv2_2_supported()) { 176 /* Enable access to the SCXTNUM_ELx registers. */ 177 scr_el3 |= SCR_EnSCXT_BIT; 178 } 179 180 if (is_feat_sctlr2_supported()) { 181 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 182 * SCTLR2_ELx registers. 183 */ 184 scr_el3 |= SCR_SCTLR2En_BIT; 185 } 186 187 if (is_feat_d128_supported()) { 188 /* 189 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 190 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 191 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 192 */ 193 scr_el3 |= SCR_D128En_BIT; 194 } 195 196 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 197 198 if (is_feat_fgt2_supported()) { 199 fgt2_enable(ctx); 200 } 201 202 if (is_feat_debugv8p9_supported()) { 203 debugv8p9_extended_bp_wp_enable(ctx); 204 } 205 206 if (is_feat_brbe_supported()) { 207 brbe_enable(ctx); 208 } 209 210 /* 211 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world. 212 */ 213 if (is_feat_sme_supported()) { 214 sme_enable(ctx); 215 } 216 217 /* 218 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 219 * sysreg access can. In case the EL1 controls leave them active on 220 * context switch, we want the owning security state to be NS so Realm 221 * can't be DOSed. 222 */ 223 if (is_feat_spe_supported()) { 224 spe_disable(ctx); 225 } 226 227 if (is_feat_trbe_supported()) { 228 trbe_disable(ctx); 229 } 230 } 231 #endif /* ENABLE_RME && IMAGE_BL31 */ 232 233 /****************************************************************************** 234 * This function performs initializations that are specific to NON-SECURE state 235 * and updates the cpu context specified by 'ctx'. 236 *****************************************************************************/ 237 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 238 { 239 u_register_t scr_el3; 240 el3_state_t *state; 241 242 state = get_el3state_ctx(ctx); 243 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 244 245 /* SCR_NS: Set the NS bit */ 246 scr_el3 |= SCR_NS_BIT; 247 248 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 249 if (is_feat_mte2_supported()) { 250 scr_el3 |= SCR_ATA_BIT; 251 } 252 253 /* 254 * Pointer Authentication feature, if present, is always enabled by 255 * default for Non secure lower exception levels. We do not have an 256 * explicit flag to set it. To prevent the leakage between the worlds 257 * during world switch, we enable it only for the non-secure world. 258 * 259 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 260 * exception levels of secure and realm worlds. 261 * 262 * If the Secure/realm world wants to use pointer authentication, 263 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 264 * it will be enabled globally for all the contexts. 265 * 266 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 267 * other than EL3 268 * 269 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 270 * than EL3 271 */ 272 if (!is_ctx_pauth_supported()) { 273 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 274 } 275 276 #if HANDLE_EA_EL3_FIRST_NS 277 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 278 scr_el3 |= SCR_EA_BIT; 279 #endif 280 281 #if RAS_TRAP_NS_ERR_REC_ACCESS 282 /* 283 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 284 * and RAS ERX registers from EL1 and EL2(from any security state) 285 * are trapped to EL3. 286 * Set here to trap only for NS EL1/EL2 287 */ 288 scr_el3 |= SCR_TERR_BIT; 289 #endif 290 291 /* CSV2 version 2 and above */ 292 if (is_feat_csv2_2_supported()) { 293 /* Enable access to the SCXTNUM_ELx registers. */ 294 scr_el3 |= SCR_EnSCXT_BIT; 295 } 296 297 #ifdef IMAGE_BL31 298 /* 299 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 300 * indicated by the interrupt routing model for BL31. 301 */ 302 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 303 #endif 304 305 if (is_feat_the_supported()) { 306 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 307 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 308 */ 309 scr_el3 |= SCR_RCWMASKEn_BIT; 310 } 311 312 if (is_feat_sctlr2_supported()) { 313 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 314 * SCTLR2_ELx registers. 315 */ 316 scr_el3 |= SCR_SCTLR2En_BIT; 317 } 318 319 if (is_feat_d128_supported()) { 320 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 321 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 322 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 323 */ 324 scr_el3 |= SCR_D128En_BIT; 325 } 326 327 if (is_feat_fpmr_supported()) { 328 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 329 * register. 330 */ 331 scr_el3 |= SCR_EnFPM_BIT; 332 } 333 334 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 335 336 /* Initialize EL2 context registers */ 337 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 338 if (is_feat_hcx_supported()) { 339 /* 340 * Initialize register HCRX_EL2 with its init value. 341 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 342 * chance that this can lead to unexpected behavior in lower 343 * ELs that have not been updated since the introduction of 344 * this feature if not properly initialized, especially when 345 * it comes to those bits that enable/disable traps. 346 */ 347 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 348 HCRX_EL2_INIT_VAL); 349 } 350 351 if (is_feat_fgt_supported()) { 352 /* 353 * Initialize HFG*_EL2 registers with a default value so legacy 354 * systems unaware of FEAT_FGT do not get trapped due to their lack 355 * of initialization for this feature. 356 */ 357 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 358 HFGITR_EL2_INIT_VAL); 359 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 360 HFGRTR_EL2_INIT_VAL); 361 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 362 HFGWTR_EL2_INIT_VAL); 363 } 364 #else 365 /* Initialize EL1 context registers */ 366 setup_el1_context(ctx, ep); 367 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 368 369 manage_extensions_nonsecure(ctx); 370 } 371 372 /******************************************************************************* 373 * The following function performs initialization of the cpu_context 'ctx' 374 * for first use that is common to all security states, and sets the 375 * initial entrypoint state as specified by the entry_point_info structure. 376 * 377 * The EE and ST attributes are used to configure the endianness and secure 378 * timer availability for the new execution context. 379 ******************************************************************************/ 380 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 381 { 382 u_register_t scr_el3; 383 u_register_t mdcr_el3; 384 el3_state_t *state; 385 gp_regs_t *gp_regs; 386 387 state = get_el3state_ctx(ctx); 388 389 /* Clear any residual register values from the context */ 390 zeromem(ctx, sizeof(*ctx)); 391 392 /* 393 * The lower-EL context is zeroed so that no stale values leak to a world. 394 * It is assumed that an all-zero lower-EL context is good enough for it 395 * to boot correctly. However, there are very few registers where this 396 * is not true and some values need to be recreated. 397 */ 398 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 399 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 400 401 /* 402 * These bits are set in the gicv3 driver. Losing them (especially the 403 * SRE bit) is problematic for all worlds. Henceforth recreate them. 404 */ 405 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 406 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 407 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 408 409 /* 410 * The actlr_el2 register can be initialized in platform's reset handler 411 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 412 */ 413 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 414 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 415 416 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 417 scr_el3 = SCR_RESET_VAL; 418 419 /* 420 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 421 * EL2, EL1 and EL0 are not trapped to EL3. 422 * 423 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 424 * EL2, EL1 and EL0 are not trapped to EL3. 425 * 426 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 427 * both Security states and both Execution states. 428 * 429 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 430 * Non-secure memory. 431 */ 432 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 433 434 scr_el3 |= SCR_SIF_BIT; 435 436 /* 437 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 438 * Exception level as specified by SPSR. 439 */ 440 if (GET_RW(ep->spsr) == MODE_RW_64) { 441 scr_el3 |= SCR_RW_BIT; 442 } 443 444 /* 445 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 446 * Secure timer registers to EL3, from AArch64 state only, if specified 447 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 448 * bit always behaves as 1 (i.e. secure physical timer register access 449 * is not trapped) 450 */ 451 if (EP_GET_ST(ep->h.attr) != 0U) { 452 scr_el3 |= SCR_ST_BIT; 453 } 454 455 /* 456 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 457 * SCR_EL3.HXEn. 458 */ 459 if (is_feat_hcx_supported()) { 460 scr_el3 |= SCR_HXEn_BIT; 461 } 462 463 /* 464 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 465 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 466 * SCR_EL3.EnAS0. 467 */ 468 if (is_feat_ls64_accdata_supported()) { 469 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 470 } 471 472 /* 473 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 474 * registers are trapped to EL3. 475 */ 476 if (is_feat_rng_trap_supported()) { 477 scr_el3 |= SCR_TRNDR_BIT; 478 } 479 480 #if FAULT_INJECTION_SUPPORT 481 /* Enable fault injection from lower ELs */ 482 scr_el3 |= SCR_FIEN_BIT; 483 #endif 484 485 /* 486 * Enable Pointer Authentication globally for all the worlds. 487 * 488 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 489 * other than EL3 490 * 491 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 492 * than EL3 493 */ 494 if (is_ctx_pauth_supported()) { 495 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 496 } 497 498 /* 499 * SCR_EL3.PIEN: Enable permission indirection and overlay 500 * registers for AArch64 if present. 501 */ 502 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 503 scr_el3 |= SCR_PIEN_BIT; 504 } 505 506 /* 507 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 508 */ 509 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 510 scr_el3 |= SCR_GCSEn_BIT; 511 } 512 513 /* 514 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 515 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 516 * next mode is Hyp. 517 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 518 * same conditions as HVC instructions and when the processor supports 519 * ARMv8.6-FGT. 520 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 521 * CNTPOFF_EL2 register under the same conditions as HVC instructions 522 * and when the processor supports ECV. 523 */ 524 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 525 || ((GET_RW(ep->spsr) != MODE_RW_64) 526 && (GET_M32(ep->spsr) == MODE32_hyp))) { 527 scr_el3 |= SCR_HCE_BIT; 528 529 if (is_feat_fgt_supported()) { 530 scr_el3 |= SCR_FGTEN_BIT; 531 } 532 533 if (is_feat_ecv_supported()) { 534 scr_el3 |= SCR_ECVEN_BIT; 535 } 536 } 537 538 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 539 if (is_feat_twed_supported()) { 540 /* Set delay in SCR_EL3 */ 541 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 542 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 543 << SCR_TWEDEL_SHIFT); 544 545 /* Enable WFE delay */ 546 scr_el3 |= SCR_TWEDEn_BIT; 547 } 548 549 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 550 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 551 if (is_feat_sel2_supported()) { 552 scr_el3 |= SCR_EEL2_BIT; 553 } 554 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 555 556 if (is_feat_mec_supported()) { 557 scr_el3 |= SCR_MECEn_BIT; 558 } 559 560 /* 561 * Populate EL3 state so that we've the right context 562 * before doing ERET 563 */ 564 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 565 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 566 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 567 568 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 569 mdcr_el3 = MDCR_EL3_RESET_VAL; 570 571 /* --------------------------------------------------------------------- 572 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 573 * Some fields are architecturally UNKNOWN on reset. 574 * 575 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 576 * Debug exceptions, other than Breakpoint Instruction exceptions, are 577 * disabled from all ELs in Secure state. 578 * 579 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 580 * privileged debug from S-EL1. 581 * 582 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 583 * access to the powerdown debug registers do not trap to EL3. 584 * 585 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 586 * debug registers, other than those registers that are controlled by 587 * MDCR_EL3.TDOSA. 588 */ 589 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 590 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 591 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 592 593 #if IMAGE_BL31 594 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 595 if (is_feat_trf_supported()) { 596 trf_enable(ctx); 597 } 598 599 if (is_feat_tcr2_supported()) { 600 tcr2_enable(ctx); 601 } 602 603 pmuv3_enable(ctx); 604 605 #if CTX_INCLUDE_EL2_REGS 606 /* 607 * Initialize SCTLR_EL2 context register with reset value. 608 */ 609 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 610 #endif /* CTX_INCLUDE_EL2_REGS */ 611 #endif /* IMAGE_BL31 */ 612 613 /* 614 * Store the X0-X7 value from the entrypoint into the context 615 * Use memcpy as we are in control of the layout of the structures 616 */ 617 gp_regs = get_gpregs_ctx(ctx); 618 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 619 } 620 621 /******************************************************************************* 622 * Context management library initialization routine. This library is used by 623 * runtime services to share pointers to 'cpu_context' structures for secure 624 * non-secure and realm states. Management of the structures and their associated 625 * memory is not done by the context management library e.g. the PSCI service 626 * manages the cpu context used for entry from and exit to the non-secure state. 627 * The Secure payload dispatcher service manages the context(s) corresponding to 628 * the secure state. It also uses this library to get access to the non-secure 629 * state cpu context pointers. 630 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 631 * which will be used for programming an entry into a lower EL. The same context 632 * will be used to save state upon exception entry from that EL. 633 ******************************************************************************/ 634 void __init cm_init(void) 635 { 636 /* 637 * The context management library has only global data to initialize, but 638 * that will be done when the BSS is zeroed out. 639 */ 640 } 641 642 /******************************************************************************* 643 * This is the high-level function used to initialize the cpu_context 'ctx' for 644 * first use. It performs initializations that are common to all security states 645 * and initializations specific to the security state specified in 'ep' 646 ******************************************************************************/ 647 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 648 { 649 size_t security_state; 650 651 assert(ctx != NULL); 652 653 /* 654 * Perform initializations that are common 655 * to all security states 656 */ 657 setup_context_common(ctx, ep); 658 659 security_state = GET_SECURITY_STATE(ep->h.attr); 660 661 /* Perform security state specific initializations */ 662 switch (security_state) { 663 case SECURE: 664 setup_secure_context(ctx, ep); 665 break; 666 #if ENABLE_RME && IMAGE_BL31 667 case REALM: 668 setup_realm_context(ctx, ep); 669 break; 670 #endif 671 case NON_SECURE: 672 setup_ns_context(ctx, ep); 673 break; 674 default: 675 ERROR("Invalid security state\n"); 676 panic(); 677 break; 678 } 679 } 680 681 /******************************************************************************* 682 * Enable architecture extensions for EL3 execution. This function only updates 683 * registers in-place which are expected to either never change or be 684 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 685 ******************************************************************************/ 686 #if IMAGE_BL31 687 void cm_manage_extensions_el3(unsigned int my_idx) 688 { 689 if (is_feat_sve_supported()) { 690 sve_init_el3(); 691 } 692 693 if (is_feat_amu_supported()) { 694 amu_init_el3(my_idx); 695 } 696 697 if (is_feat_sme_supported()) { 698 sme_init_el3(); 699 } 700 701 if (is_feat_fgwte3_supported()) { 702 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL); 703 } 704 pmuv3_init_el3(); 705 } 706 707 /****************************************************************************** 708 * Function to initialise the registers with the RESET values in the context 709 * memory, which are maintained per world. 710 ******************************************************************************/ 711 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 712 { 713 /* 714 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 715 * 716 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 717 * by Advanced SIMD, floating-point or SVE instructions (if 718 * implemented) do not trap to EL3. 719 * 720 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 721 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 722 */ 723 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 724 725 per_world_ctx->ctx_cptr_el3 = cptr_el3; 726 727 /* 728 * Initialize MPAM3_EL3 to its default reset value 729 * 730 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 731 * all lower ELn MPAM3_EL3 register access to, trap to EL3 732 */ 733 734 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 735 } 736 737 /******************************************************************************* 738 * Initialise per_world_context for Non-Secure world. 739 * This function enables the architecture extensions, which have same value 740 * across the cores for the non-secure world. 741 ******************************************************************************/ 742 static void manage_extensions_nonsecure_per_world(void) 743 { 744 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 745 746 if (is_feat_sme_supported()) { 747 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 748 } 749 750 if (is_feat_sve_supported()) { 751 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 752 } 753 754 if (is_feat_amu_supported()) { 755 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 756 } 757 758 if (is_feat_sys_reg_trace_supported()) { 759 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 760 } 761 762 if (is_feat_mpam_supported()) { 763 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 764 } 765 766 if (is_feat_fpmr_supported()) { 767 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 768 } 769 } 770 771 /******************************************************************************* 772 * Initialise per_world_context for Secure world. 773 * This function enables the architecture extensions, which have same value 774 * across the cores for the secure world. 775 ******************************************************************************/ 776 static void manage_extensions_secure_per_world(void) 777 { 778 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 779 780 if (is_feat_sme_supported()) { 781 782 if (ENABLE_SME_FOR_SWD) { 783 /* 784 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 785 * SME, SVE, and FPU/SIMD context properly managed. 786 */ 787 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 788 } else { 789 /* 790 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 791 * world can safely use the associated registers. 792 */ 793 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 794 } 795 } 796 if (is_feat_sve_supported()) { 797 if (ENABLE_SVE_FOR_SWD) { 798 /* 799 * Enable SVE and FPU in secure context, SPM must ensure 800 * that the SVE and FPU register contexts are properly managed. 801 */ 802 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 803 } else { 804 /* 805 * Disable SVE and FPU in secure context so non-secure world 806 * can safely use them. 807 */ 808 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 809 } 810 } 811 812 /* NS can access this but Secure shouldn't */ 813 if (is_feat_sys_reg_trace_supported()) { 814 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 815 } 816 } 817 818 static void manage_extensions_realm_per_world(void) 819 { 820 #if ENABLE_RME 821 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 822 823 if (is_feat_sve_supported()) { 824 /* 825 * Enable SVE and FPU in realm context when it is enabled for NS. 826 * Realm manager must ensure that the SVE and FPU register 827 * contexts are properly managed. 828 */ 829 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 830 } 831 832 /* NS can access this but Realm shouldn't */ 833 if (is_feat_sys_reg_trace_supported()) { 834 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 835 } 836 837 /* 838 * If SME/SME2 is supported and enabled for NS world, then disable trapping 839 * of SME instructions for Realm world. RMM will save/restore required 840 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 841 */ 842 if (is_feat_sme_supported()) { 843 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 844 } 845 846 /* 847 * If FEAT_MPAM is supported and enabled, then disable trapping access 848 * to the MPAM registers for Realm world. Instead, RMM will configure 849 * the access to be trapped by itself so it can inject undefined aborts 850 * back to the Realm. 851 */ 852 if (is_feat_mpam_supported()) { 853 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 854 } 855 #endif /* ENABLE_RME */ 856 } 857 858 void cm_manage_extensions_per_world(void) 859 { 860 manage_extensions_nonsecure_per_world(); 861 manage_extensions_secure_per_world(); 862 manage_extensions_realm_per_world(); 863 } 864 #endif /* IMAGE_BL31 */ 865 866 /******************************************************************************* 867 * Enable architecture extensions on first entry to Non-secure world. 868 ******************************************************************************/ 869 static void manage_extensions_nonsecure(cpu_context_t *ctx) 870 { 871 #if IMAGE_BL31 872 /* NOTE: registers are not context switched */ 873 if (is_feat_amu_supported()) { 874 amu_enable(ctx); 875 } 876 877 if (is_feat_sme_supported()) { 878 sme_enable(ctx); 879 } 880 881 if (is_feat_fgt2_supported()) { 882 fgt2_enable(ctx); 883 } 884 885 if (is_feat_debugv8p9_supported()) { 886 debugv8p9_extended_bp_wp_enable(ctx); 887 } 888 889 /* 890 * SPE, TRBE, and BRBE have multi-field enables that affect which world 891 * they apply to. Despite this, it is useful to ignore these for 892 * simplicity in determining the feature's per world enablement status. 893 * This is only possible when context is written per-world. Relied on 894 * by SMCCC_ARCH_FEATURE_AVAILABILITY 895 */ 896 if (is_feat_spe_supported()) { 897 spe_enable(ctx); 898 } 899 900 if (!check_if_trbe_disable_affected_core()) { 901 if (is_feat_trbe_supported()) { 902 trbe_enable(ctx); 903 } 904 } 905 906 if (is_feat_brbe_supported()) { 907 brbe_enable(ctx); 908 } 909 #endif /* IMAGE_BL31 */ 910 } 911 912 #if INIT_UNUSED_NS_EL2 913 /******************************************************************************* 914 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 915 * world when EL2 is empty and unused. 916 ******************************************************************************/ 917 static void manage_extensions_nonsecure_el2_unused(void) 918 { 919 #if IMAGE_BL31 920 if (is_feat_spe_supported()) { 921 spe_init_el2_unused(); 922 } 923 924 if (is_feat_amu_supported()) { 925 amu_init_el2_unused(); 926 } 927 928 if (is_feat_mpam_supported()) { 929 mpam_init_el2_unused(); 930 } 931 932 if (is_feat_trbe_supported()) { 933 trbe_init_el2_unused(); 934 } 935 936 if (is_feat_sys_reg_trace_supported()) { 937 sys_reg_trace_init_el2_unused(); 938 } 939 940 if (is_feat_trf_supported()) { 941 trf_init_el2_unused(); 942 } 943 944 pmuv3_init_el2_unused(); 945 946 if (is_feat_sve_supported()) { 947 sve_init_el2_unused(); 948 } 949 950 if (is_feat_sme_supported()) { 951 sme_init_el2_unused(); 952 } 953 954 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 955 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 956 } 957 958 if (is_feat_pauth_supported()) { 959 pauth_enable_el2(); 960 } 961 #endif /* IMAGE_BL31 */ 962 } 963 #endif /* INIT_UNUSED_NS_EL2 */ 964 965 /******************************************************************************* 966 * Enable architecture extensions on first entry to Secure world. 967 ******************************************************************************/ 968 static void manage_extensions_secure(cpu_context_t *ctx) 969 { 970 #if IMAGE_BL31 971 if (is_feat_sme_supported()) { 972 if (ENABLE_SME_FOR_SWD) { 973 /* 974 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 975 * must ensure SME, SVE, and FPU/SIMD context properly managed. 976 */ 977 sme_init_el3(); 978 sme_enable(ctx); 979 } else { 980 /* 981 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 982 * world can safely use the associated registers. 983 */ 984 sme_disable(ctx); 985 } 986 } 987 988 /* 989 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 990 * sysreg access can. In case the EL1 controls leave them active on 991 * context switch, we want the owning security state to be NS so Secure 992 * can't be DOSed. 993 */ 994 if (is_feat_spe_supported()) { 995 spe_disable(ctx); 996 } 997 998 if (is_feat_trbe_supported()) { 999 trbe_disable(ctx); 1000 } 1001 #endif /* IMAGE_BL31 */ 1002 } 1003 1004 /******************************************************************************* 1005 * The following function initializes the cpu_context for the current CPU 1006 * for first use, and sets the initial entrypoint state as specified by the 1007 * entry_point_info structure. 1008 ******************************************************************************/ 1009 void cm_init_my_context(const entry_point_info_t *ep) 1010 { 1011 cpu_context_t *ctx; 1012 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 1013 cm_setup_context(ctx, ep); 1014 } 1015 1016 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 1017 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 1018 { 1019 #if INIT_UNUSED_NS_EL2 1020 u_register_t hcr_el2 = HCR_RESET_VAL; 1021 u_register_t mdcr_el2; 1022 u_register_t scr_el3; 1023 1024 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1025 1026 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 1027 if ((scr_el3 & SCR_RW_BIT) != 0U) { 1028 hcr_el2 |= HCR_RW_BIT; 1029 } 1030 1031 write_hcr_el2(hcr_el2); 1032 1033 /* 1034 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1035 * All fields have architecturally UNKNOWN reset values. 1036 */ 1037 write_cptr_el2(CPTR_EL2_RESET_VAL); 1038 1039 /* 1040 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1041 * reset and are set to zero except for field(s) listed below. 1042 * 1043 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1044 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1045 * 1046 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1047 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1048 */ 1049 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1050 1051 /* 1052 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1053 * UNKNOWN value. 1054 */ 1055 write_cntvoff_el2(0); 1056 1057 /* 1058 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1059 * respectively. 1060 */ 1061 write_vpidr_el2(read_midr_el1()); 1062 write_vmpidr_el2(read_mpidr_el1()); 1063 1064 /* 1065 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1066 * 1067 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1068 * translation is disabled, cache maintenance operations depend on the 1069 * VMID. 1070 * 1071 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1072 * disabled. 1073 */ 1074 write_vttbr_el2(VTTBR_RESET_VAL & 1075 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1076 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1077 1078 /* 1079 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1080 * Some fields are architecturally UNKNOWN on reset. 1081 * 1082 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1083 * register accesses to the Debug ROM registers are not trapped to EL2. 1084 * 1085 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1086 * accesses to the powerdown debug registers are not trapped to EL2. 1087 * 1088 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1089 * debug registers do not trap to EL2. 1090 * 1091 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1092 * EL2. 1093 */ 1094 mdcr_el2 = MDCR_EL2_RESET_VAL & 1095 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1096 MDCR_EL2_TDE_BIT); 1097 1098 write_mdcr_el2(mdcr_el2); 1099 1100 /* 1101 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1102 * 1103 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1104 * EL1 accesses to System registers do not trap to EL2. 1105 */ 1106 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1107 1108 /* 1109 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1110 * reset. 1111 * 1112 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1113 * and prevent timer interrupts. 1114 */ 1115 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1116 1117 manage_extensions_nonsecure_el2_unused(); 1118 #endif /* INIT_UNUSED_NS_EL2 */ 1119 } 1120 1121 /******************************************************************************* 1122 * Prepare the CPU system registers for first entry into realm, secure, or 1123 * normal world. 1124 * 1125 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1126 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1127 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1128 * For all entries, the EL1 registers are initialized from the cpu_context 1129 ******************************************************************************/ 1130 void cm_prepare_el3_exit(size_t security_state) 1131 { 1132 u_register_t sctlr_el2, scr_el3; 1133 cpu_context_t *ctx = cm_get_context(security_state); 1134 1135 assert(ctx != NULL); 1136 1137 if (security_state == NON_SECURE) { 1138 uint64_t el2_implemented = el_implemented(2); 1139 1140 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1141 CTX_SCR_EL3); 1142 1143 if (el2_implemented != EL_IMPL_NONE) { 1144 1145 /* 1146 * If context is not being used for EL2, initialize 1147 * HCRX_EL2 with its init value here. 1148 */ 1149 if (is_feat_hcx_supported()) { 1150 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1151 } 1152 1153 /* 1154 * Initialize Fine-grained trap registers introduced 1155 * by FEAT_FGT so all traps are initially disabled when 1156 * switching to EL2 or a lower EL, preventing undesired 1157 * behavior. 1158 */ 1159 if (is_feat_fgt_supported()) { 1160 /* 1161 * Initialize HFG*_EL2 registers with a default 1162 * value so legacy systems unaware of FEAT_FGT 1163 * do not get trapped due to their lack of 1164 * initialization for this feature. 1165 */ 1166 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1167 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1168 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1169 } 1170 1171 /* Condition to ensure EL2 is being used. */ 1172 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1173 /* Initialize SCTLR_EL2 register with reset value. */ 1174 sctlr_el2 = SCTLR_EL2_RES1; 1175 1176 /* 1177 * If workaround of errata 764081 for Cortex-A75 1178 * is used then set SCTLR_EL2.IESB to enable 1179 * Implicit Error Synchronization Barrier. 1180 */ 1181 if (errata_a75_764081_applies()) { 1182 sctlr_el2 |= SCTLR_IESB_BIT; 1183 } 1184 1185 write_sctlr_el2(sctlr_el2); 1186 } else { 1187 /* 1188 * (scr_el3 & SCR_HCE_BIT==0) 1189 * EL2 implemented but unused. 1190 */ 1191 init_nonsecure_el2_unused(ctx); 1192 } 1193 } 1194 1195 if (is_feat_fgwte3_supported()) { 1196 /* 1197 * TCR_EL3 and ACTLR_EL3 could be overwritten 1198 * by platforms and hence is locked a bit late. 1199 */ 1200 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL); 1201 } 1202 } 1203 #if (!CTX_INCLUDE_EL2_REGS) 1204 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1205 cm_el1_sysregs_context_restore(security_state); 1206 #endif 1207 cm_set_next_eret_context(security_state); 1208 } 1209 1210 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1211 1212 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1213 { 1214 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1215 if (is_feat_amu_supported()) { 1216 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1217 } 1218 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1219 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1220 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1221 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1222 } 1223 1224 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1225 { 1226 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1227 if (is_feat_amu_supported()) { 1228 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1229 } 1230 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1231 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1232 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1233 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1234 } 1235 1236 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1237 { 1238 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1239 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1240 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1241 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1242 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1243 } 1244 1245 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1246 { 1247 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1248 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1249 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1250 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1251 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1252 } 1253 1254 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1255 { 1256 u_register_t mpam_idr = read_mpamidr_el1(); 1257 1258 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1259 1260 /* 1261 * The context registers that we intend to save would be part of the 1262 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1263 */ 1264 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1265 return; 1266 } 1267 1268 /* 1269 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1270 * MPAMIDR_HAS_HCR_BIT == 1. 1271 */ 1272 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1273 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1274 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1275 1276 /* 1277 * The number of MPAMVPM registers is implementation defined, their 1278 * number is stored in the MPAMIDR_EL1 register. 1279 */ 1280 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1281 case 7: 1282 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1283 __fallthrough; 1284 case 6: 1285 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1286 __fallthrough; 1287 case 5: 1288 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1289 __fallthrough; 1290 case 4: 1291 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1292 __fallthrough; 1293 case 3: 1294 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1295 __fallthrough; 1296 case 2: 1297 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1298 __fallthrough; 1299 case 1: 1300 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1301 break; 1302 } 1303 } 1304 1305 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1306 { 1307 u_register_t mpam_idr = read_mpamidr_el1(); 1308 1309 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1310 1311 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1312 return; 1313 } 1314 1315 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1316 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1317 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1318 1319 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1320 case 7: 1321 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1322 __fallthrough; 1323 case 6: 1324 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1325 __fallthrough; 1326 case 5: 1327 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1328 __fallthrough; 1329 case 4: 1330 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1331 __fallthrough; 1332 case 3: 1333 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1334 __fallthrough; 1335 case 2: 1336 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1337 __fallthrough; 1338 case 1: 1339 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1340 break; 1341 } 1342 } 1343 1344 /* --------------------------------------------------------------------------- 1345 * The following registers are not added: 1346 * ICH_AP0R<n>_EL2 1347 * ICH_AP1R<n>_EL2 1348 * ICH_LR<n>_EL2 1349 * 1350 * NOTE: For a system with S-EL2 present but not enabled, accessing 1351 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1352 * SCR_EL3.NS = 1 before accessing this register. 1353 * --------------------------------------------------------------------------- 1354 */ 1355 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1356 { 1357 u_register_t scr_el3 = read_scr_el3(); 1358 1359 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1360 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1361 #else 1362 write_scr_el3(scr_el3 | SCR_NS_BIT); 1363 isb(); 1364 1365 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1366 1367 write_scr_el3(scr_el3); 1368 isb(); 1369 #endif 1370 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1371 1372 if (errata_ich_vmcr_el2_applies()) { 1373 if (security_state == SECURE) { 1374 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1375 } else { 1376 write_scr_el3(scr_el3 | SCR_NS_BIT); 1377 } 1378 isb(); 1379 } 1380 1381 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1382 1383 if (errata_ich_vmcr_el2_applies()) { 1384 write_scr_el3(scr_el3); 1385 isb(); 1386 } 1387 } 1388 1389 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1390 { 1391 u_register_t scr_el3 = read_scr_el3(); 1392 1393 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1394 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1395 #else 1396 write_scr_el3(scr_el3 | SCR_NS_BIT); 1397 isb(); 1398 1399 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1400 1401 write_scr_el3(scr_el3); 1402 isb(); 1403 #endif 1404 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1405 1406 if (errata_ich_vmcr_el2_applies()) { 1407 if (security_state == SECURE) { 1408 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1409 } else { 1410 write_scr_el3(scr_el3 | SCR_NS_BIT); 1411 } 1412 isb(); 1413 } 1414 1415 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1416 1417 if (errata_ich_vmcr_el2_applies()) { 1418 write_scr_el3(scr_el3); 1419 isb(); 1420 } 1421 } 1422 1423 /* ----------------------------------------------------- 1424 * The following registers are not added: 1425 * AMEVCNTVOFF0<n>_EL2 1426 * AMEVCNTVOFF1<n>_EL2 1427 * ----------------------------------------------------- 1428 */ 1429 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1430 { 1431 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1432 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1433 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1434 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1435 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1436 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1437 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1438 if (CTX_INCLUDE_AARCH32_REGS) { 1439 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1440 } 1441 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1442 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1443 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1444 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1445 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1446 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1447 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1448 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1449 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1450 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1451 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1452 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1453 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1454 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1455 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1456 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1457 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1458 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1459 1460 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1461 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1462 } 1463 1464 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1465 { 1466 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1467 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1468 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1469 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1470 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1471 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1472 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1473 if (CTX_INCLUDE_AARCH32_REGS) { 1474 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1475 } 1476 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1477 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1478 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1479 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1480 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1481 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1482 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1483 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1484 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1485 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1486 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1487 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1488 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1489 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1490 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1491 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1492 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1493 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1494 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1495 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1496 } 1497 1498 /******************************************************************************* 1499 * Save EL2 sysreg context 1500 ******************************************************************************/ 1501 void cm_el2_sysregs_context_save(uint32_t security_state) 1502 { 1503 cpu_context_t *ctx; 1504 el2_sysregs_t *el2_sysregs_ctx; 1505 1506 ctx = cm_get_context(security_state); 1507 assert(ctx != NULL); 1508 1509 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1510 1511 el2_sysregs_context_save_common(el2_sysregs_ctx); 1512 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1513 1514 if (is_feat_mte2_supported()) { 1515 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1516 } 1517 1518 if (is_feat_mpam_supported()) { 1519 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1520 } 1521 1522 if (is_feat_fgt_supported()) { 1523 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1524 } 1525 1526 if (is_feat_fgt2_supported()) { 1527 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1528 } 1529 1530 if (is_feat_ecv_v2_supported()) { 1531 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1532 } 1533 1534 if (is_feat_vhe_supported()) { 1535 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1536 read_contextidr_el2()); 1537 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1538 } 1539 1540 if (is_feat_ras_supported()) { 1541 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1542 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1543 } 1544 1545 if (is_feat_nv2_supported()) { 1546 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1547 } 1548 1549 if (is_feat_trf_supported()) { 1550 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1551 } 1552 1553 if (is_feat_csv2_2_supported()) { 1554 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1555 read_scxtnum_el2()); 1556 } 1557 1558 if (is_feat_hcx_supported()) { 1559 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1560 } 1561 1562 if (is_feat_tcr2_supported()) { 1563 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1564 } 1565 1566 if (is_feat_sxpie_supported()) { 1567 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1568 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1569 } 1570 1571 if (is_feat_sxpoe_supported()) { 1572 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1573 } 1574 1575 if (is_feat_brbe_supported()) { 1576 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1577 } 1578 1579 if (is_feat_s2pie_supported()) { 1580 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1581 } 1582 1583 if (is_feat_gcs_supported()) { 1584 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1585 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1586 } 1587 1588 if (is_feat_sctlr2_supported()) { 1589 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1590 } 1591 } 1592 1593 /******************************************************************************* 1594 * Restore EL2 sysreg context 1595 ******************************************************************************/ 1596 void cm_el2_sysregs_context_restore(uint32_t security_state) 1597 { 1598 cpu_context_t *ctx; 1599 el2_sysregs_t *el2_sysregs_ctx; 1600 1601 ctx = cm_get_context(security_state); 1602 assert(ctx != NULL); 1603 1604 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1605 1606 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1607 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1608 1609 if (is_feat_mte2_supported()) { 1610 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1611 } 1612 1613 if (is_feat_mpam_supported()) { 1614 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1615 } 1616 1617 if (is_feat_fgt_supported()) { 1618 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1619 } 1620 1621 if (is_feat_fgt2_supported()) { 1622 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1623 } 1624 1625 if (is_feat_ecv_v2_supported()) { 1626 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1627 } 1628 1629 if (is_feat_vhe_supported()) { 1630 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1631 contextidr_el2)); 1632 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1633 } 1634 1635 if (is_feat_ras_supported()) { 1636 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1637 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1638 } 1639 1640 if (is_feat_nv2_supported()) { 1641 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1642 } 1643 1644 if (is_feat_trf_supported()) { 1645 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1646 } 1647 1648 if (is_feat_csv2_2_supported()) { 1649 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1650 scxtnum_el2)); 1651 } 1652 1653 if (is_feat_hcx_supported()) { 1654 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1655 } 1656 1657 if (is_feat_tcr2_supported()) { 1658 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1659 } 1660 1661 if (is_feat_sxpie_supported()) { 1662 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1663 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1664 } 1665 1666 if (is_feat_sxpoe_supported()) { 1667 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1668 } 1669 1670 if (is_feat_s2pie_supported()) { 1671 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1672 } 1673 1674 if (is_feat_gcs_supported()) { 1675 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1676 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1677 } 1678 1679 if (is_feat_sctlr2_supported()) { 1680 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1681 } 1682 1683 if (is_feat_brbe_supported()) { 1684 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1685 } 1686 } 1687 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1688 1689 /******************************************************************************* 1690 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1691 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1692 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1693 * cm_prepare_el3_exit function. 1694 ******************************************************************************/ 1695 void cm_prepare_el3_exit_ns(void) 1696 { 1697 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1698 #if ENABLE_ASSERTIONS 1699 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1700 assert(ctx != NULL); 1701 1702 /* Assert that EL2 is used. */ 1703 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1704 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1705 (el_implemented(2U) != EL_IMPL_NONE)); 1706 #endif /* ENABLE_ASSERTIONS */ 1707 1708 /* Restore EL2 sysreg contexts */ 1709 cm_el2_sysregs_context_restore(NON_SECURE); 1710 cm_set_next_eret_context(NON_SECURE); 1711 #else 1712 cm_prepare_el3_exit(NON_SECURE); 1713 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1714 } 1715 1716 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1717 /******************************************************************************* 1718 * The next set of six functions are used by runtime services to save and restore 1719 * EL1 context on the 'cpu_context' structure for the specified security state. 1720 ******************************************************************************/ 1721 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1722 { 1723 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1724 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1725 1726 #if (!ERRATA_SPECULATIVE_AT) 1727 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1728 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1729 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1730 1731 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1732 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1733 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1734 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1735 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1736 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1737 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1738 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1739 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1740 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1741 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1742 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1743 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1744 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1745 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1746 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1747 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1748 1749 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1750 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1751 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1752 1753 if (CTX_INCLUDE_AARCH32_REGS) { 1754 /* Save Aarch32 registers */ 1755 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1756 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1757 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1758 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1759 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1760 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1761 } 1762 1763 if (NS_TIMER_SWITCH) { 1764 /* Save NS Timer registers */ 1765 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1766 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1767 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1768 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1769 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1770 } 1771 1772 if (is_feat_mte2_supported()) { 1773 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1774 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1775 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1776 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1777 } 1778 1779 if (is_feat_ras_supported()) { 1780 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1781 } 1782 1783 if (is_feat_s1pie_supported()) { 1784 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1785 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1786 } 1787 1788 if (is_feat_s1poe_supported()) { 1789 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1790 } 1791 1792 if (is_feat_s2poe_supported()) { 1793 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1794 } 1795 1796 if (is_feat_tcr2_supported()) { 1797 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1798 } 1799 1800 if (is_feat_trf_supported()) { 1801 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1802 } 1803 1804 if (is_feat_csv2_2_supported()) { 1805 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1806 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1807 } 1808 1809 if (is_feat_gcs_supported()) { 1810 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1811 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1812 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1813 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1814 } 1815 1816 if (is_feat_the_supported()) { 1817 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1818 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1819 } 1820 1821 if (is_feat_sctlr2_supported()) { 1822 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1823 } 1824 1825 if (is_feat_ls64_accdata_supported()) { 1826 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1827 } 1828 } 1829 1830 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1831 { 1832 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1833 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1834 1835 #if (!ERRATA_SPECULATIVE_AT) 1836 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1837 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1838 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1839 1840 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1841 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1842 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1843 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1844 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1845 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1846 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1847 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1848 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1849 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1850 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1851 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1852 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1853 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1854 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1855 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1856 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1857 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1858 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1859 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1860 1861 if (CTX_INCLUDE_AARCH32_REGS) { 1862 /* Restore Aarch32 registers */ 1863 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1864 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1865 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1866 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1867 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1868 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1869 } 1870 1871 if (NS_TIMER_SWITCH) { 1872 /* Restore NS Timer registers */ 1873 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1874 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1875 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1876 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1877 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1878 } 1879 1880 if (is_feat_mte2_supported()) { 1881 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1882 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1883 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1884 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1885 } 1886 1887 if (is_feat_ras_supported()) { 1888 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1889 } 1890 1891 if (is_feat_s1pie_supported()) { 1892 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1893 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1894 } 1895 1896 if (is_feat_s1poe_supported()) { 1897 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1898 } 1899 1900 if (is_feat_s2poe_supported()) { 1901 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1902 } 1903 1904 if (is_feat_tcr2_supported()) { 1905 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1906 } 1907 1908 if (is_feat_trf_supported()) { 1909 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1910 } 1911 1912 if (is_feat_csv2_2_supported()) { 1913 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1914 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1915 } 1916 1917 if (is_feat_gcs_supported()) { 1918 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1919 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1920 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1921 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1922 } 1923 1924 if (is_feat_the_supported()) { 1925 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1926 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1927 } 1928 1929 if (is_feat_sctlr2_supported()) { 1930 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1931 } 1932 1933 if (is_feat_ls64_accdata_supported()) { 1934 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1935 } 1936 } 1937 1938 /******************************************************************************* 1939 * The next couple of functions are used by runtime services to save and restore 1940 * EL1 context on the 'cpu_context' structure for the specified security state. 1941 ******************************************************************************/ 1942 void cm_el1_sysregs_context_save(uint32_t security_state) 1943 { 1944 cpu_context_t *ctx; 1945 1946 ctx = cm_get_context(security_state); 1947 assert(ctx != NULL); 1948 1949 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1950 1951 #if IMAGE_BL31 1952 if (security_state == SECURE) { 1953 PUBLISH_EVENT(cm_exited_secure_world); 1954 } else { 1955 PUBLISH_EVENT(cm_exited_normal_world); 1956 } 1957 #endif 1958 } 1959 1960 void cm_el1_sysregs_context_restore(uint32_t security_state) 1961 { 1962 cpu_context_t *ctx; 1963 1964 ctx = cm_get_context(security_state); 1965 assert(ctx != NULL); 1966 1967 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1968 1969 #if IMAGE_BL31 1970 if (security_state == SECURE) { 1971 PUBLISH_EVENT(cm_entering_secure_world); 1972 } else { 1973 PUBLISH_EVENT(cm_entering_normal_world); 1974 } 1975 #endif 1976 } 1977 1978 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1979 1980 /******************************************************************************* 1981 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1982 * given security state with the given entrypoint 1983 ******************************************************************************/ 1984 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1985 { 1986 cpu_context_t *ctx; 1987 el3_state_t *state; 1988 1989 ctx = cm_get_context(security_state); 1990 assert(ctx != NULL); 1991 1992 /* Populate EL3 state so that ERET jumps to the correct entry */ 1993 state = get_el3state_ctx(ctx); 1994 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1995 } 1996 1997 /******************************************************************************* 1998 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1999 * pertaining to the given security state 2000 ******************************************************************************/ 2001 void cm_set_elr_spsr_el3(uint32_t security_state, 2002 uintptr_t entrypoint, uint32_t spsr) 2003 { 2004 cpu_context_t *ctx; 2005 el3_state_t *state; 2006 2007 ctx = cm_get_context(security_state); 2008 assert(ctx != NULL); 2009 2010 /* Populate EL3 state so that ERET jumps to the correct entry */ 2011 state = get_el3state_ctx(ctx); 2012 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2013 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2014 } 2015 2016 /******************************************************************************* 2017 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2018 * pertaining to the given security state using the value and bit position 2019 * specified in the parameters. It preserves all other bits. 2020 ******************************************************************************/ 2021 void cm_write_scr_el3_bit(uint32_t security_state, 2022 uint32_t bit_pos, 2023 uint32_t value) 2024 { 2025 cpu_context_t *ctx; 2026 el3_state_t *state; 2027 u_register_t scr_el3; 2028 2029 ctx = cm_get_context(security_state); 2030 assert(ctx != NULL); 2031 2032 /* Ensure that the bit position is a valid one */ 2033 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2034 2035 /* Ensure that the 'value' is only a bit wide */ 2036 assert(value <= 1U); 2037 2038 /* 2039 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2040 * and set it to its new value. 2041 */ 2042 state = get_el3state_ctx(ctx); 2043 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2044 scr_el3 &= ~(1UL << bit_pos); 2045 scr_el3 |= (u_register_t)value << bit_pos; 2046 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2047 } 2048 2049 /******************************************************************************* 2050 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2051 * given security state. 2052 ******************************************************************************/ 2053 u_register_t cm_get_scr_el3(uint32_t security_state) 2054 { 2055 const cpu_context_t *ctx; 2056 const el3_state_t *state; 2057 2058 ctx = cm_get_context(security_state); 2059 assert(ctx != NULL); 2060 2061 /* Populate EL3 state so that ERET jumps to the correct entry */ 2062 state = get_el3state_ctx(ctx); 2063 return read_ctx_reg(state, CTX_SCR_EL3); 2064 } 2065 2066 /******************************************************************************* 2067 * This function is used to program the context that's used for exception 2068 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2069 * the required security state 2070 ******************************************************************************/ 2071 void cm_set_next_eret_context(uint32_t security_state) 2072 { 2073 cpu_context_t *ctx; 2074 2075 ctx = cm_get_context(security_state); 2076 assert(ctx != NULL); 2077 2078 cm_set_next_context(ctx); 2079 } 2080