1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/pmuv3.h> 28 #include <lib/extensions/sme.h> 29 #include <lib/extensions/spe.h> 30 #include <lib/extensions/sve.h> 31 #include <lib/extensions/sys_reg_trace.h> 32 #include <lib/extensions/trbe.h> 33 #include <lib/extensions/trf.h> 34 #include <lib/utils.h> 35 36 #if ENABLE_FEAT_TWED 37 /* Make sure delay value fits within the range(0-15) */ 38 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 39 #endif /* ENABLE_FEAT_TWED */ 40 41 static void manage_extensions_nonsecure(cpu_context_t *ctx); 42 static void manage_extensions_secure(cpu_context_t *ctx); 43 44 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 45 { 46 u_register_t sctlr_elx, actlr_elx; 47 48 /* 49 * Initialise SCTLR_EL1 to the reset value corresponding to the target 50 * execution state setting all fields rather than relying on the hw. 51 * Some fields have architecturally UNKNOWN reset values and these are 52 * set to zero. 53 * 54 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 55 * 56 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 57 * required by PSCI specification) 58 */ 59 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 60 if (GET_RW(ep->spsr) == MODE_RW_64) { 61 sctlr_elx |= SCTLR_EL1_RES1; 62 } else { 63 /* 64 * If the target execution state is AArch32 then the following 65 * fields need to be set. 66 * 67 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 68 * instructions are not trapped to EL1. 69 * 70 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 71 * instructions are not trapped to EL1. 72 * 73 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 74 * CP15DMB, CP15DSB, and CP15ISB instructions. 75 */ 76 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 77 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 78 } 79 80 #if ERRATA_A75_764081 81 /* 82 * If workaround of errata 764081 for Cortex-A75 is used then set 83 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 84 */ 85 sctlr_elx |= SCTLR_IESB_BIT; 86 #endif 87 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 88 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 89 90 /* 91 * Base the context ACTLR_EL1 on the current value, as it is 92 * implementation defined. The context restore process will write 93 * the value from the context to the actual register and can cause 94 * problems for processor cores that don't expect certain bits to 95 * be zero. 96 */ 97 actlr_elx = read_actlr_el1(); 98 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 99 } 100 101 /****************************************************************************** 102 * This function performs initializations that are specific to SECURE state 103 * and updates the cpu context specified by 'ctx'. 104 *****************************************************************************/ 105 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 106 { 107 u_register_t scr_el3; 108 el3_state_t *state; 109 110 state = get_el3state_ctx(ctx); 111 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 112 113 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 114 /* 115 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 116 * indicated by the interrupt routing model for BL31. 117 */ 118 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 119 #endif 120 121 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 122 /* Get Memory Tagging Extension support level */ 123 unsigned int mte = get_armv8_5_mte_support(); 124 #endif 125 /* 126 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 127 * is set, or when MTE is only implemented at EL0. 128 */ 129 #if CTX_INCLUDE_MTE_REGS 130 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 131 scr_el3 |= SCR_ATA_BIT; 132 #else 133 if (mte == MTE_IMPLEMENTED_EL0) { 134 scr_el3 |= SCR_ATA_BIT; 135 } 136 #endif /* CTX_INCLUDE_MTE_REGS */ 137 138 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 139 if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) { 140 if (GET_RW(ep->spsr) != MODE_RW_64) { 141 ERROR("S-EL2 can not be used in AArch32\n."); 142 panic(); 143 } 144 145 scr_el3 |= SCR_EEL2_BIT; 146 } 147 148 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 149 150 /* 151 * Initialize EL1 context registers unless SPMC is running 152 * at S-EL2. 153 */ 154 #if !SPMD_SPM_AT_SEL2 155 setup_el1_context(ctx, ep); 156 #endif 157 158 manage_extensions_secure(ctx); 159 } 160 161 #if ENABLE_RME 162 /****************************************************************************** 163 * This function performs initializations that are specific to REALM state 164 * and updates the cpu context specified by 'ctx'. 165 *****************************************************************************/ 166 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 167 { 168 u_register_t scr_el3; 169 el3_state_t *state; 170 171 state = get_el3state_ctx(ctx); 172 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 173 174 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 175 176 if (is_feat_csv2_2_supported()) { 177 /* Enable access to the SCXTNUM_ELx registers. */ 178 scr_el3 |= SCR_EnSCXT_BIT; 179 } 180 181 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 182 } 183 #endif /* ENABLE_RME */ 184 185 /****************************************************************************** 186 * This function performs initializations that are specific to NON-SECURE state 187 * and updates the cpu context specified by 'ctx'. 188 *****************************************************************************/ 189 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 190 { 191 u_register_t scr_el3; 192 el3_state_t *state; 193 194 state = get_el3state_ctx(ctx); 195 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 196 197 /* SCR_NS: Set the NS bit */ 198 scr_el3 |= SCR_NS_BIT; 199 200 #if !CTX_INCLUDE_PAUTH_REGS 201 /* 202 * If the pointer authentication registers aren't saved during world 203 * switches the value of the registers can be leaked from the Secure to 204 * the Non-secure world. To prevent this, rather than enabling pointer 205 * authentication everywhere, we only enable it in the Non-secure world. 206 * 207 * If the Secure world wants to use pointer authentication, 208 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 209 */ 210 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 211 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 212 213 /* Allow access to Allocation Tags when MTE is implemented. */ 214 scr_el3 |= SCR_ATA_BIT; 215 216 #if HANDLE_EA_EL3_FIRST_NS 217 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 218 scr_el3 |= SCR_EA_BIT; 219 #endif 220 221 #if RAS_TRAP_NS_ERR_REC_ACCESS 222 /* 223 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 224 * and RAS ERX registers from EL1 and EL2(from any security state) 225 * are trapped to EL3. 226 * Set here to trap only for NS EL1/EL2 227 * 228 */ 229 scr_el3 |= SCR_TERR_BIT; 230 #endif 231 232 if (is_feat_csv2_2_supported()) { 233 /* Enable access to the SCXTNUM_ELx registers. */ 234 scr_el3 |= SCR_EnSCXT_BIT; 235 } 236 237 #ifdef IMAGE_BL31 238 /* 239 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 240 * indicated by the interrupt routing model for BL31. 241 */ 242 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 243 #endif 244 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 245 246 /* Initialize EL1 context registers */ 247 setup_el1_context(ctx, ep); 248 249 /* Initialize EL2 context registers */ 250 #if CTX_INCLUDE_EL2_REGS 251 252 /* 253 * Initialize SCTLR_EL2 context register using Endianness value 254 * taken from the entrypoint attribute. 255 */ 256 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 257 sctlr_el2 |= SCTLR_EL2_RES1; 258 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 259 sctlr_el2); 260 261 /* 262 * Program the ICC_SRE_EL2 to make sure the correct bits are set 263 * when restoring NS context. 264 */ 265 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 266 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 267 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 268 icc_sre_el2); 269 270 if (is_feat_hcx_supported()) { 271 /* 272 * Initialize register HCRX_EL2 with its init value. 273 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 274 * chance that this can lead to unexpected behavior in lower 275 * ELs that have not been updated since the introduction of 276 * this feature if not properly initialized, especially when 277 * it comes to those bits that enable/disable traps. 278 */ 279 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, 280 HCRX_EL2_INIT_VAL); 281 } 282 #endif /* CTX_INCLUDE_EL2_REGS */ 283 284 manage_extensions_nonsecure(ctx); 285 } 286 287 /******************************************************************************* 288 * The following function performs initialization of the cpu_context 'ctx' 289 * for first use that is common to all security states, and sets the 290 * initial entrypoint state as specified by the entry_point_info structure. 291 * 292 * The EE and ST attributes are used to configure the endianness and secure 293 * timer availability for the new execution context. 294 ******************************************************************************/ 295 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 296 { 297 u_register_t scr_el3; 298 el3_state_t *state; 299 gp_regs_t *gp_regs; 300 301 /* Clear any residual register values from the context */ 302 zeromem(ctx, sizeof(*ctx)); 303 304 /* 305 * SCR_EL3 was initialised during reset sequence in macro 306 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 307 * affect the next EL. 308 * 309 * The following fields are initially set to zero and then updated to 310 * the required value depending on the state of the SPSR_EL3 and the 311 * Security state and entrypoint attributes of the next EL. 312 */ 313 scr_el3 = read_scr(); 314 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 315 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 316 317 /* 318 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 319 * Exception level as specified by SPSR. 320 */ 321 if (GET_RW(ep->spsr) == MODE_RW_64) { 322 scr_el3 |= SCR_RW_BIT; 323 } 324 325 /* 326 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 327 * Secure timer registers to EL3, from AArch64 state only, if specified 328 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 329 * bit always behaves as 1 (i.e. secure physical timer register access 330 * is not trapped) 331 */ 332 if (EP_GET_ST(ep->h.attr) != 0U) { 333 scr_el3 |= SCR_ST_BIT; 334 } 335 336 /* 337 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 338 * SCR_EL3.HXEn. 339 */ 340 if (is_feat_hcx_supported()) { 341 scr_el3 |= SCR_HXEn_BIT; 342 } 343 344 /* 345 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 346 * registers are trapped to EL3. 347 */ 348 #if ENABLE_FEAT_RNG_TRAP 349 scr_el3 |= SCR_TRNDR_BIT; 350 #endif 351 352 #if FAULT_INJECTION_SUPPORT 353 /* Enable fault injection from lower ELs */ 354 scr_el3 |= SCR_FIEN_BIT; 355 #endif 356 357 /* 358 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 359 */ 360 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 361 scr_el3 |= SCR_TCR2EN_BIT; 362 } 363 364 /* 365 * SCR_EL3.PIEN: Enable permission indirection and overlay 366 * registers for AArch64 if present. 367 */ 368 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 369 scr_el3 |= SCR_PIEN_BIT; 370 } 371 372 /* 373 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 374 */ 375 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 376 scr_el3 |= SCR_GCSEn_BIT; 377 } 378 379 /* 380 * CPTR_EL3 was initialized out of reset, copy that value to the 381 * context register. 382 */ 383 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 384 385 /* 386 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 387 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 388 * next mode is Hyp. 389 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 390 * same conditions as HVC instructions and when the processor supports 391 * ARMv8.6-FGT. 392 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 393 * CNTPOFF_EL2 register under the same conditions as HVC instructions 394 * and when the processor supports ECV. 395 */ 396 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 397 || ((GET_RW(ep->spsr) != MODE_RW_64) 398 && (GET_M32(ep->spsr) == MODE32_hyp))) { 399 scr_el3 |= SCR_HCE_BIT; 400 401 if (is_feat_fgt_supported()) { 402 scr_el3 |= SCR_FGTEN_BIT; 403 } 404 405 if (is_feat_ecv_supported()) { 406 scr_el3 |= SCR_ECVEN_BIT; 407 } 408 } 409 410 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 411 if (is_feat_twed_supported()) { 412 /* Set delay in SCR_EL3 */ 413 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 414 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 415 << SCR_TWEDEL_SHIFT); 416 417 /* Enable WFE delay */ 418 scr_el3 |= SCR_TWEDEn_BIT; 419 } 420 421 /* 422 * Populate EL3 state so that we've the right context 423 * before doing ERET 424 */ 425 state = get_el3state_ctx(ctx); 426 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 427 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 428 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 429 430 /* 431 * Store the X0-X7 value from the entrypoint into the context 432 * Use memcpy as we are in control of the layout of the structures 433 */ 434 gp_regs = get_gpregs_ctx(ctx); 435 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 436 } 437 438 /******************************************************************************* 439 * Context management library initialization routine. This library is used by 440 * runtime services to share pointers to 'cpu_context' structures for secure 441 * non-secure and realm states. Management of the structures and their associated 442 * memory is not done by the context management library e.g. the PSCI service 443 * manages the cpu context used for entry from and exit to the non-secure state. 444 * The Secure payload dispatcher service manages the context(s) corresponding to 445 * the secure state. It also uses this library to get access to the non-secure 446 * state cpu context pointers. 447 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 448 * which will be used for programming an entry into a lower EL. The same context 449 * will be used to save state upon exception entry from that EL. 450 ******************************************************************************/ 451 void __init cm_init(void) 452 { 453 /* 454 * The context management library has only global data to initialize, but 455 * that will be done when the BSS is zeroed out. 456 */ 457 } 458 459 /******************************************************************************* 460 * This is the high-level function used to initialize the cpu_context 'ctx' for 461 * first use. It performs initializations that are common to all security states 462 * and initializations specific to the security state specified in 'ep' 463 ******************************************************************************/ 464 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 465 { 466 unsigned int security_state; 467 468 assert(ctx != NULL); 469 470 /* 471 * Perform initializations that are common 472 * to all security states 473 */ 474 setup_context_common(ctx, ep); 475 476 security_state = GET_SECURITY_STATE(ep->h.attr); 477 478 /* Perform security state specific initializations */ 479 switch (security_state) { 480 case SECURE: 481 setup_secure_context(ctx, ep); 482 break; 483 #if ENABLE_RME 484 case REALM: 485 setup_realm_context(ctx, ep); 486 break; 487 #endif 488 case NON_SECURE: 489 setup_ns_context(ctx, ep); 490 break; 491 default: 492 ERROR("Invalid security state\n"); 493 panic(); 494 break; 495 } 496 } 497 498 /******************************************************************************* 499 * Enable architecture extensions for EL3 execution. This function only updates 500 * registers in-place which are expected to either never change or be 501 * overwritten by el3_exit. 502 ******************************************************************************/ 503 #if IMAGE_BL31 504 void cm_manage_extensions_el3(void) 505 { 506 if (is_feat_spe_supported()) { 507 spe_init_el3(); 508 } 509 510 if (is_feat_amu_supported()) { 511 amu_init_el3(); 512 } 513 514 if (is_feat_sme_supported()) { 515 sme_init_el3(); 516 } 517 518 if (is_feat_mpam_supported()) { 519 mpam_init_el3(); 520 } 521 522 if (is_feat_trbe_supported()) { 523 trbe_init_el3(); 524 } 525 526 if (is_feat_brbe_supported()) { 527 brbe_init_el3(); 528 } 529 530 if (is_feat_trf_supported()) { 531 trf_init_el3(); 532 } 533 534 pmuv3_init_el3(); 535 } 536 #endif /* IMAGE_BL31 */ 537 538 /******************************************************************************* 539 * Enable architecture extensions on first entry to Non-secure world. 540 ******************************************************************************/ 541 static void manage_extensions_nonsecure(cpu_context_t *ctx) 542 { 543 #if IMAGE_BL31 544 if (is_feat_amu_supported()) { 545 amu_enable(ctx); 546 } 547 548 /* Enable SVE and FPU/SIMD */ 549 if (is_feat_sve_supported()) { 550 sve_enable(ctx); 551 } 552 553 if (is_feat_sme_supported()) { 554 sme_enable(ctx); 555 } 556 557 if (is_feat_sys_reg_trace_supported()) { 558 sys_reg_trace_enable(ctx); 559 } 560 561 pmuv3_enable(ctx); 562 #endif /* IMAGE_BL31 */ 563 } 564 565 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 566 static __unused void enable_pauth_el2(void) 567 { 568 u_register_t hcr_el2 = read_hcr_el2(); 569 /* 570 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 571 * accessing key registers or using pointer authentication instructions 572 * from lower ELs. 573 */ 574 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 575 576 write_hcr_el2(hcr_el2); 577 } 578 579 /******************************************************************************* 580 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 581 * world when EL2 is empty and unused. 582 ******************************************************************************/ 583 static void manage_extensions_nonsecure_el2_unused(void) 584 { 585 #if IMAGE_BL31 586 if (is_feat_spe_supported()) { 587 spe_init_el2_unused(); 588 } 589 590 if (is_feat_amu_supported()) { 591 amu_init_el2_unused(); 592 } 593 594 if (is_feat_mpam_supported()) { 595 mpam_init_el2_unused(); 596 } 597 598 if (is_feat_trbe_supported()) { 599 trbe_init_el2_unused(); 600 } 601 602 if (is_feat_sys_reg_trace_supported()) { 603 sys_reg_trace_init_el2_unused(); 604 } 605 606 if (is_feat_trf_supported()) { 607 trf_init_el2_unused(); 608 } 609 610 pmuv3_init_el2_unused(); 611 612 if (is_feat_sve_supported()) { 613 sve_init_el2_unused(); 614 } 615 616 if (is_feat_sme_supported()) { 617 sme_init_el2_unused(); 618 } 619 620 #if ENABLE_PAUTH 621 enable_pauth_el2(); 622 #endif /* ENABLE_PAUTH */ 623 #endif /* IMAGE_BL31 */ 624 } 625 626 /******************************************************************************* 627 * Enable architecture extensions on first entry to Secure world. 628 ******************************************************************************/ 629 static void manage_extensions_secure(cpu_context_t *ctx) 630 { 631 #if IMAGE_BL31 632 if (is_feat_sve_supported()) { 633 if (ENABLE_SVE_FOR_SWD) { 634 /* 635 * Enable SVE and FPU in secure context, secure manager must 636 * ensure that the SVE and FPU register contexts are properly 637 * managed. 638 */ 639 sve_enable(ctx); 640 } else { 641 /* 642 * Disable SVE and FPU in secure context so non-secure world 643 * can safely use them. 644 */ 645 sve_disable(ctx); 646 } 647 } 648 649 if (is_feat_sme_supported()) { 650 if (ENABLE_SME_FOR_SWD) { 651 /* 652 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 653 * must ensure SME, SVE, and FPU/SIMD context properly managed. 654 */ 655 sme_init_el3(); 656 sme_enable(ctx); 657 } else { 658 /* 659 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 660 * world can safely use the associated registers. 661 */ 662 sme_disable(ctx); 663 } 664 } 665 #endif /* IMAGE_BL31 */ 666 } 667 668 /******************************************************************************* 669 * The following function initializes the cpu_context for a CPU specified by 670 * its `cpu_idx` for first use, and sets the initial entrypoint state as 671 * specified by the entry_point_info structure. 672 ******************************************************************************/ 673 void cm_init_context_by_index(unsigned int cpu_idx, 674 const entry_point_info_t *ep) 675 { 676 cpu_context_t *ctx; 677 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 678 cm_setup_context(ctx, ep); 679 } 680 681 /******************************************************************************* 682 * The following function initializes the cpu_context for the current CPU 683 * for first use, and sets the initial entrypoint state as specified by the 684 * entry_point_info structure. 685 ******************************************************************************/ 686 void cm_init_my_context(const entry_point_info_t *ep) 687 { 688 cpu_context_t *ctx; 689 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 690 cm_setup_context(ctx, ep); 691 } 692 693 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 694 static __unused void init_nonsecure_el2_unused(cpu_context_t *ctx) 695 { 696 u_register_t hcr_el2 = HCR_RESET_VAL; 697 u_register_t mdcr_el2; 698 u_register_t scr_el3; 699 700 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 701 702 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 703 if ((scr_el3 & SCR_RW_BIT) != 0U) { 704 hcr_el2 |= HCR_RW_BIT; 705 } 706 707 write_hcr_el2(hcr_el2); 708 709 /* 710 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 711 * All fields have architecturally UNKNOWN reset values. 712 */ 713 write_cptr_el2(CPTR_EL2_RESET_VAL); 714 715 /* 716 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 717 * reset and are set to zero except for field(s) listed below. 718 * 719 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 720 * Non-secure EL0 and EL1 accesses to the physical timer registers. 721 * 722 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 723 * Non-secure EL0 and EL1 accesses to the physical counter registers. 724 */ 725 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 726 727 /* 728 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 729 * UNKNOWN value. 730 */ 731 write_cntvoff_el2(0); 732 733 /* 734 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 735 * respectively. 736 */ 737 write_vpidr_el2(read_midr_el1()); 738 write_vmpidr_el2(read_mpidr_el1()); 739 740 /* 741 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 742 * 743 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 744 * translation is disabled, cache maintenance operations depend on the 745 * VMID. 746 * 747 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 748 * disabled. 749 */ 750 write_vttbr_el2(VTTBR_RESET_VAL & 751 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 752 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 753 754 /* 755 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 756 * Some fields are architecturally UNKNOWN on reset. 757 * 758 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 759 * register accesses to the Debug ROM registers are not trapped to EL2. 760 * 761 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 762 * accesses to the powerdown debug registers are not trapped to EL2. 763 * 764 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 765 * debug registers do not trap to EL2. 766 * 767 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 768 * EL2. 769 */ 770 mdcr_el2 = MDCR_EL2_RESET_VAL & 771 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 772 MDCR_EL2_TDE_BIT); 773 774 write_mdcr_el2(mdcr_el2); 775 776 /* 777 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 778 * 779 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 780 * EL1 accesses to System registers do not trap to EL2. 781 */ 782 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 783 784 /* 785 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 786 * reset. 787 * 788 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 789 * and prevent timer interrupts. 790 */ 791 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 792 793 manage_extensions_nonsecure_el2_unused(); 794 } 795 796 /******************************************************************************* 797 * Prepare the CPU system registers for first entry into realm, secure, or 798 * normal world. 799 * 800 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 801 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 802 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 803 * For all entries, the EL1 registers are initialized from the cpu_context 804 ******************************************************************************/ 805 void cm_prepare_el3_exit(uint32_t security_state) 806 { 807 u_register_t sctlr_elx, scr_el3; 808 cpu_context_t *ctx = cm_get_context(security_state); 809 810 assert(ctx != NULL); 811 812 if (security_state == NON_SECURE) { 813 uint64_t el2_implemented = el_implemented(2); 814 815 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 816 CTX_SCR_EL3); 817 818 if (((scr_el3 & SCR_HCE_BIT) != 0U) 819 || (el2_implemented != EL_IMPL_NONE)) { 820 /* 821 * If context is not being used for EL2, initialize 822 * HCRX_EL2 with its init value here. 823 */ 824 if (is_feat_hcx_supported()) { 825 write_hcrx_el2(HCRX_EL2_INIT_VAL); 826 } 827 } 828 829 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 830 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 831 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 832 CTX_SCTLR_EL1); 833 sctlr_elx &= SCTLR_EE_BIT; 834 sctlr_elx |= SCTLR_EL2_RES1; 835 #if ERRATA_A75_764081 836 /* 837 * If workaround of errata 764081 for Cortex-A75 is used 838 * then set SCTLR_EL2.IESB to enable Implicit Error 839 * Synchronization Barrier. 840 */ 841 sctlr_elx |= SCTLR_IESB_BIT; 842 #endif 843 write_sctlr_el2(sctlr_elx); 844 } else if (el2_implemented != EL_IMPL_NONE) { 845 init_nonsecure_el2_unused(ctx); 846 } 847 } 848 849 cm_el1_sysregs_context_restore(security_state); 850 cm_set_next_eret_context(security_state); 851 } 852 853 #if CTX_INCLUDE_EL2_REGS 854 855 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 856 { 857 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 858 if (is_feat_amu_supported()) { 859 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 860 } 861 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 862 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 863 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 864 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 865 } 866 867 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 868 { 869 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 870 if (is_feat_amu_supported()) { 871 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 872 } 873 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 874 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 875 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 876 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 877 } 878 879 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 880 { 881 u_register_t mpam_idr = read_mpamidr_el1(); 882 883 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 884 885 /* 886 * The context registers that we intend to save would be part of the 887 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 888 */ 889 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 890 return; 891 } 892 893 /* 894 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 895 * MPAMIDR_HAS_HCR_BIT == 1. 896 */ 897 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 898 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 899 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 900 901 /* 902 * The number of MPAMVPM registers is implementation defined, their 903 * number is stored in the MPAMIDR_EL1 register. 904 */ 905 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 906 case 7: 907 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 908 __fallthrough; 909 case 6: 910 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 911 __fallthrough; 912 case 5: 913 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 914 __fallthrough; 915 case 4: 916 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 917 __fallthrough; 918 case 3: 919 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 920 __fallthrough; 921 case 2: 922 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 923 __fallthrough; 924 case 1: 925 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 926 break; 927 } 928 } 929 930 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 931 { 932 u_register_t mpam_idr = read_mpamidr_el1(); 933 934 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 935 936 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 937 return; 938 } 939 940 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 941 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 942 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 943 944 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 945 case 7: 946 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 947 __fallthrough; 948 case 6: 949 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 950 __fallthrough; 951 case 5: 952 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 953 __fallthrough; 954 case 4: 955 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 956 __fallthrough; 957 case 3: 958 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 959 __fallthrough; 960 case 2: 961 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 962 __fallthrough; 963 case 1: 964 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 965 break; 966 } 967 } 968 969 /******************************************************************************* 970 * Save EL2 sysreg context 971 ******************************************************************************/ 972 void cm_el2_sysregs_context_save(uint32_t security_state) 973 { 974 u_register_t scr_el3 = read_scr(); 975 976 /* 977 * Always save the non-secure and realm EL2 context, only save the 978 * S-EL2 context if S-EL2 is enabled. 979 */ 980 if ((security_state != SECURE) || 981 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 982 cpu_context_t *ctx; 983 el2_sysregs_t *el2_sysregs_ctx; 984 985 ctx = cm_get_context(security_state); 986 assert(ctx != NULL); 987 988 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 989 990 el2_sysregs_context_save_common(el2_sysregs_ctx); 991 #if CTX_INCLUDE_MTE_REGS 992 el2_sysregs_context_save_mte(el2_sysregs_ctx); 993 #endif 994 if (is_feat_mpam_supported()) { 995 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 996 } 997 998 if (is_feat_fgt_supported()) { 999 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1000 } 1001 1002 if (is_feat_ecv_v2_supported()) { 1003 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, 1004 read_cntpoff_el2()); 1005 } 1006 1007 if (is_feat_vhe_supported()) { 1008 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, 1009 read_contextidr_el2()); 1010 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, 1011 read_ttbr1_el2()); 1012 } 1013 1014 if (is_feat_ras_supported()) { 1015 write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, 1016 read_vdisr_el2()); 1017 write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, 1018 read_vsesr_el2()); 1019 } 1020 1021 if (is_feat_nv2_supported()) { 1022 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, 1023 read_vncr_el2()); 1024 } 1025 1026 if (is_feat_trf_supported()) { 1027 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 1028 } 1029 1030 if (is_feat_csv2_2_supported()) { 1031 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, 1032 read_scxtnum_el2()); 1033 } 1034 1035 if (is_feat_hcx_supported()) { 1036 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1037 } 1038 if (is_feat_tcr2_supported()) { 1039 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1040 } 1041 if (is_feat_sxpie_supported()) { 1042 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); 1043 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); 1044 } 1045 if (is_feat_s2pie_supported()) { 1046 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); 1047 } 1048 if (is_feat_sxpoe_supported()) { 1049 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); 1050 } 1051 if (is_feat_gcs_supported()) { 1052 write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); 1053 write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); 1054 } 1055 } 1056 } 1057 1058 /******************************************************************************* 1059 * Restore EL2 sysreg context 1060 ******************************************************************************/ 1061 void cm_el2_sysregs_context_restore(uint32_t security_state) 1062 { 1063 u_register_t scr_el3 = read_scr(); 1064 1065 /* 1066 * Always restore the non-secure and realm EL2 context, only restore the 1067 * S-EL2 context if S-EL2 is enabled. 1068 */ 1069 if ((security_state != SECURE) || 1070 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 1071 cpu_context_t *ctx; 1072 el2_sysregs_t *el2_sysregs_ctx; 1073 1074 ctx = cm_get_context(security_state); 1075 assert(ctx != NULL); 1076 1077 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1078 1079 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1080 #if CTX_INCLUDE_MTE_REGS 1081 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 1082 #endif 1083 if (is_feat_mpam_supported()) { 1084 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1085 } 1086 1087 if (is_feat_fgt_supported()) { 1088 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1089 } 1090 1091 if (is_feat_ecv_v2_supported()) { 1092 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, 1093 CTX_CNTPOFF_EL2)); 1094 } 1095 1096 if (is_feat_vhe_supported()) { 1097 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1098 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1099 } 1100 1101 if (is_feat_ras_supported()) { 1102 write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); 1103 write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); 1104 } 1105 1106 if (is_feat_nv2_supported()) { 1107 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1108 } 1109 if (is_feat_trf_supported()) { 1110 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1111 } 1112 1113 if (is_feat_csv2_2_supported()) { 1114 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, 1115 CTX_SCXTNUM_EL2)); 1116 } 1117 1118 if (is_feat_hcx_supported()) { 1119 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1120 } 1121 if (is_feat_tcr2_supported()) { 1122 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1123 } 1124 if (is_feat_sxpie_supported()) { 1125 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); 1126 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); 1127 } 1128 if (is_feat_s2pie_supported()) { 1129 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); 1130 } 1131 if (is_feat_sxpoe_supported()) { 1132 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); 1133 } 1134 if (is_feat_gcs_supported()) { 1135 write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); 1136 write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); 1137 } 1138 } 1139 } 1140 #endif /* CTX_INCLUDE_EL2_REGS */ 1141 1142 /******************************************************************************* 1143 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1144 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1145 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1146 * cm_prepare_el3_exit function. 1147 ******************************************************************************/ 1148 void cm_prepare_el3_exit_ns(void) 1149 { 1150 #if CTX_INCLUDE_EL2_REGS 1151 #if ENABLE_ASSERTIONS 1152 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1153 assert(ctx != NULL); 1154 1155 /* Assert that EL2 is used. */ 1156 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1157 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1158 (el_implemented(2U) != EL_IMPL_NONE)); 1159 #endif /* ENABLE_ASSERTIONS */ 1160 1161 /* 1162 * Set the NS bit to be able to access the ICC_SRE_EL2 1163 * register when restoring context. 1164 */ 1165 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 1166 1167 /* 1168 * Ensure the NS bit change is committed before the EL2/EL1 1169 * state restoration. 1170 */ 1171 isb(); 1172 1173 /* Restore EL2 and EL1 sysreg contexts */ 1174 cm_el2_sysregs_context_restore(NON_SECURE); 1175 cm_el1_sysregs_context_restore(NON_SECURE); 1176 cm_set_next_eret_context(NON_SECURE); 1177 #else 1178 cm_prepare_el3_exit(NON_SECURE); 1179 #endif /* CTX_INCLUDE_EL2_REGS */ 1180 } 1181 1182 /******************************************************************************* 1183 * The next four functions are used by runtime services to save and restore 1184 * EL1 context on the 'cpu_context' structure for the specified security 1185 * state. 1186 ******************************************************************************/ 1187 void cm_el1_sysregs_context_save(uint32_t security_state) 1188 { 1189 cpu_context_t *ctx; 1190 1191 ctx = cm_get_context(security_state); 1192 assert(ctx != NULL); 1193 1194 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1195 1196 #if IMAGE_BL31 1197 if (security_state == SECURE) 1198 PUBLISH_EVENT(cm_exited_secure_world); 1199 else 1200 PUBLISH_EVENT(cm_exited_normal_world); 1201 #endif 1202 } 1203 1204 void cm_el1_sysregs_context_restore(uint32_t security_state) 1205 { 1206 cpu_context_t *ctx; 1207 1208 ctx = cm_get_context(security_state); 1209 assert(ctx != NULL); 1210 1211 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1212 1213 #if IMAGE_BL31 1214 if (security_state == SECURE) 1215 PUBLISH_EVENT(cm_entering_secure_world); 1216 else 1217 PUBLISH_EVENT(cm_entering_normal_world); 1218 #endif 1219 } 1220 1221 /******************************************************************************* 1222 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1223 * given security state with the given entrypoint 1224 ******************************************************************************/ 1225 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1226 { 1227 cpu_context_t *ctx; 1228 el3_state_t *state; 1229 1230 ctx = cm_get_context(security_state); 1231 assert(ctx != NULL); 1232 1233 /* Populate EL3 state so that ERET jumps to the correct entry */ 1234 state = get_el3state_ctx(ctx); 1235 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1236 } 1237 1238 /******************************************************************************* 1239 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1240 * pertaining to the given security state 1241 ******************************************************************************/ 1242 void cm_set_elr_spsr_el3(uint32_t security_state, 1243 uintptr_t entrypoint, uint32_t spsr) 1244 { 1245 cpu_context_t *ctx; 1246 el3_state_t *state; 1247 1248 ctx = cm_get_context(security_state); 1249 assert(ctx != NULL); 1250 1251 /* Populate EL3 state so that ERET jumps to the correct entry */ 1252 state = get_el3state_ctx(ctx); 1253 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1254 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1255 } 1256 1257 /******************************************************************************* 1258 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1259 * pertaining to the given security state using the value and bit position 1260 * specified in the parameters. It preserves all other bits. 1261 ******************************************************************************/ 1262 void cm_write_scr_el3_bit(uint32_t security_state, 1263 uint32_t bit_pos, 1264 uint32_t value) 1265 { 1266 cpu_context_t *ctx; 1267 el3_state_t *state; 1268 u_register_t scr_el3; 1269 1270 ctx = cm_get_context(security_state); 1271 assert(ctx != NULL); 1272 1273 /* Ensure that the bit position is a valid one */ 1274 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1275 1276 /* Ensure that the 'value' is only a bit wide */ 1277 assert(value <= 1U); 1278 1279 /* 1280 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1281 * and set it to its new value. 1282 */ 1283 state = get_el3state_ctx(ctx); 1284 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1285 scr_el3 &= ~(1UL << bit_pos); 1286 scr_el3 |= (u_register_t)value << bit_pos; 1287 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1288 } 1289 1290 /******************************************************************************* 1291 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1292 * given security state. 1293 ******************************************************************************/ 1294 u_register_t cm_get_scr_el3(uint32_t security_state) 1295 { 1296 cpu_context_t *ctx; 1297 el3_state_t *state; 1298 1299 ctx = cm_get_context(security_state); 1300 assert(ctx != NULL); 1301 1302 /* Populate EL3 state so that ERET jumps to the correct entry */ 1303 state = get_el3state_ctx(ctx); 1304 return read_ctx_reg(state, CTX_SCR_EL3); 1305 } 1306 1307 /******************************************************************************* 1308 * This function is used to program the context that's used for exception 1309 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1310 * the required security state 1311 ******************************************************************************/ 1312 void cm_set_next_eret_context(uint32_t security_state) 1313 { 1314 cpu_context_t *ctx; 1315 1316 ctx = cm_get_context(security_state); 1317 assert(ctx != NULL); 1318 1319 cm_set_next_context(ctx); 1320 } 1321