1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/cpu_data.h> 24 #include <lib/el3_runtime/pubsub_events.h> 25 #include <lib/extensions/amu.h> 26 #include <lib/extensions/brbe.h> 27 #include <lib/extensions/mpam.h> 28 #include <lib/extensions/pmuv3.h> 29 #include <lib/extensions/sme.h> 30 #include <lib/extensions/spe.h> 31 #include <lib/extensions/sve.h> 32 #include <lib/extensions/sys_reg_trace.h> 33 #include <lib/extensions/trbe.h> 34 #include <lib/extensions/trf.h> 35 #include <lib/utils.h> 36 37 #if ENABLE_FEAT_TWED 38 /* Make sure delay value fits within the range(0-15) */ 39 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 40 #endif /* ENABLE_FEAT_TWED */ 41 42 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 43 static bool has_secure_perworld_init; 44 45 static void manage_extensions_nonsecure(cpu_context_t *ctx); 46 static void manage_extensions_secure(cpu_context_t *ctx); 47 static void manage_extensions_secure_per_world(void); 48 49 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 50 { 51 u_register_t sctlr_elx, actlr_elx; 52 53 /* 54 * Initialise SCTLR_EL1 to the reset value corresponding to the target 55 * execution state setting all fields rather than relying on the hw. 56 * Some fields have architecturally UNKNOWN reset values and these are 57 * set to zero. 58 * 59 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 60 * 61 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 62 * required by PSCI specification) 63 */ 64 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 65 if (GET_RW(ep->spsr) == MODE_RW_64) { 66 sctlr_elx |= SCTLR_EL1_RES1; 67 } else { 68 /* 69 * If the target execution state is AArch32 then the following 70 * fields need to be set. 71 * 72 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 73 * instructions are not trapped to EL1. 74 * 75 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 76 * instructions are not trapped to EL1. 77 * 78 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 79 * CP15DMB, CP15DSB, and CP15ISB instructions. 80 */ 81 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 82 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 83 } 84 85 #if ERRATA_A75_764081 86 /* 87 * If workaround of errata 764081 for Cortex-A75 is used then set 88 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 89 */ 90 sctlr_elx |= SCTLR_IESB_BIT; 91 #endif 92 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 93 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 94 95 /* 96 * Base the context ACTLR_EL1 on the current value, as it is 97 * implementation defined. The context restore process will write 98 * the value from the context to the actual register and can cause 99 * problems for processor cores that don't expect certain bits to 100 * be zero. 101 */ 102 actlr_elx = read_actlr_el1(); 103 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 104 } 105 106 /****************************************************************************** 107 * This function performs initializations that are specific to SECURE state 108 * and updates the cpu context specified by 'ctx'. 109 *****************************************************************************/ 110 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 111 { 112 u_register_t scr_el3; 113 el3_state_t *state; 114 115 state = get_el3state_ctx(ctx); 116 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 117 118 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 119 /* 120 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 121 * indicated by the interrupt routing model for BL31. 122 */ 123 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 124 #endif 125 126 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 127 /* Get Memory Tagging Extension support level */ 128 unsigned int mte = get_armv8_5_mte_support(); 129 #endif 130 /* 131 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 132 * is set, or when MTE is only implemented at EL0. 133 */ 134 #if CTX_INCLUDE_MTE_REGS 135 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 136 scr_el3 |= SCR_ATA_BIT; 137 #else 138 if (mte == MTE_IMPLEMENTED_EL0) { 139 scr_el3 |= SCR_ATA_BIT; 140 } 141 #endif /* CTX_INCLUDE_MTE_REGS */ 142 143 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 144 145 /* 146 * Initialize EL1 context registers unless SPMC is running 147 * at S-EL2. 148 */ 149 #if !SPMD_SPM_AT_SEL2 150 setup_el1_context(ctx, ep); 151 #endif 152 153 manage_extensions_secure(ctx); 154 155 /** 156 * manage_extensions_secure_per_world api has to be executed once, 157 * as the registers getting initialised, maintain constant value across 158 * all the cpus for the secure world. 159 * Henceforth, this check ensures that the registers are initialised once 160 * and avoids re-initialization from multiple cores. 161 */ 162 if (!has_secure_perworld_init) { 163 manage_extensions_secure_per_world(); 164 } 165 166 } 167 168 #if ENABLE_RME 169 /****************************************************************************** 170 * This function performs initializations that are specific to REALM state 171 * and updates the cpu context specified by 'ctx'. 172 *****************************************************************************/ 173 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 174 { 175 u_register_t scr_el3; 176 el3_state_t *state; 177 178 state = get_el3state_ctx(ctx); 179 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 180 181 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 182 183 if (is_feat_csv2_2_supported()) { 184 /* Enable access to the SCXTNUM_ELx registers. */ 185 scr_el3 |= SCR_EnSCXT_BIT; 186 } 187 188 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 189 } 190 #endif /* ENABLE_RME */ 191 192 /****************************************************************************** 193 * This function performs initializations that are specific to NON-SECURE state 194 * and updates the cpu context specified by 'ctx'. 195 *****************************************************************************/ 196 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 197 { 198 u_register_t scr_el3; 199 el3_state_t *state; 200 201 state = get_el3state_ctx(ctx); 202 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 203 204 /* SCR_NS: Set the NS bit */ 205 scr_el3 |= SCR_NS_BIT; 206 207 /* Allow access to Allocation Tags when MTE is implemented. */ 208 scr_el3 |= SCR_ATA_BIT; 209 210 #if !CTX_INCLUDE_PAUTH_REGS 211 /* 212 * Pointer Authentication feature, if present, is always enabled by default 213 * for Non secure lower exception levels. We do not have an explicit 214 * flag to set it. 215 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 216 * exception levels of secure and realm worlds. 217 * 218 * To prevent the leakage between the worlds during world switch, 219 * we enable it only for the non-secure world. 220 * 221 * If the Secure/realm world wants to use pointer authentication, 222 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 223 * it will be enabled globally for all the contexts. 224 * 225 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 226 * other than EL3 227 * 228 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 229 * than EL3 230 */ 231 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 232 233 #endif /* CTX_INCLUDE_PAUTH_REGS */ 234 235 #if HANDLE_EA_EL3_FIRST_NS 236 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 237 scr_el3 |= SCR_EA_BIT; 238 #endif 239 240 #if RAS_TRAP_NS_ERR_REC_ACCESS 241 /* 242 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 243 * and RAS ERX registers from EL1 and EL2(from any security state) 244 * are trapped to EL3. 245 * Set here to trap only for NS EL1/EL2 246 * 247 */ 248 scr_el3 |= SCR_TERR_BIT; 249 #endif 250 251 if (is_feat_csv2_2_supported()) { 252 /* Enable access to the SCXTNUM_ELx registers. */ 253 scr_el3 |= SCR_EnSCXT_BIT; 254 } 255 256 #ifdef IMAGE_BL31 257 /* 258 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 259 * indicated by the interrupt routing model for BL31. 260 */ 261 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 262 #endif 263 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 264 265 /* Initialize EL1 context registers */ 266 setup_el1_context(ctx, ep); 267 268 /* Initialize EL2 context registers */ 269 #if CTX_INCLUDE_EL2_REGS 270 271 /* 272 * Initialize SCTLR_EL2 context register using Endianness value 273 * taken from the entrypoint attribute. 274 */ 275 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 276 sctlr_el2 |= SCTLR_EL2_RES1; 277 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 278 sctlr_el2); 279 280 if (is_feat_hcx_supported()) { 281 /* 282 * Initialize register HCRX_EL2 with its init value. 283 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 284 * chance that this can lead to unexpected behavior in lower 285 * ELs that have not been updated since the introduction of 286 * this feature if not properly initialized, especially when 287 * it comes to those bits that enable/disable traps. 288 */ 289 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, 290 HCRX_EL2_INIT_VAL); 291 } 292 293 if (is_feat_fgt_supported()) { 294 /* 295 * Initialize HFG*_EL2 registers with a default value so legacy 296 * systems unaware of FEAT_FGT do not get trapped due to their lack 297 * of initialization for this feature. 298 */ 299 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2, 300 HFGITR_EL2_INIT_VAL); 301 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2, 302 HFGRTR_EL2_INIT_VAL); 303 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2, 304 HFGWTR_EL2_INIT_VAL); 305 } 306 #endif /* CTX_INCLUDE_EL2_REGS */ 307 308 manage_extensions_nonsecure(ctx); 309 } 310 311 /******************************************************************************* 312 * The following function performs initialization of the cpu_context 'ctx' 313 * for first use that is common to all security states, and sets the 314 * initial entrypoint state as specified by the entry_point_info structure. 315 * 316 * The EE and ST attributes are used to configure the endianness and secure 317 * timer availability for the new execution context. 318 ******************************************************************************/ 319 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 320 { 321 u_register_t scr_el3; 322 el3_state_t *state; 323 gp_regs_t *gp_regs; 324 325 state = get_el3state_ctx(ctx); 326 327 /* Clear any residual register values from the context */ 328 zeromem(ctx, sizeof(*ctx)); 329 330 /* 331 * The lower-EL context is zeroed so that no stale values leak to a world. 332 * It is assumed that an all-zero lower-EL context is good enough for it 333 * to boot correctly. However, there are very few registers where this 334 * is not true and some values need to be recreated. 335 */ 336 #if CTX_INCLUDE_EL2_REGS 337 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 338 339 /* 340 * These bits are set in the gicv3 driver. Losing them (especially the 341 * SRE bit) is problematic for all worlds. Henceforth recreate them. 342 */ 343 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 344 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 345 write_ctx_reg(el2_ctx, CTX_ICC_SRE_EL2, icc_sre_el2); 346 #endif /* CTX_INCLUDE_EL2_REGS */ 347 348 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 349 scr_el3 = SCR_RESET_VAL; 350 351 /* 352 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 353 * EL2, EL1 and EL0 are not trapped to EL3. 354 * 355 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 356 * EL2, EL1 and EL0 are not trapped to EL3. 357 * 358 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 359 * both Security states and both Execution states. 360 * 361 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 362 * Non-secure memory. 363 */ 364 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 365 366 scr_el3 |= SCR_SIF_BIT; 367 368 /* 369 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 370 * Exception level as specified by SPSR. 371 */ 372 if (GET_RW(ep->spsr) == MODE_RW_64) { 373 scr_el3 |= SCR_RW_BIT; 374 } 375 376 /* 377 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 378 * Secure timer registers to EL3, from AArch64 state only, if specified 379 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 380 * bit always behaves as 1 (i.e. secure physical timer register access 381 * is not trapped) 382 */ 383 if (EP_GET_ST(ep->h.attr) != 0U) { 384 scr_el3 |= SCR_ST_BIT; 385 } 386 387 /* 388 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 389 * SCR_EL3.HXEn. 390 */ 391 if (is_feat_hcx_supported()) { 392 scr_el3 |= SCR_HXEn_BIT; 393 } 394 395 /* 396 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 397 * registers are trapped to EL3. 398 */ 399 #if ENABLE_FEAT_RNG_TRAP 400 scr_el3 |= SCR_TRNDR_BIT; 401 #endif 402 403 #if FAULT_INJECTION_SUPPORT 404 /* Enable fault injection from lower ELs */ 405 scr_el3 |= SCR_FIEN_BIT; 406 #endif 407 408 #if CTX_INCLUDE_PAUTH_REGS 409 /* 410 * Enable Pointer Authentication globally for all the worlds. 411 * 412 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 413 * other than EL3 414 * 415 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 416 * than EL3 417 */ 418 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 419 #endif /* CTX_INCLUDE_PAUTH_REGS */ 420 421 /* 422 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 423 */ 424 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 425 scr_el3 |= SCR_TCR2EN_BIT; 426 } 427 428 /* 429 * SCR_EL3.PIEN: Enable permission indirection and overlay 430 * registers for AArch64 if present. 431 */ 432 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 433 scr_el3 |= SCR_PIEN_BIT; 434 } 435 436 /* 437 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 438 */ 439 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 440 scr_el3 |= SCR_GCSEn_BIT; 441 } 442 443 /* 444 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 445 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 446 * next mode is Hyp. 447 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 448 * same conditions as HVC instructions and when the processor supports 449 * ARMv8.6-FGT. 450 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 451 * CNTPOFF_EL2 register under the same conditions as HVC instructions 452 * and when the processor supports ECV. 453 */ 454 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 455 || ((GET_RW(ep->spsr) != MODE_RW_64) 456 && (GET_M32(ep->spsr) == MODE32_hyp))) { 457 scr_el3 |= SCR_HCE_BIT; 458 459 if (is_feat_fgt_supported()) { 460 scr_el3 |= SCR_FGTEN_BIT; 461 } 462 463 if (is_feat_ecv_supported()) { 464 scr_el3 |= SCR_ECVEN_BIT; 465 } 466 } 467 468 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 469 if (is_feat_twed_supported()) { 470 /* Set delay in SCR_EL3 */ 471 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 472 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 473 << SCR_TWEDEL_SHIFT); 474 475 /* Enable WFE delay */ 476 scr_el3 |= SCR_TWEDEn_BIT; 477 } 478 479 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 480 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 481 if (is_feat_sel2_supported()) { 482 scr_el3 |= SCR_EEL2_BIT; 483 } 484 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 485 486 /* 487 * Populate EL3 state so that we've the right context 488 * before doing ERET 489 */ 490 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 491 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 492 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 493 494 /* 495 * Store the X0-X7 value from the entrypoint into the context 496 * Use memcpy as we are in control of the layout of the structures 497 */ 498 gp_regs = get_gpregs_ctx(ctx); 499 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 500 } 501 502 /******************************************************************************* 503 * Context management library initialization routine. This library is used by 504 * runtime services to share pointers to 'cpu_context' structures for secure 505 * non-secure and realm states. Management of the structures and their associated 506 * memory is not done by the context management library e.g. the PSCI service 507 * manages the cpu context used for entry from and exit to the non-secure state. 508 * The Secure payload dispatcher service manages the context(s) corresponding to 509 * the secure state. It also uses this library to get access to the non-secure 510 * state cpu context pointers. 511 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 512 * which will be used for programming an entry into a lower EL. The same context 513 * will be used to save state upon exception entry from that EL. 514 ******************************************************************************/ 515 void __init cm_init(void) 516 { 517 /* 518 * The context management library has only global data to initialize, but 519 * that will be done when the BSS is zeroed out. 520 */ 521 } 522 523 /******************************************************************************* 524 * This is the high-level function used to initialize the cpu_context 'ctx' for 525 * first use. It performs initializations that are common to all security states 526 * and initializations specific to the security state specified in 'ep' 527 ******************************************************************************/ 528 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 529 { 530 unsigned int security_state; 531 532 assert(ctx != NULL); 533 534 /* 535 * Perform initializations that are common 536 * to all security states 537 */ 538 setup_context_common(ctx, ep); 539 540 security_state = GET_SECURITY_STATE(ep->h.attr); 541 542 /* Perform security state specific initializations */ 543 switch (security_state) { 544 case SECURE: 545 setup_secure_context(ctx, ep); 546 break; 547 #if ENABLE_RME 548 case REALM: 549 setup_realm_context(ctx, ep); 550 break; 551 #endif 552 case NON_SECURE: 553 setup_ns_context(ctx, ep); 554 break; 555 default: 556 ERROR("Invalid security state\n"); 557 panic(); 558 break; 559 } 560 } 561 562 /******************************************************************************* 563 * Enable architecture extensions for EL3 execution. This function only updates 564 * registers in-place which are expected to either never change or be 565 * overwritten by el3_exit. 566 ******************************************************************************/ 567 #if IMAGE_BL31 568 void cm_manage_extensions_el3(void) 569 { 570 if (is_feat_spe_supported()) { 571 spe_init_el3(); 572 } 573 574 if (is_feat_amu_supported()) { 575 amu_init_el3(); 576 } 577 578 if (is_feat_sme_supported()) { 579 sme_init_el3(); 580 } 581 582 if (is_feat_trbe_supported()) { 583 trbe_init_el3(); 584 } 585 586 if (is_feat_brbe_supported()) { 587 brbe_init_el3(); 588 } 589 590 if (is_feat_trf_supported()) { 591 trf_init_el3(); 592 } 593 594 pmuv3_init_el3(); 595 } 596 #endif /* IMAGE_BL31 */ 597 598 /****************************************************************************** 599 * Function to initialise the registers with the RESET values in the context 600 * memory, which are maintained per world. 601 ******************************************************************************/ 602 #if IMAGE_BL31 603 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 604 { 605 /* 606 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 607 * 608 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 609 * by Advanced SIMD, floating-point or SVE instructions (if 610 * implemented) do not trap to EL3. 611 * 612 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 613 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 614 */ 615 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 616 617 per_world_ctx->ctx_cptr_el3 = cptr_el3; 618 619 /* 620 * Initialize MPAM3_EL3 to its default reset value 621 * 622 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 623 * all lower ELn MPAM3_EL3 register access to, trap to EL3 624 */ 625 626 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 627 } 628 #endif /* IMAGE_BL31 */ 629 630 /******************************************************************************* 631 * Initialise per_world_context for Non-Secure world. 632 * This function enables the architecture extensions, which have same value 633 * across the cores for the non-secure world. 634 ******************************************************************************/ 635 #if IMAGE_BL31 636 void manage_extensions_nonsecure_per_world(void) 637 { 638 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 639 640 if (is_feat_sme_supported()) { 641 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 642 } 643 644 if (is_feat_sve_supported()) { 645 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 646 } 647 648 if (is_feat_amu_supported()) { 649 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 650 } 651 652 if (is_feat_sys_reg_trace_supported()) { 653 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 654 } 655 656 if (is_feat_mpam_supported()) { 657 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 658 } 659 } 660 #endif /* IMAGE_BL31 */ 661 662 /******************************************************************************* 663 * Initialise per_world_context for Secure world. 664 * This function enables the architecture extensions, which have same value 665 * across the cores for the secure world. 666 ******************************************************************************/ 667 static void manage_extensions_secure_per_world(void) 668 { 669 #if IMAGE_BL31 670 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 671 672 if (is_feat_sme_supported()) { 673 674 if (ENABLE_SME_FOR_SWD) { 675 /* 676 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 677 * SME, SVE, and FPU/SIMD context properly managed. 678 */ 679 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 680 } else { 681 /* 682 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 683 * world can safely use the associated registers. 684 */ 685 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 686 } 687 } 688 if (is_feat_sve_supported()) { 689 if (ENABLE_SVE_FOR_SWD) { 690 /* 691 * Enable SVE and FPU in secure context, SPM must ensure 692 * that the SVE and FPU register contexts are properly managed. 693 */ 694 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 695 } else { 696 /* 697 * Disable SVE and FPU in secure context so non-secure world 698 * can safely use them. 699 */ 700 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 701 } 702 } 703 704 /* NS can access this but Secure shouldn't */ 705 if (is_feat_sys_reg_trace_supported()) { 706 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 707 } 708 709 has_secure_perworld_init = true; 710 #endif /* IMAGE_BL31 */ 711 } 712 713 /******************************************************************************* 714 * Enable architecture extensions on first entry to Non-secure world. 715 ******************************************************************************/ 716 static void manage_extensions_nonsecure(cpu_context_t *ctx) 717 { 718 #if IMAGE_BL31 719 if (is_feat_amu_supported()) { 720 amu_enable(ctx); 721 } 722 723 if (is_feat_sme_supported()) { 724 sme_enable(ctx); 725 } 726 727 pmuv3_enable(ctx); 728 #endif /* IMAGE_BL31 */ 729 } 730 731 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 732 static __unused void enable_pauth_el2(void) 733 { 734 u_register_t hcr_el2 = read_hcr_el2(); 735 /* 736 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 737 * accessing key registers or using pointer authentication instructions 738 * from lower ELs. 739 */ 740 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 741 742 write_hcr_el2(hcr_el2); 743 } 744 745 #if INIT_UNUSED_NS_EL2 746 /******************************************************************************* 747 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 748 * world when EL2 is empty and unused. 749 ******************************************************************************/ 750 static void manage_extensions_nonsecure_el2_unused(void) 751 { 752 #if IMAGE_BL31 753 if (is_feat_spe_supported()) { 754 spe_init_el2_unused(); 755 } 756 757 if (is_feat_amu_supported()) { 758 amu_init_el2_unused(); 759 } 760 761 if (is_feat_mpam_supported()) { 762 mpam_init_el2_unused(); 763 } 764 765 if (is_feat_trbe_supported()) { 766 trbe_init_el2_unused(); 767 } 768 769 if (is_feat_sys_reg_trace_supported()) { 770 sys_reg_trace_init_el2_unused(); 771 } 772 773 if (is_feat_trf_supported()) { 774 trf_init_el2_unused(); 775 } 776 777 pmuv3_init_el2_unused(); 778 779 if (is_feat_sve_supported()) { 780 sve_init_el2_unused(); 781 } 782 783 if (is_feat_sme_supported()) { 784 sme_init_el2_unused(); 785 } 786 787 #if ENABLE_PAUTH 788 enable_pauth_el2(); 789 #endif /* ENABLE_PAUTH */ 790 #endif /* IMAGE_BL31 */ 791 } 792 #endif /* INIT_UNUSED_NS_EL2 */ 793 794 /******************************************************************************* 795 * Enable architecture extensions on first entry to Secure world. 796 ******************************************************************************/ 797 static void manage_extensions_secure(cpu_context_t *ctx) 798 { 799 #if IMAGE_BL31 800 if (is_feat_sme_supported()) { 801 if (ENABLE_SME_FOR_SWD) { 802 /* 803 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 804 * must ensure SME, SVE, and FPU/SIMD context properly managed. 805 */ 806 sme_init_el3(); 807 sme_enable(ctx); 808 } else { 809 /* 810 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 811 * world can safely use the associated registers. 812 */ 813 sme_disable(ctx); 814 } 815 } 816 #endif /* IMAGE_BL31 */ 817 } 818 819 /******************************************************************************* 820 * The following function initializes the cpu_context for a CPU specified by 821 * its `cpu_idx` for first use, and sets the initial entrypoint state as 822 * specified by the entry_point_info structure. 823 ******************************************************************************/ 824 void cm_init_context_by_index(unsigned int cpu_idx, 825 const entry_point_info_t *ep) 826 { 827 cpu_context_t *ctx; 828 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 829 cm_setup_context(ctx, ep); 830 } 831 832 /******************************************************************************* 833 * The following function initializes the cpu_context for the current CPU 834 * for first use, and sets the initial entrypoint state as specified by the 835 * entry_point_info structure. 836 ******************************************************************************/ 837 void cm_init_my_context(const entry_point_info_t *ep) 838 { 839 cpu_context_t *ctx; 840 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 841 cm_setup_context(ctx, ep); 842 } 843 844 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 845 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 846 { 847 #if INIT_UNUSED_NS_EL2 848 u_register_t hcr_el2 = HCR_RESET_VAL; 849 u_register_t mdcr_el2; 850 u_register_t scr_el3; 851 852 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 853 854 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 855 if ((scr_el3 & SCR_RW_BIT) != 0U) { 856 hcr_el2 |= HCR_RW_BIT; 857 } 858 859 write_hcr_el2(hcr_el2); 860 861 /* 862 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 863 * All fields have architecturally UNKNOWN reset values. 864 */ 865 write_cptr_el2(CPTR_EL2_RESET_VAL); 866 867 /* 868 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 869 * reset and are set to zero except for field(s) listed below. 870 * 871 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 872 * Non-secure EL0 and EL1 accesses to the physical timer registers. 873 * 874 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 875 * Non-secure EL0 and EL1 accesses to the physical counter registers. 876 */ 877 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 878 879 /* 880 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 881 * UNKNOWN value. 882 */ 883 write_cntvoff_el2(0); 884 885 /* 886 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 887 * respectively. 888 */ 889 write_vpidr_el2(read_midr_el1()); 890 write_vmpidr_el2(read_mpidr_el1()); 891 892 /* 893 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 894 * 895 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 896 * translation is disabled, cache maintenance operations depend on the 897 * VMID. 898 * 899 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 900 * disabled. 901 */ 902 write_vttbr_el2(VTTBR_RESET_VAL & 903 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 904 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 905 906 /* 907 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 908 * Some fields are architecturally UNKNOWN on reset. 909 * 910 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 911 * register accesses to the Debug ROM registers are not trapped to EL2. 912 * 913 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 914 * accesses to the powerdown debug registers are not trapped to EL2. 915 * 916 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 917 * debug registers do not trap to EL2. 918 * 919 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 920 * EL2. 921 */ 922 mdcr_el2 = MDCR_EL2_RESET_VAL & 923 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 924 MDCR_EL2_TDE_BIT); 925 926 write_mdcr_el2(mdcr_el2); 927 928 /* 929 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 930 * 931 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 932 * EL1 accesses to System registers do not trap to EL2. 933 */ 934 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 935 936 /* 937 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 938 * reset. 939 * 940 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 941 * and prevent timer interrupts. 942 */ 943 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 944 945 manage_extensions_nonsecure_el2_unused(); 946 #endif /* INIT_UNUSED_NS_EL2 */ 947 } 948 949 /******************************************************************************* 950 * Prepare the CPU system registers for first entry into realm, secure, or 951 * normal world. 952 * 953 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 954 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 955 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 956 * For all entries, the EL1 registers are initialized from the cpu_context 957 ******************************************************************************/ 958 void cm_prepare_el3_exit(uint32_t security_state) 959 { 960 u_register_t sctlr_elx, scr_el3; 961 cpu_context_t *ctx = cm_get_context(security_state); 962 963 assert(ctx != NULL); 964 965 if (security_state == NON_SECURE) { 966 uint64_t el2_implemented = el_implemented(2); 967 968 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 969 CTX_SCR_EL3); 970 971 if (((scr_el3 & SCR_HCE_BIT) != 0U) 972 || (el2_implemented != EL_IMPL_NONE)) { 973 /* 974 * If context is not being used for EL2, initialize 975 * HCRX_EL2 with its init value here. 976 */ 977 if (is_feat_hcx_supported()) { 978 write_hcrx_el2(HCRX_EL2_INIT_VAL); 979 } 980 981 /* 982 * Initialize Fine-grained trap registers introduced 983 * by FEAT_FGT so all traps are initially disabled when 984 * switching to EL2 or a lower EL, preventing undesired 985 * behavior. 986 */ 987 if (is_feat_fgt_supported()) { 988 /* 989 * Initialize HFG*_EL2 registers with a default 990 * value so legacy systems unaware of FEAT_FGT 991 * do not get trapped due to their lack of 992 * initialization for this feature. 993 */ 994 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 995 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 996 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 997 } 998 } 999 1000 1001 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1002 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 1003 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 1004 CTX_SCTLR_EL1); 1005 sctlr_elx &= SCTLR_EE_BIT; 1006 sctlr_elx |= SCTLR_EL2_RES1; 1007 #if ERRATA_A75_764081 1008 /* 1009 * If workaround of errata 764081 for Cortex-A75 is used 1010 * then set SCTLR_EL2.IESB to enable Implicit Error 1011 * Synchronization Barrier. 1012 */ 1013 sctlr_elx |= SCTLR_IESB_BIT; 1014 #endif 1015 write_sctlr_el2(sctlr_elx); 1016 } else if (el2_implemented != EL_IMPL_NONE) { 1017 init_nonsecure_el2_unused(ctx); 1018 } 1019 } 1020 1021 cm_el1_sysregs_context_restore(security_state); 1022 cm_set_next_eret_context(security_state); 1023 } 1024 1025 #if CTX_INCLUDE_EL2_REGS 1026 1027 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1028 { 1029 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 1030 if (is_feat_amu_supported()) { 1031 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 1032 } 1033 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 1034 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 1035 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 1036 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 1037 } 1038 1039 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1040 { 1041 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 1042 if (is_feat_amu_supported()) { 1043 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 1044 } 1045 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 1046 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 1047 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 1048 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 1049 } 1050 1051 #if CTX_INCLUDE_MPAM_REGS 1052 1053 static void el2_sysregs_context_save_mpam(mpam_t *ctx) 1054 { 1055 u_register_t mpam_idr = read_mpamidr_el1(); 1056 1057 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 1058 1059 /* 1060 * The context registers that we intend to save would be part of the 1061 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1062 */ 1063 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1064 return; 1065 } 1066 1067 /* 1068 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1069 * MPAMIDR_HAS_HCR_BIT == 1. 1070 */ 1071 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 1072 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 1073 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 1074 1075 /* 1076 * The number of MPAMVPM registers is implementation defined, their 1077 * number is stored in the MPAMIDR_EL1 register. 1078 */ 1079 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1080 case 7: 1081 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 1082 __fallthrough; 1083 case 6: 1084 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 1085 __fallthrough; 1086 case 5: 1087 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 1088 __fallthrough; 1089 case 4: 1090 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 1091 __fallthrough; 1092 case 3: 1093 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 1094 __fallthrough; 1095 case 2: 1096 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 1097 __fallthrough; 1098 case 1: 1099 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 1100 break; 1101 } 1102 } 1103 1104 #endif /* CTX_INCLUDE_MPAM_REGS */ 1105 1106 #if CTX_INCLUDE_MPAM_REGS 1107 static void el2_sysregs_context_restore_mpam(mpam_t *ctx) 1108 { 1109 u_register_t mpam_idr = read_mpamidr_el1(); 1110 1111 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 1112 1113 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1114 return; 1115 } 1116 1117 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 1118 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 1119 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 1120 1121 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1122 case 7: 1123 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 1124 __fallthrough; 1125 case 6: 1126 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 1127 __fallthrough; 1128 case 5: 1129 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 1130 __fallthrough; 1131 case 4: 1132 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 1133 __fallthrough; 1134 case 3: 1135 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 1136 __fallthrough; 1137 case 2: 1138 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 1139 __fallthrough; 1140 case 1: 1141 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 1142 break; 1143 } 1144 } 1145 #endif /* CTX_INCLUDE_MPAM_REGS */ 1146 1147 /* ----------------------------------------------------- 1148 * The following registers are not added: 1149 * AMEVCNTVOFF0<n>_EL2 1150 * AMEVCNTVOFF1<n>_EL2 1151 * ICH_AP0R<n>_EL2 1152 * ICH_AP1R<n>_EL2 1153 * ICH_LR<n>_EL2 1154 * ----------------------------------------------------- 1155 */ 1156 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1157 { 1158 write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2()); 1159 write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2()); 1160 write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2()); 1161 write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2()); 1162 write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2()); 1163 write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2()); 1164 write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2()); 1165 if (CTX_INCLUDE_AARCH32_REGS) { 1166 write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2()); 1167 } 1168 write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2()); 1169 write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2()); 1170 write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2()); 1171 write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2()); 1172 write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2()); 1173 write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2()); 1174 write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2()); 1175 1176 /* 1177 * Set the NS bit to be able to access the ICC_SRE_EL2 register 1178 * TODO: remove with root context 1179 */ 1180 u_register_t scr_el3 = read_scr_el3(); 1181 1182 write_scr_el3(scr_el3 | SCR_NS_BIT); 1183 isb(); 1184 write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2()); 1185 1186 write_scr_el3(scr_el3); 1187 isb(); 1188 1189 write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2()); 1190 write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2()); 1191 write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2()); 1192 write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2()); 1193 write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2()); 1194 write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2()); 1195 write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2()); 1196 write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2()); 1197 write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2()); 1198 write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2()); 1199 write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2()); 1200 write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2()); 1201 write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2()); 1202 write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2()); 1203 write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2()); 1204 } 1205 1206 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1207 { 1208 write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2)); 1209 write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2)); 1210 write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2)); 1211 write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2)); 1212 write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2)); 1213 write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2)); 1214 write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2)); 1215 if (CTX_INCLUDE_AARCH32_REGS) { 1216 write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2)); 1217 } 1218 write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2)); 1219 write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2)); 1220 write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2)); 1221 write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2)); 1222 write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2)); 1223 write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2)); 1224 write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2)); 1225 1226 /* 1227 * Set the NS bit to be able to access the ICC_SRE_EL2 register 1228 * TODO: remove with root context 1229 */ 1230 u_register_t scr_el3 = read_scr_el3(); 1231 1232 write_scr_el3(scr_el3 | SCR_NS_BIT); 1233 isb(); 1234 write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2)); 1235 1236 write_scr_el3(scr_el3); 1237 isb(); 1238 1239 write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2)); 1240 write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2)); 1241 write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2)); 1242 write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2)); 1243 write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2)); 1244 write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2)); 1245 write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2)); 1246 write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2)); 1247 write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2)); 1248 write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2)); 1249 write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2)); 1250 write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2)); 1251 write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2)); 1252 write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2)); 1253 write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2)); 1254 } 1255 1256 /******************************************************************************* 1257 * Save EL2 sysreg context 1258 ******************************************************************************/ 1259 void cm_el2_sysregs_context_save(uint32_t security_state) 1260 { 1261 cpu_context_t *ctx; 1262 el2_sysregs_t *el2_sysregs_ctx; 1263 1264 ctx = cm_get_context(security_state); 1265 assert(ctx != NULL); 1266 1267 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1268 1269 el2_sysregs_context_save_common(el2_sysregs_ctx); 1270 #if CTX_INCLUDE_MTE_REGS 1271 write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2()); 1272 #endif 1273 1274 #if CTX_INCLUDE_MPAM_REGS 1275 if (is_feat_mpam_supported()) { 1276 mpam_t *mpam_ctx = get_mpam_ctx(ctx); 1277 el2_sysregs_context_save_mpam(mpam_ctx); 1278 } 1279 #endif 1280 1281 if (is_feat_fgt_supported()) { 1282 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1283 } 1284 1285 if (is_feat_ecv_v2_supported()) { 1286 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, read_cntpoff_el2()); 1287 } 1288 1289 if (is_feat_vhe_supported()) { 1290 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, read_contextidr_el2()); 1291 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, read_ttbr1_el2()); 1292 } 1293 1294 if (is_feat_ras_supported()) { 1295 write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, read_vdisr_el2()); 1296 write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, read_vsesr_el2()); 1297 } 1298 1299 if (is_feat_nv2_supported()) { 1300 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, read_vncr_el2()); 1301 } 1302 1303 if (is_feat_trf_supported()) { 1304 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 1305 } 1306 1307 if (is_feat_csv2_2_supported()) { 1308 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, read_scxtnum_el2()); 1309 } 1310 1311 if (is_feat_hcx_supported()) { 1312 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1313 } 1314 if (is_feat_tcr2_supported()) { 1315 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1316 } 1317 if (is_feat_sxpie_supported()) { 1318 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); 1319 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); 1320 } 1321 if (is_feat_s2pie_supported()) { 1322 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); 1323 } 1324 if (is_feat_sxpoe_supported()) { 1325 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); 1326 } 1327 if (is_feat_gcs_supported()) { 1328 write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); 1329 write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); 1330 } 1331 } 1332 1333 /******************************************************************************* 1334 * Restore EL2 sysreg context 1335 ******************************************************************************/ 1336 void cm_el2_sysregs_context_restore(uint32_t security_state) 1337 { 1338 cpu_context_t *ctx; 1339 el2_sysregs_t *el2_sysregs_ctx; 1340 1341 ctx = cm_get_context(security_state); 1342 assert(ctx != NULL); 1343 1344 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1345 1346 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1347 #if CTX_INCLUDE_MTE_REGS 1348 write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2)); 1349 #endif 1350 1351 #if CTX_INCLUDE_MPAM_REGS 1352 if (is_feat_mpam_supported()) { 1353 mpam_t *mpam_ctx = get_mpam_ctx(ctx); 1354 el2_sysregs_context_restore_mpam(mpam_ctx); 1355 } 1356 #endif 1357 1358 if (is_feat_fgt_supported()) { 1359 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1360 } 1361 1362 if (is_feat_ecv_v2_supported()) { 1363 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2)); 1364 } 1365 1366 if (is_feat_vhe_supported()) { 1367 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1368 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1369 } 1370 1371 if (is_feat_ras_supported()) { 1372 write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); 1373 write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); 1374 } 1375 1376 if (is_feat_nv2_supported()) { 1377 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1378 } 1379 if (is_feat_trf_supported()) { 1380 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1381 } 1382 1383 if (is_feat_csv2_2_supported()) { 1384 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2)); 1385 } 1386 1387 if (is_feat_hcx_supported()) { 1388 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1389 } 1390 if (is_feat_tcr2_supported()) { 1391 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1392 } 1393 if (is_feat_sxpie_supported()) { 1394 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); 1395 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); 1396 } 1397 if (is_feat_s2pie_supported()) { 1398 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); 1399 } 1400 if (is_feat_sxpoe_supported()) { 1401 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); 1402 } 1403 if (is_feat_gcs_supported()) { 1404 write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); 1405 write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); 1406 } 1407 } 1408 #endif /* CTX_INCLUDE_EL2_REGS */ 1409 1410 /******************************************************************************* 1411 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1412 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1413 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1414 * cm_prepare_el3_exit function. 1415 ******************************************************************************/ 1416 void cm_prepare_el3_exit_ns(void) 1417 { 1418 #if CTX_INCLUDE_EL2_REGS 1419 #if ENABLE_ASSERTIONS 1420 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1421 assert(ctx != NULL); 1422 1423 /* Assert that EL2 is used. */ 1424 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1425 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1426 (el_implemented(2U) != EL_IMPL_NONE)); 1427 #endif /* ENABLE_ASSERTIONS */ 1428 1429 /* Restore EL2 and EL1 sysreg contexts */ 1430 cm_el2_sysregs_context_restore(NON_SECURE); 1431 cm_el1_sysregs_context_restore(NON_SECURE); 1432 cm_set_next_eret_context(NON_SECURE); 1433 #else 1434 cm_prepare_el3_exit(NON_SECURE); 1435 #endif /* CTX_INCLUDE_EL2_REGS */ 1436 } 1437 1438 /******************************************************************************* 1439 * The next four functions are used by runtime services to save and restore 1440 * EL1 context on the 'cpu_context' structure for the specified security 1441 * state. 1442 ******************************************************************************/ 1443 void cm_el1_sysregs_context_save(uint32_t security_state) 1444 { 1445 cpu_context_t *ctx; 1446 1447 ctx = cm_get_context(security_state); 1448 assert(ctx != NULL); 1449 1450 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1451 1452 #if IMAGE_BL31 1453 if (security_state == SECURE) 1454 PUBLISH_EVENT(cm_exited_secure_world); 1455 else 1456 PUBLISH_EVENT(cm_exited_normal_world); 1457 #endif 1458 } 1459 1460 void cm_el1_sysregs_context_restore(uint32_t security_state) 1461 { 1462 cpu_context_t *ctx; 1463 1464 ctx = cm_get_context(security_state); 1465 assert(ctx != NULL); 1466 1467 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1468 1469 #if IMAGE_BL31 1470 if (security_state == SECURE) 1471 PUBLISH_EVENT(cm_entering_secure_world); 1472 else 1473 PUBLISH_EVENT(cm_entering_normal_world); 1474 #endif 1475 } 1476 1477 /******************************************************************************* 1478 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1479 * given security state with the given entrypoint 1480 ******************************************************************************/ 1481 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1482 { 1483 cpu_context_t *ctx; 1484 el3_state_t *state; 1485 1486 ctx = cm_get_context(security_state); 1487 assert(ctx != NULL); 1488 1489 /* Populate EL3 state so that ERET jumps to the correct entry */ 1490 state = get_el3state_ctx(ctx); 1491 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1492 } 1493 1494 /******************************************************************************* 1495 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1496 * pertaining to the given security state 1497 ******************************************************************************/ 1498 void cm_set_elr_spsr_el3(uint32_t security_state, 1499 uintptr_t entrypoint, uint32_t spsr) 1500 { 1501 cpu_context_t *ctx; 1502 el3_state_t *state; 1503 1504 ctx = cm_get_context(security_state); 1505 assert(ctx != NULL); 1506 1507 /* Populate EL3 state so that ERET jumps to the correct entry */ 1508 state = get_el3state_ctx(ctx); 1509 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1510 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1511 } 1512 1513 /******************************************************************************* 1514 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1515 * pertaining to the given security state using the value and bit position 1516 * specified in the parameters. It preserves all other bits. 1517 ******************************************************************************/ 1518 void cm_write_scr_el3_bit(uint32_t security_state, 1519 uint32_t bit_pos, 1520 uint32_t value) 1521 { 1522 cpu_context_t *ctx; 1523 el3_state_t *state; 1524 u_register_t scr_el3; 1525 1526 ctx = cm_get_context(security_state); 1527 assert(ctx != NULL); 1528 1529 /* Ensure that the bit position is a valid one */ 1530 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1531 1532 /* Ensure that the 'value' is only a bit wide */ 1533 assert(value <= 1U); 1534 1535 /* 1536 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1537 * and set it to its new value. 1538 */ 1539 state = get_el3state_ctx(ctx); 1540 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1541 scr_el3 &= ~(1UL << bit_pos); 1542 scr_el3 |= (u_register_t)value << bit_pos; 1543 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1544 } 1545 1546 /******************************************************************************* 1547 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1548 * given security state. 1549 ******************************************************************************/ 1550 u_register_t cm_get_scr_el3(uint32_t security_state) 1551 { 1552 cpu_context_t *ctx; 1553 el3_state_t *state; 1554 1555 ctx = cm_get_context(security_state); 1556 assert(ctx != NULL); 1557 1558 /* Populate EL3 state so that ERET jumps to the correct entry */ 1559 state = get_el3state_ctx(ctx); 1560 return read_ctx_reg(state, CTX_SCR_EL3); 1561 } 1562 1563 /******************************************************************************* 1564 * This function is used to program the context that's used for exception 1565 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1566 * the required security state 1567 ******************************************************************************/ 1568 void cm_set_next_eret_context(uint32_t security_state) 1569 { 1570 cpu_context_t *ctx; 1571 1572 ctx = cm_get_context(security_state); 1573 assert(ctx != NULL); 1574 1575 cm_set_next_context(ctx); 1576 } 1577