1 /* 2 * Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/cpa2.h> 30 #include <lib/extensions/debug_v8p9.h> 31 #include <lib/extensions/fgt2.h> 32 #include <lib/extensions/idte3.h> 33 #include <lib/extensions/mpam.h> 34 #include <lib/extensions/pauth.h> 35 #include <lib/extensions/pmuv3.h> 36 #include <lib/extensions/sme.h> 37 #include <lib/extensions/spe.h> 38 #include <lib/extensions/sve.h> 39 #include <lib/extensions/sysreg128.h> 40 #include <lib/extensions/sys_reg_trace.h> 41 #include <lib/extensions/tcr2.h> 42 #include <lib/extensions/trbe.h> 43 #include <lib/extensions/trf.h> 44 #include <lib/utils.h> 45 46 #if ENABLE_FEAT_TWED 47 /* Make sure delay value fits within the range(0-15) */ 48 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 49 #endif /* ENABLE_FEAT_TWED */ 50 51 per_world_context_t per_world_context[CPU_CONTEXT_NUM]; 52 PER_CPU_DEFINE(world_amu_regs_t, world_amu_ctx[CPU_CONTEXT_NUM]); 53 54 static void manage_extensions_nonsecure(cpu_context_t *ctx); 55 static void manage_extensions_secure(cpu_context_t *ctx); 56 57 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 58 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 59 { 60 u_register_t sctlr_elx, actlr_elx; 61 62 /* 63 * Initialise SCTLR_EL1 to the reset value corresponding to the target 64 * execution state setting all fields rather than relying on the hw. 65 * Some fields have architecturally UNKNOWN reset values and these are 66 * set to zero. 67 * 68 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 69 * 70 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 71 * required by PSCI specification) 72 */ 73 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 74 if (GET_RW(ep->spsr) == MODE_RW_64) { 75 sctlr_elx |= SCTLR_EL1_RES1; 76 } else { 77 /* 78 * If the target execution state is AArch32 then the following 79 * fields need to be set. 80 * 81 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 82 * instructions are not trapped to EL1. 83 * 84 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 85 * instructions are not trapped to EL1. 86 * 87 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 88 * CP15DMB, CP15DSB, and CP15ISB instructions. 89 */ 90 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 91 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 92 } 93 94 /* 95 * If workaround of errata 764081 for Cortex-A75 is used then set 96 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 97 */ 98 if (errata_a75_764081_applies()) { 99 sctlr_elx |= SCTLR_IESB_BIT; 100 } 101 102 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 103 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 104 105 /* 106 * Base the context ACTLR_EL1 on the current value, as it is 107 * implementation defined. The context restore process will write 108 * the value from the context to the actual register and can cause 109 * problems for processor cores that don't expect certain bits to 110 * be zero. 111 */ 112 actlr_elx = read_actlr_el1(); 113 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 114 } 115 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 116 117 /****************************************************************************** 118 * This function performs initializations that are specific to SECURE state 119 * and updates the cpu context specified by 'ctx'. 120 *****************************************************************************/ 121 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 122 { 123 u_register_t scr_el3; 124 el3_state_t *state; 125 126 state = get_el3state_ctx(ctx); 127 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 128 129 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 130 /* 131 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 132 * indicated by the interrupt routing model for BL31. 133 */ 134 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 135 #endif 136 137 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 138 if (is_feat_mte2_supported()) { 139 scr_el3 |= SCR_ATA_BIT; 140 } 141 142 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 143 144 /* 145 * Initialize EL1 context registers unless SPMC is running 146 * at S-EL2. 147 */ 148 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1 149 setup_el1_context(ctx, ep); 150 #endif 151 152 manage_extensions_secure(ctx); 153 } 154 155 #if ENABLE_RME && IMAGE_BL31 156 /****************************************************************************** 157 * This function performs initializations that are specific to REALM state 158 * and updates the cpu context specified by 'ctx'. 159 * 160 * NOTE: any changes to this function must be verified by an RMMD maintainer. 161 *****************************************************************************/ 162 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 163 { 164 u_register_t scr_el3; 165 el3_state_t *state; 166 el2_sysregs_t *el2_ctx; 167 168 state = get_el3state_ctx(ctx); 169 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 170 el2_ctx = get_el2_sysregs_ctx(ctx); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 173 174 write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM); 175 176 /* CSV2 version 2 and above */ 177 if (is_feat_csv2_2_supported()) { 178 /* Enable access to the SCXTNUM_ELx registers. */ 179 scr_el3 |= SCR_EnSCXT_BIT; 180 } 181 182 if (is_feat_sctlr2_supported()) { 183 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 184 * SCTLR2_ELx registers. 185 */ 186 scr_el3 |= SCR_SCTLR2En_BIT; 187 } 188 189 if (is_feat_d128_supported()) { 190 /* 191 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 192 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 193 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 194 */ 195 scr_el3 |= SCR_D128En_BIT; 196 } 197 198 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 199 200 if (is_feat_fgt2_supported()) { 201 fgt2_enable(ctx); 202 } 203 204 if (is_feat_debugv8p9_supported()) { 205 debugv8p9_extended_bp_wp_enable(ctx); 206 } 207 208 if (is_feat_brbe_supported()) { 209 brbe_enable(ctx); 210 } 211 212 /* 213 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world. 214 */ 215 if (is_feat_sme_supported()) { 216 sme_enable(ctx); 217 } 218 219 if (is_feat_spe_supported()) { 220 spe_disable_realm(ctx); 221 } 222 223 if (is_feat_trbe_supported()) { 224 trbe_disable_realm(ctx); 225 } 226 } 227 #endif /* ENABLE_RME && IMAGE_BL31 */ 228 229 /****************************************************************************** 230 * This function performs initializations that are specific to NON-SECURE state 231 * and updates the cpu context specified by 'ctx'. 232 *****************************************************************************/ 233 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 234 { 235 u_register_t scr_el3; 236 el3_state_t *state; 237 238 state = get_el3state_ctx(ctx); 239 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 240 241 /* SCR_NS: Set the NS bit */ 242 scr_el3 |= SCR_NS_BIT; 243 244 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 245 if (is_feat_mte2_supported()) { 246 scr_el3 |= SCR_ATA_BIT; 247 } 248 249 /* 250 * Pointer Authentication feature, if present, is always enabled by 251 * default for Non secure lower exception levels. We do not have an 252 * explicit flag to set it. To prevent the leakage between the worlds 253 * during world switch, we enable it only for the non-secure world. 254 * 255 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 256 * exception levels of secure and realm worlds. 257 * 258 * If the Secure/realm world wants to use pointer authentication, 259 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 260 * it will be enabled globally for all the contexts. 261 * 262 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 263 * other than EL3 264 * 265 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 266 * than EL3 267 */ 268 if (!is_ctx_pauth_supported()) { 269 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 270 } 271 272 #if HANDLE_EA_EL3_FIRST_NS 273 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 274 scr_el3 |= SCR_EA_BIT; 275 #endif 276 277 #if RAS_TRAP_NS_ERR_REC_ACCESS 278 /* 279 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 280 * and RAS ERX registers from EL1 and EL2(from any security state) 281 * are trapped to EL3. 282 * Set here to trap only for NS EL1/EL2 283 */ 284 scr_el3 |= SCR_TERR_BIT; 285 #endif 286 287 /* CSV2 version 2 and above */ 288 if (is_feat_csv2_2_supported()) { 289 /* Enable access to the SCXTNUM_ELx registers. */ 290 scr_el3 |= SCR_EnSCXT_BIT; 291 } 292 293 #ifdef IMAGE_BL31 294 /* 295 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 296 * indicated by the interrupt routing model for BL31. 297 */ 298 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 299 #endif 300 301 if (is_feat_the_supported()) { 302 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 303 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 304 */ 305 scr_el3 |= SCR_RCWMASKEn_BIT; 306 } 307 308 if (is_feat_sctlr2_supported()) { 309 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 310 * SCTLR2_ELx registers. 311 */ 312 scr_el3 |= SCR_SCTLR2En_BIT; 313 } 314 315 if (is_feat_d128_supported()) { 316 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 317 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 318 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 319 */ 320 scr_el3 |= SCR_D128En_BIT; 321 } 322 323 if (is_feat_fpmr_supported()) { 324 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 325 * register. 326 */ 327 scr_el3 |= SCR_EnFPM_BIT; 328 } 329 330 if (is_feat_aie_supported()) { 331 /* Set the AIEn bit in SCR_EL3 to enable access to (A)MAIR2 332 * system registers from NS world. 333 */ 334 scr_el3 |= SCR_AIEn_BIT; 335 } 336 337 if (is_feat_pfar_supported()) { 338 /* Set the PFAREn bit in SCR_EL3 to enable access to the PFAR 339 * system registers from NS world. 340 */ 341 scr_el3 |= SCR_PFAREn_BIT; 342 } 343 344 if (is_feat_hdbss_supported()) { 345 /* Set the HDBSSEn bit to enable access to hdbssbr_el2 and 346 * hdbssprod_el2 347 */ 348 scr_el3 |= SCR_HDBSSEn_BIT; 349 } 350 351 if (is_feat_hacdbs_supported()) { 352 /* Set the HACDBSEn bit to enable access to hacdbsbr_el2 and 353 * hacdbscons_el2 354 */ 355 scr_el3 |= SCR_HACDBSEn_BIT; 356 } 357 358 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 359 360 /* Initialize EL2 context registers */ 361 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 362 if (is_feat_hcx_supported()) { 363 /* 364 * Initialize register HCRX_EL2 with its init value. 365 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 366 * chance that this can lead to unexpected behavior in lower 367 * ELs that have not been updated since the introduction of 368 * this feature if not properly initialized, especially when 369 * it comes to those bits that enable/disable traps. 370 */ 371 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 372 HCRX_EL2_INIT_VAL); 373 } 374 375 if (is_feat_fgt_supported()) { 376 /* 377 * Initialize HFG*_EL2 registers with a default value so legacy 378 * systems unaware of FEAT_FGT do not get trapped due to their lack 379 * of initialization for this feature. 380 */ 381 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 382 HFGITR_EL2_INIT_VAL); 383 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 384 HFGRTR_EL2_INIT_VAL); 385 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 386 HFGWTR_EL2_INIT_VAL); 387 } 388 #else 389 /* Initialize EL1 context registers */ 390 setup_el1_context(ctx, ep); 391 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 392 393 manage_extensions_nonsecure(ctx); 394 } 395 396 static inline ddc_cap_t read_ddc_el0 (void) 397 { 398 ddc_cap_t val = NULL; 399 #if ENABLE_FEAT_MORELLO 400 __asm__ volatile ("msr spsel, #1 \n" 401 "mrs %0, ddc \n" 402 "msr spsel, #0 \n" 403 : "=C"(val) 404 : 405 : "memory" 406 ); 407 #endif 408 return val; 409 } 410 411 /******************************************************************************* 412 * The following function performs initialization of the cpu_context 'ctx' 413 * for first use that is common to all security states, and sets the 414 * initial entrypoint state as specified by the entry_point_info structure. 415 * 416 * The EE and ST attributes are used to configure the endianness and secure 417 * timer availability for the new execution context. 418 ******************************************************************************/ 419 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 420 { 421 u_register_t scr_el3; 422 u_register_t mdcr_el3; 423 el3_state_t *state; 424 gp_regs_t *gp_regs; 425 426 state = get_el3state_ctx(ctx); 427 428 /* Clear any residual register values from the context */ 429 zeromem(ctx, sizeof(*ctx)); 430 431 /* 432 * The lower-EL context is zeroed so that no stale values leak to a world. 433 * It is assumed that an all-zero lower-EL context is good enough for it 434 * to boot correctly. However, there are very few registers where this 435 * is not true and some values need to be recreated. 436 */ 437 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 438 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 439 440 /* 441 * These bits are set in the gicv3 driver. Losing them (especially the 442 * SRE bit) is problematic for all worlds. Henceforth recreate them. 443 */ 444 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 445 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 446 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 447 448 /* 449 * The actlr_el2 register can be initialized in platform's reset handler 450 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 451 */ 452 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 453 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 454 455 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 456 scr_el3 = SCR_RESET_VAL; 457 458 /* 459 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 460 * EL2, EL1 and EL0 are not trapped to EL3. 461 * 462 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 463 * EL2, EL1 and EL0 are not trapped to EL3. 464 * 465 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 466 * both Security states and both Execution states. 467 * 468 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 469 * Non-secure memory. 470 */ 471 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 472 473 scr_el3 |= SCR_SIF_BIT; 474 475 /* 476 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 477 * Exception level as specified by SPSR. 478 */ 479 if (GET_RW(ep->spsr) == MODE_RW_64) { 480 scr_el3 |= SCR_RW_BIT; 481 } 482 483 /* 484 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 485 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 486 * next mode is Hyp. 487 */ 488 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 489 || ((GET_RW(ep->spsr) != MODE_RW_64) 490 && (GET_M32(ep->spsr) == MODE32_hyp))) { 491 scr_el3 |= SCR_HCE_BIT; 492 } 493 494 /* 495 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 496 * Secure timer registers to EL3, from AArch64 state only, if specified 497 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 498 * bit always behaves as 1 (i.e. secure physical timer register access 499 * is not trapped) 500 */ 501 if (EP_GET_ST(ep->h.attr) != 0U) { 502 scr_el3 |= SCR_ST_BIT; 503 } 504 505 /* 506 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 507 * SCR_EL3.HXEn. 508 */ 509 if (is_feat_hcx_supported()) { 510 scr_el3 |= SCR_HXEn_BIT; 511 } 512 513 /* 514 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 515 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 516 * SCR_EL3.EnAS0. 517 */ 518 if (is_feat_ls64_accdata_supported()) { 519 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 520 } 521 522 /* 523 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 524 * registers are trapped to EL3. 525 */ 526 if (is_feat_rng_trap_supported()) { 527 scr_el3 |= SCR_TRNDR_BIT; 528 } 529 530 #if FAULT_INJECTION_SUPPORT 531 /* Enable fault injection from lower ELs */ 532 scr_el3 |= SCR_FIEN_BIT; 533 #endif 534 535 /* 536 * Enable Pointer Authentication globally for all the worlds. 537 * 538 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 539 * other than EL3 540 * 541 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 542 * than EL3 543 */ 544 if (is_ctx_pauth_supported()) { 545 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 546 } 547 548 /* 549 * SCR_EL3.PIEN: Enable permission indirection and overlay 550 * registers for AArch64 if present. 551 */ 552 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 553 scr_el3 |= SCR_PIEN_BIT; 554 } 555 556 /* SCR_EL3.GCSEn: Enable GCS registers. */ 557 if (is_feat_gcs_supported()) { 558 scr_el3 |= SCR_GCSEn_BIT; 559 } 560 561 /* SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps */ 562 if (is_feat_fgt_supported()) { 563 scr_el3 |= SCR_FGTEN_BIT; 564 } 565 566 /* SCR_EL3.ECVEn: Do not trap the CNTPOFF_EL2 register */ 567 if (is_feat_ecv_supported()) { 568 scr_el3 |= SCR_ECVEN_BIT; 569 } 570 571 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 572 if (is_feat_twed_supported()) { 573 /* Set delay in SCR_EL3 */ 574 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 575 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 576 << SCR_TWEDEL_SHIFT); 577 578 /* Enable WFE delay */ 579 scr_el3 |= SCR_TWEDEn_BIT; 580 } 581 582 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 583 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 584 if (is_feat_sel2_supported()) { 585 scr_el3 |= SCR_EEL2_BIT; 586 } 587 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 588 589 if (is_feat_mec_supported()) { 590 scr_el3 |= SCR_MECEn_BIT; 591 } 592 593 /* 594 * Populate EL3 state so that we've the right context 595 * before doing ERET 596 */ 597 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 598 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 599 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 600 601 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 602 mdcr_el3 = MDCR_EL3_RESET_VAL; 603 604 /* --------------------------------------------------------------------- 605 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 606 * Some fields are architecturally UNKNOWN on reset. 607 * 608 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 609 * Debug exceptions, other than Breakpoint Instruction exceptions, are 610 * disabled from all ELs in Secure state. 611 * 612 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 613 * privileged debug from S-EL1. 614 * 615 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 616 * access to the powerdown debug registers do not trap to EL3. 617 * 618 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 619 * debug registers, other than those registers that are controlled by 620 * MDCR_EL3.TDOSA. 621 */ 622 mdcr_el3 |= MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE); 623 mdcr_el3 &= ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT); 624 625 /* MDCR_EL3.EnSTEPOP: allow access to MDSTEPOP_EL1 */ 626 if (is_feat_step2_supported()) { 627 mdcr_el3 |= MDCR_EnSTEPOP_BIT; 628 } 629 630 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 631 632 #if IMAGE_BL31 633 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 634 if (is_feat_trf_supported()) { 635 trf_enable(ctx); 636 } 637 638 if (is_feat_tcr2_supported()) { 639 tcr2_enable(ctx); 640 } 641 642 pmuv3_enable(ctx); 643 644 if (is_feat_idte3_supported()) { 645 idte3_enable(ctx); 646 } 647 648 #if CTX_INCLUDE_EL2_REGS && IMAGE_BL31 649 /* 650 * Initialize SCTLR_EL2 context register with reset value. 651 */ 652 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 653 #endif /* CTX_INCLUDE_EL2_REGS */ 654 #endif /* IMAGE_BL31 */ 655 656 if (is_feat_morello_supported()) { 657 ctx->ddc_el0 = read_ddc_el0(); 658 } 659 660 /* 661 * Store the X0-X7 value from the entrypoint into the context 662 * Use memcpy as we are in control of the layout of the structures 663 */ 664 gp_regs = get_gpregs_ctx(ctx); 665 memcpy((void *)gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 666 } 667 668 /******************************************************************************* 669 * Context management library initialization routine. This library is used by 670 * runtime services to share pointers to 'cpu_context' structures for secure 671 * non-secure and realm states. Management of the structures and their associated 672 * memory is not done by the context management library e.g. the PSCI service 673 * manages the cpu context used for entry from and exit to the non-secure state. 674 * The Secure payload dispatcher service manages the context(s) corresponding to 675 * the secure state. It also uses this library to get access to the non-secure 676 * state cpu context pointers. 677 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 678 * which will be used for programming an entry into a lower EL. The same context 679 * will be used to save state upon exception entry from that EL. 680 ******************************************************************************/ 681 void __init cm_init(void) 682 { 683 /* 684 * The context management library has only global data to initialize, but 685 * that will be done when the BSS is zeroed out. 686 */ 687 } 688 689 /******************************************************************************* 690 * This is the high-level function used to initialize the cpu_context 'ctx' for 691 * first use. It performs initializations that are common to all security states 692 * and initializations specific to the security state specified in 'ep' 693 ******************************************************************************/ 694 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 695 { 696 size_t security_state; 697 698 assert(ctx != NULL); 699 700 /* 701 * Perform initializations that are common 702 * to all security states 703 */ 704 setup_context_common(ctx, ep); 705 706 security_state = GET_SECURITY_STATE(ep->h.attr); 707 708 /* Perform security state specific initializations */ 709 switch (security_state) { 710 case SECURE: 711 setup_secure_context(ctx, ep); 712 break; 713 #if ENABLE_RME && IMAGE_BL31 714 case REALM: 715 setup_realm_context(ctx, ep); 716 break; 717 #endif 718 case NON_SECURE: 719 setup_ns_context(ctx, ep); 720 break; 721 default: 722 ERROR("Invalid security state\n"); 723 panic(); 724 break; 725 } 726 } 727 728 /******************************************************************************* 729 * Enable architecture extensions for EL3 execution. This function only updates 730 * registers in-place which are expected to either never change or be 731 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 732 ******************************************************************************/ 733 void __no_pauth cm_manage_extensions_el3(unsigned int my_idx) 734 { 735 if (is_feat_pauth_supported()) { 736 pauth_init_enable_el3(); 737 } 738 739 #if IMAGE_BL31 740 if (is_feat_sve_supported()) { 741 sve_init_el3(); 742 } 743 744 if (is_feat_amu_supported()) { 745 amu_init_el3(my_idx); 746 } 747 748 if (is_feat_sme_supported()) { 749 sme_init_el3(); 750 } 751 752 if (is_feat_mpam_supported()) { 753 mpam_init_el3(); 754 } 755 756 if (is_feat_cpa2_supported()) { 757 cpa2_enable_el3(); 758 } 759 760 pmuv3_init_el3(); 761 762 /* NOTE: must be done last, makes the configuration immutable */ 763 if (is_feat_fgwte3_supported()) { 764 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL); 765 } 766 #endif /* IMAGE_BL31 */ 767 } 768 769 /****************************************************************************** 770 * Function to initialise the registers with the RESET values in the context 771 * memory, which are maintained per world. 772 ******************************************************************************/ 773 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 774 { 775 per_world_ctx->ctx_cptr_el3 = CPTR_EL3_RESET_VAL; 776 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 777 } 778 779 /******************************************************************************* 780 * Initialise per_world_context for Non-Secure world. 781 * This function enables the architecture extensions, which have same value 782 * across the cores for the non-secure world. 783 ******************************************************************************/ 784 static void manage_extensions_nonsecure_per_world(void) 785 { 786 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 787 788 #if IMAGE_BL31 789 if (is_feat_sme_supported()) { 790 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 791 } 792 793 if (is_feat_sve_supported()) { 794 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 795 } 796 797 if (is_feat_amu_supported()) { 798 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 799 } 800 801 if (is_feat_sys_reg_trace_supported()) { 802 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 803 } 804 805 if (is_feat_mpam_supported()) { 806 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 807 } 808 809 if (is_feat_idte3_supported()) { 810 idte3_init_cached_idregs_per_world(CPU_CONTEXT_NS); 811 } 812 #endif /* IMAGE_BL31 */ 813 } 814 815 /******************************************************************************* 816 * Initialise per_world_context for Secure world. 817 * This function enables the architecture extensions, which have same value 818 * across the cores for the secure world. 819 ******************************************************************************/ 820 static void manage_extensions_secure_per_world(void) 821 { 822 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 823 824 #if IMAGE_BL31 825 if (is_feat_sme_supported()) { 826 827 if (ENABLE_SME_FOR_SWD) { 828 /* 829 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 830 * SME, SVE, and FPU/SIMD context properly managed. 831 */ 832 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 833 } else { 834 /* 835 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 836 * world can safely use the associated registers. 837 */ 838 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 839 } 840 } 841 if (is_feat_sve_supported()) { 842 if (ENABLE_SVE_FOR_SWD) { 843 /* 844 * Enable SVE and FPU in secure context, SPM must ensure 845 * that the SVE and FPU register contexts are properly managed. 846 */ 847 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 848 } else { 849 /* 850 * Disable SVE and FPU in secure context so non-secure world 851 * can safely use them. 852 */ 853 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 854 } 855 } 856 857 /* NS can access this but Secure shouldn't */ 858 if (is_feat_sys_reg_trace_supported()) { 859 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 860 } 861 862 if (is_feat_idte3_supported()) { 863 idte3_init_cached_idregs_per_world(CPU_CONTEXT_SECURE); 864 } 865 #endif /* IMAGE_BL31 */ 866 } 867 868 static void manage_extensions_realm_per_world(void) 869 { 870 #if ENABLE_RME && IMAGE_BL31 871 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 872 873 if (is_feat_sve_supported()) { 874 /* 875 * Enable SVE and FPU in realm context when it is enabled for NS. 876 * Realm manager must ensure that the SVE and FPU register 877 * contexts are properly managed. 878 */ 879 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 880 } 881 882 /* NS can access this but Realm shouldn't */ 883 if (is_feat_sys_reg_trace_supported()) { 884 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 885 } 886 887 /* 888 * If SME/SME2 is supported and enabled for NS world, then disable trapping 889 * of SME instructions for Realm world. RMM will save/restore required 890 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 891 */ 892 if (is_feat_sme_supported()) { 893 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 894 } 895 896 /* 897 * If FEAT_MPAM is supported and enabled, then disable trapping access 898 * to the MPAM registers for Realm world. Instead, RMM will configure 899 * the access to be trapped by itself so it can inject undefined aborts 900 * back to the Realm. 901 */ 902 if (is_feat_mpam_supported()) { 903 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 904 } 905 906 if (is_feat_idte3_supported()) { 907 idte3_init_cached_idregs_per_world(CPU_CONTEXT_REALM); 908 } 909 #endif /* ENABLE_RME && IMAGE_BL31 */ 910 } 911 912 void cm_manage_extensions_per_world(void) 913 { 914 manage_extensions_nonsecure_per_world(); 915 manage_extensions_secure_per_world(); 916 manage_extensions_realm_per_world(); 917 } 918 919 void cm_init_percpu_once_regs(void) 920 { 921 #if IMAGE_BL31 922 if (is_feat_idte3_supported()) { 923 idte3_init_percpu_once_regs(CPU_CONTEXT_NS); 924 idte3_init_percpu_once_regs(CPU_CONTEXT_SECURE); 925 #if ENABLE_RME 926 idte3_init_percpu_once_regs(CPU_CONTEXT_REALM); 927 #endif /* ENABLE_RME */ 928 } 929 #endif /* IMAGE_BL31 */ 930 } 931 932 /******************************************************************************* 933 * Enable architecture extensions on first entry to Non-secure world. 934 ******************************************************************************/ 935 static void manage_extensions_nonsecure(cpu_context_t *ctx) 936 { 937 #if IMAGE_BL31 938 /* NOTE: registers are not context switched */ 939 if (is_feat_amu_supported()) { 940 amu_enable(ctx); 941 } 942 943 if (is_feat_sme_supported()) { 944 sme_enable(ctx); 945 } 946 947 if (is_feat_fgt2_supported()) { 948 fgt2_enable(ctx); 949 } 950 951 if (is_feat_debugv8p9_supported()) { 952 debugv8p9_extended_bp_wp_enable(ctx); 953 } 954 955 if (is_feat_spe_supported()) { 956 spe_enable_ns(ctx); 957 } 958 959 if (is_feat_trbe_supported()) { 960 if (check_if_trbe_disable_affected_core()) { 961 trbe_disable_ns(ctx); 962 } else { 963 trbe_enable_ns(ctx); 964 } 965 } 966 967 if (is_feat_brbe_supported()) { 968 brbe_enable(ctx); 969 } 970 #endif /* IMAGE_BL31 */ 971 } 972 973 #if INIT_UNUSED_NS_EL2 974 /******************************************************************************* 975 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 976 * world when EL2 is empty and unused. 977 ******************************************************************************/ 978 static void manage_extensions_nonsecure_el2_unused(void) 979 { 980 #if IMAGE_BL31 981 if (is_feat_spe_supported()) { 982 spe_init_el2_unused(); 983 } 984 985 if (is_feat_amu_supported()) { 986 amu_init_el2_unused(); 987 } 988 989 if (is_feat_mpam_supported()) { 990 mpam_init_el2_unused(); 991 } 992 993 if (is_feat_trbe_supported()) { 994 trbe_init_el2_unused(); 995 } 996 997 if (is_feat_sys_reg_trace_supported()) { 998 sys_reg_trace_init_el2_unused(); 999 } 1000 1001 if (is_feat_trf_supported()) { 1002 trf_init_el2_unused(); 1003 } 1004 1005 pmuv3_init_el2_unused(); 1006 1007 if (is_feat_sve_supported()) { 1008 sve_init_el2_unused(); 1009 } 1010 1011 if (is_feat_sme_supported()) { 1012 sme_init_el2_unused(); 1013 } 1014 1015 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 1016 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 1017 } 1018 1019 if (is_feat_pauth_supported()) { 1020 pauth_enable_el2(); 1021 } 1022 #endif /* IMAGE_BL31 */ 1023 } 1024 #endif /* INIT_UNUSED_NS_EL2 */ 1025 1026 /******************************************************************************* 1027 * Enable architecture extensions on first entry to Secure world. 1028 ******************************************************************************/ 1029 static void manage_extensions_secure(cpu_context_t *ctx) 1030 { 1031 #if IMAGE_BL31 1032 if (is_feat_sme_supported()) { 1033 if (ENABLE_SME_FOR_SWD) { 1034 /* 1035 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 1036 * must ensure SME, SVE, and FPU/SIMD context properly managed. 1037 */ 1038 sme_init_el3(); 1039 sme_enable(ctx); 1040 } else { 1041 /* 1042 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 1043 * world can safely use the associated registers. 1044 */ 1045 sme_disable(ctx); 1046 } 1047 } 1048 1049 if (is_feat_spe_supported()) { 1050 spe_disable_secure(ctx); 1051 } 1052 1053 if (is_feat_trbe_supported()) { 1054 trbe_disable_secure(ctx); 1055 } 1056 #endif /* IMAGE_BL31 */ 1057 } 1058 1059 /******************************************************************************* 1060 * The following function initializes the cpu_context for the current CPU 1061 * for first use, and sets the initial entrypoint state as specified by the 1062 * entry_point_info structure. 1063 ******************************************************************************/ 1064 void cm_init_my_context(const entry_point_info_t *ep) 1065 { 1066 cpu_context_t *ctx; 1067 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 1068 cm_setup_context(ctx, ep); 1069 } 1070 1071 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 1072 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 1073 { 1074 #if INIT_UNUSED_NS_EL2 1075 u_register_t hcr_el2 = HCR_RESET_VAL; 1076 u_register_t mdcr_el2; 1077 u_register_t scr_el3; 1078 1079 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1080 1081 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 1082 if ((scr_el3 & SCR_RW_BIT) != 0U) { 1083 hcr_el2 |= HCR_RW_BIT; 1084 } 1085 1086 write_hcr_el2(hcr_el2); 1087 1088 /* 1089 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1090 * All fields have architecturally UNKNOWN reset values. 1091 */ 1092 write_cptr_el2(CPTR_EL2_RESET_VAL); 1093 1094 /* 1095 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1096 * reset and are set to zero except for field(s) listed below. 1097 * 1098 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1099 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1100 * 1101 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1102 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1103 */ 1104 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1105 1106 /* 1107 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1108 * UNKNOWN value. 1109 */ 1110 write_cntvoff_el2(0); 1111 1112 /* 1113 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1114 * respectively. 1115 */ 1116 write_vpidr_el2(read_midr_el1()); 1117 write_vmpidr_el2(read_mpidr_el1()); 1118 1119 /* 1120 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1121 * 1122 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1123 * translation is disabled, cache maintenance operations depend on the 1124 * VMID. 1125 * 1126 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1127 * disabled. 1128 */ 1129 write_vttbr_el2(VTTBR_RESET_VAL & 1130 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1131 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1132 1133 /* 1134 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1135 * Some fields are architecturally UNKNOWN on reset. 1136 * 1137 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1138 * register accesses to the Debug ROM registers are not trapped to EL2. 1139 * 1140 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1141 * accesses to the powerdown debug registers are not trapped to EL2. 1142 * 1143 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1144 * debug registers do not trap to EL2. 1145 * 1146 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1147 * EL2. 1148 */ 1149 mdcr_el2 = MDCR_EL2_RESET_VAL & 1150 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1151 MDCR_EL2_TDE_BIT); 1152 1153 write_mdcr_el2(mdcr_el2); 1154 1155 /* 1156 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1157 * 1158 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1159 * EL1 accesses to System registers do not trap to EL2. 1160 */ 1161 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1162 1163 /* 1164 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1165 * reset. 1166 * 1167 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1168 * and prevent timer interrupts. 1169 */ 1170 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1171 1172 manage_extensions_nonsecure_el2_unused(); 1173 #endif /* INIT_UNUSED_NS_EL2 */ 1174 } 1175 1176 /******************************************************************************* 1177 * Prepare the CPU system registers for first entry into realm, secure, or 1178 * normal world. 1179 * 1180 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1181 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1182 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1183 * For all entries, the EL1 registers are initialized from the cpu_context 1184 ******************************************************************************/ 1185 void cm_prepare_el3_exit(size_t security_state) 1186 { 1187 u_register_t sctlr_el2, scr_el3; 1188 cpu_context_t *ctx = cm_get_context(security_state); 1189 1190 assert(ctx != NULL); 1191 1192 if (security_state == NON_SECURE) { 1193 uint64_t el2_implemented = el_implemented(2); 1194 1195 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1196 CTX_SCR_EL3); 1197 1198 if (el2_implemented != EL_IMPL_NONE) { 1199 1200 /* 1201 * If context is not being used for EL2, initialize 1202 * HCRX_EL2 with its init value here. 1203 */ 1204 if (is_feat_hcx_supported()) { 1205 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1206 } 1207 1208 /* 1209 * Initialize Fine-grained trap registers introduced 1210 * by FEAT_FGT so all traps are initially disabled when 1211 * switching to EL2 or a lower EL, preventing undesired 1212 * behavior. 1213 */ 1214 if (is_feat_fgt_supported()) { 1215 /* 1216 * Initialize HFG*_EL2 registers with a default 1217 * value so legacy systems unaware of FEAT_FGT 1218 * do not get trapped due to their lack of 1219 * initialization for this feature. 1220 */ 1221 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1222 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1223 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1224 } 1225 1226 /* Condition to ensure EL2 is being used. */ 1227 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1228 /* Initialize SCTLR_EL2 register with reset value. */ 1229 sctlr_el2 = SCTLR_EL2_RES1; 1230 1231 /* 1232 * If workaround of errata 764081 for Cortex-A75 1233 * is used then set SCTLR_EL2.IESB to enable 1234 * Implicit Error Synchronization Barrier. 1235 */ 1236 if (errata_a75_764081_applies()) { 1237 sctlr_el2 |= SCTLR_IESB_BIT; 1238 } 1239 1240 write_sctlr_el2(sctlr_el2); 1241 } else { 1242 /* 1243 * (scr_el3 & SCR_HCE_BIT==0) 1244 * EL2 implemented but unused. 1245 */ 1246 init_nonsecure_el2_unused(ctx); 1247 } 1248 } 1249 1250 if (is_feat_fgwte3_supported()) { 1251 /* 1252 * TCR_EL3 and ACTLR_EL3 could be overwritten 1253 * by platforms and hence is locked a bit late. 1254 */ 1255 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL); 1256 } 1257 } 1258 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1 1259 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1260 cm_el1_sysregs_context_restore(security_state); 1261 #endif 1262 cm_set_next_eret_context(security_state); 1263 } 1264 1265 /* Assumes prepare_el3_entry() has disabled counters 2 and 3 */ 1266 void cm_sysregs_context_save_amu(unsigned int security_state) 1267 { 1268 world_amu_regs_t *ctx = PER_CPU_CUR(world_amu_ctx[get_cpu_context_index(security_state)]); 1269 1270 ctx->amevcntr02_el0 = read_amevcntr02_el0(); 1271 ctx->amevcntr03_el0 = read_amevcntr03_el0(); 1272 } 1273 1274 void cm_sysregs_context_restore_amu(unsigned int security_state) 1275 { 1276 world_amu_regs_t *ctx = PER_CPU_CUR(world_amu_ctx[get_cpu_context_index(security_state)]); 1277 1278 write_amevcntr02_el0(ctx->amevcntr02_el0); 1279 write_amevcntr03_el0(ctx->amevcntr03_el0); 1280 } 1281 1282 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1283 1284 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1285 { 1286 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1287 if (is_feat_amu_supported()) { 1288 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1289 } 1290 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1291 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1292 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1293 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1294 } 1295 1296 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1297 { 1298 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1299 if (is_feat_amu_supported()) { 1300 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1301 } 1302 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1303 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1304 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1305 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1306 } 1307 1308 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1309 { 1310 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1311 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1312 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1313 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1314 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1315 } 1316 1317 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1318 { 1319 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1320 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1321 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1322 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1323 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1324 } 1325 1326 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1327 { 1328 u_register_t mpam_idr = read_mpamidr_el1(); 1329 1330 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1331 1332 /* 1333 * The context registers that we intend to save would be part of the 1334 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1335 */ 1336 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1337 return; 1338 } 1339 1340 /* 1341 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1342 * MPAMIDR_HAS_HCR_BIT == 1. 1343 */ 1344 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1345 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1346 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1347 1348 /* 1349 * The number of MPAMVPM registers is implementation defined, their 1350 * number is stored in the MPAMIDR_EL1 register. 1351 */ 1352 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1353 case 7: 1354 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1355 __fallthrough; 1356 case 6: 1357 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1358 __fallthrough; 1359 case 5: 1360 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1361 __fallthrough; 1362 case 4: 1363 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1364 __fallthrough; 1365 case 3: 1366 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1367 __fallthrough; 1368 case 2: 1369 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1370 __fallthrough; 1371 case 1: 1372 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1373 break; 1374 } 1375 } 1376 1377 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1378 { 1379 u_register_t mpam_idr = read_mpamidr_el1(); 1380 1381 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1382 1383 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1384 return; 1385 } 1386 1387 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1388 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1389 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1390 1391 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1392 case 7: 1393 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1394 __fallthrough; 1395 case 6: 1396 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1397 __fallthrough; 1398 case 5: 1399 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1400 __fallthrough; 1401 case 4: 1402 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1403 __fallthrough; 1404 case 3: 1405 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1406 __fallthrough; 1407 case 2: 1408 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1409 __fallthrough; 1410 case 1: 1411 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1412 break; 1413 } 1414 } 1415 1416 /* --------------------------------------------------------------------------- 1417 * The following registers are not added: 1418 * ICH_AP0R<n>_EL2 1419 * ICH_AP1R<n>_EL2 1420 * ICH_LR<n>_EL2 1421 * 1422 * NOTE: For a system with S-EL2 present but not enabled, accessing 1423 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1424 * SCR_EL3.NS = 1 before accessing this register. 1425 * --------------------------------------------------------------------------- 1426 */ 1427 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1428 { 1429 u_register_t scr_el3 = read_scr_el3(); 1430 1431 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1432 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1433 #else 1434 write_scr_el3(scr_el3 | SCR_NS_BIT); 1435 isb(); 1436 1437 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1438 1439 write_scr_el3(scr_el3); 1440 isb(); 1441 #endif 1442 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1443 1444 if (errata_ich_vmcr_el2_applies()) { 1445 if (security_state == SECURE) { 1446 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1447 } else { 1448 write_scr_el3(scr_el3 | SCR_NS_BIT); 1449 } 1450 isb(); 1451 } 1452 1453 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1454 1455 if (errata_ich_vmcr_el2_applies()) { 1456 write_scr_el3(scr_el3); 1457 isb(); 1458 } 1459 } 1460 1461 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1462 { 1463 u_register_t scr_el3 = read_scr_el3(); 1464 1465 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1466 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1467 #else 1468 write_scr_el3(scr_el3 | SCR_NS_BIT); 1469 isb(); 1470 1471 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1472 1473 write_scr_el3(scr_el3); 1474 isb(); 1475 #endif 1476 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1477 1478 if (errata_ich_vmcr_el2_applies()) { 1479 if (security_state == SECURE) { 1480 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1481 } else { 1482 write_scr_el3(scr_el3 | SCR_NS_BIT); 1483 } 1484 isb(); 1485 } 1486 1487 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1488 1489 if (errata_ich_vmcr_el2_applies()) { 1490 write_scr_el3(scr_el3); 1491 isb(); 1492 } 1493 } 1494 1495 /* ----------------------------------------------------- 1496 * The following registers are not added: 1497 * AMEVCNTVOFF0<n>_EL2 1498 * AMEVCNTVOFF1<n>_EL2 1499 * ----------------------------------------------------- 1500 */ 1501 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1502 { 1503 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1504 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1505 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1506 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1507 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1508 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1509 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1510 if (CTX_INCLUDE_AARCH32_REGS) { 1511 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1512 } 1513 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1514 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1515 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1516 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1517 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1518 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1519 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1520 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1521 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1522 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1523 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1524 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1525 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1526 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1527 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1528 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1529 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1530 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1531 1532 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1533 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1534 } 1535 1536 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1537 { 1538 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1539 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1540 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1541 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1542 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1543 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1544 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1545 if (CTX_INCLUDE_AARCH32_REGS) { 1546 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1547 } 1548 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1549 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1550 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1551 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1552 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1553 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1554 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1555 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1556 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1557 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1558 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1559 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1560 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1561 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1562 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1563 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1564 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1565 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1566 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1567 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1568 } 1569 1570 /******************************************************************************* 1571 * Save EL2 sysreg context 1572 ******************************************************************************/ 1573 void cm_el2_sysregs_context_save(uint32_t security_state) 1574 { 1575 cpu_context_t *ctx; 1576 el2_sysregs_t *el2_sysregs_ctx; 1577 1578 ctx = cm_get_context(security_state); 1579 assert(ctx != NULL); 1580 1581 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1582 1583 el2_sysregs_context_save_common(el2_sysregs_ctx); 1584 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1585 1586 if (is_feat_mte2_supported()) { 1587 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1588 } 1589 1590 if (is_feat_mpam_supported()) { 1591 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1592 } 1593 1594 if (is_feat_fgt_supported()) { 1595 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1596 } 1597 1598 if (is_feat_fgt2_supported()) { 1599 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1600 } 1601 1602 if (is_feat_ecv_v2_supported()) { 1603 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1604 } 1605 1606 if (is_feat_vhe_supported()) { 1607 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1608 read_contextidr_el2()); 1609 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1610 } 1611 1612 if (is_feat_ras_supported()) { 1613 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1614 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1615 } 1616 1617 if (is_feat_nv2_supported()) { 1618 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1619 } 1620 1621 if (is_feat_trf_supported()) { 1622 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1623 } 1624 1625 if (is_feat_csv2_2_supported()) { 1626 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1627 read_scxtnum_el2()); 1628 } 1629 1630 if (is_feat_hcx_supported()) { 1631 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1632 } 1633 1634 if (is_feat_tcr2_supported()) { 1635 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1636 } 1637 1638 if (is_feat_s1pie_supported()) { 1639 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1640 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1641 } 1642 1643 if (is_feat_s1poe_supported()) { 1644 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1645 } 1646 1647 if (is_feat_brbe_supported()) { 1648 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1649 } 1650 1651 if (is_feat_s2pie_supported()) { 1652 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1653 } 1654 1655 if (is_feat_gcs_supported()) { 1656 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1657 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1658 } 1659 1660 if (is_feat_sctlr2_supported()) { 1661 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1662 } 1663 1664 if (is_feat_amu_supported()) { 1665 cm_sysregs_context_save_amu(security_state); 1666 } 1667 } 1668 1669 /******************************************************************************* 1670 * Restore EL2 sysreg context 1671 ******************************************************************************/ 1672 void cm_el2_sysregs_context_restore(uint32_t security_state) 1673 { 1674 cpu_context_t *ctx; 1675 el2_sysregs_t *el2_sysregs_ctx; 1676 1677 ctx = cm_get_context(security_state); 1678 assert(ctx != NULL); 1679 1680 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1681 1682 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1683 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1684 1685 if (is_feat_mte2_supported()) { 1686 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1687 } 1688 1689 if (is_feat_mpam_supported()) { 1690 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1691 } 1692 1693 if (is_feat_fgt_supported()) { 1694 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1695 } 1696 1697 if (is_feat_fgt2_supported()) { 1698 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1699 } 1700 1701 if (is_feat_ecv_v2_supported()) { 1702 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1703 } 1704 1705 if (is_feat_vhe_supported()) { 1706 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1707 contextidr_el2)); 1708 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1709 } 1710 1711 if (is_feat_ras_supported()) { 1712 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1713 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1714 } 1715 1716 if (is_feat_nv2_supported()) { 1717 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1718 } 1719 1720 if (is_feat_trf_supported()) { 1721 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1722 } 1723 1724 if (is_feat_csv2_2_supported()) { 1725 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1726 scxtnum_el2)); 1727 } 1728 1729 if (is_feat_hcx_supported()) { 1730 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1731 } 1732 1733 if (is_feat_tcr2_supported()) { 1734 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1735 } 1736 1737 if (is_feat_s1pie_supported()) { 1738 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1739 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1740 } 1741 1742 if (is_feat_s1poe_supported()) { 1743 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1744 } 1745 1746 if (is_feat_s2pie_supported()) { 1747 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1748 } 1749 1750 if (is_feat_gcs_supported()) { 1751 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1752 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1753 } 1754 1755 if (is_feat_sctlr2_supported()) { 1756 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1757 } 1758 1759 if (is_feat_brbe_supported()) { 1760 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1761 } 1762 1763 if (is_feat_amu_supported()) { 1764 cm_sysregs_context_restore_amu(security_state); 1765 } 1766 } 1767 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1768 1769 /******************************************************************************* 1770 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1771 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1772 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1773 * cm_prepare_el3_exit function. 1774 ******************************************************************************/ 1775 void cm_prepare_el3_exit_ns(void) 1776 { 1777 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1778 #if ENABLE_ASSERTIONS 1779 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1780 assert(ctx != NULL); 1781 1782 /* Assert that EL2 is used. */ 1783 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1784 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1785 (el_implemented(2U) != EL_IMPL_NONE)); 1786 #endif /* ENABLE_ASSERTIONS */ 1787 1788 /* Restore EL2 sysreg contexts */ 1789 cm_el2_sysregs_context_restore(NON_SECURE); 1790 cm_set_next_eret_context(NON_SECURE); 1791 #else 1792 cm_prepare_el3_exit(NON_SECURE); 1793 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1794 1795 if (is_feat_amu_supported()) { 1796 cm_sysregs_context_restore_amu(NON_SECURE); 1797 } 1798 } 1799 1800 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1801 /******************************************************************************* 1802 * The next set of six functions are used by runtime services to save and restore 1803 * EL1 context on the 'cpu_context' structure for the specified security state. 1804 ******************************************************************************/ 1805 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1806 { 1807 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1808 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1809 1810 #if (!ERRATA_SPECULATIVE_AT) 1811 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1812 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1813 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1814 1815 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1816 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1817 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1818 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1819 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1820 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1821 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1822 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1823 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1824 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1825 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1826 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1827 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1828 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1829 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1830 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1831 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1832 1833 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1834 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1835 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1836 1837 if (CTX_INCLUDE_AARCH32_REGS) { 1838 /* Save Aarch32 registers */ 1839 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1840 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1841 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1842 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1843 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1844 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1845 } 1846 1847 /* Save counter-timer kernel control register */ 1848 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1849 #if NS_TIMER_SWITCH 1850 /* Save NS Timer registers */ 1851 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1852 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1853 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1854 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1855 #endif 1856 1857 if (is_feat_mte2_supported()) { 1858 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1859 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1860 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1861 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1862 } 1863 1864 if (is_feat_ras_supported()) { 1865 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1866 } 1867 1868 if (is_feat_s1pie_supported()) { 1869 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1870 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1871 } 1872 1873 if (is_feat_s1poe_supported()) { 1874 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1875 } 1876 1877 if (is_feat_s2poe_supported()) { 1878 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1879 } 1880 1881 if (is_feat_tcr2_supported()) { 1882 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1883 } 1884 1885 if (is_feat_trf_supported()) { 1886 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1887 } 1888 1889 if (is_feat_csv2_2_supported()) { 1890 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1891 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1892 } 1893 1894 if (is_feat_gcs_supported()) { 1895 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1896 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1897 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1898 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1899 } 1900 1901 if (is_feat_the_supported()) { 1902 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1903 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1904 } 1905 1906 if (is_feat_sctlr2_supported()) { 1907 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1908 } 1909 1910 if (is_feat_ls64_accdata_supported()) { 1911 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1912 } 1913 1914 if (is_feat_step2_supported()) { 1915 write_el1_ctx_step2(ctx, mdstepop_el1, read_mdstepop_el1()); 1916 } 1917 } 1918 1919 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1920 { 1921 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1922 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1923 1924 #if (!ERRATA_SPECULATIVE_AT) 1925 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1926 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1927 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1928 1929 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1930 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1931 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1932 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1933 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1934 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1935 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1936 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1937 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1938 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1939 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1940 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1941 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1942 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1943 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1944 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1945 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1946 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1947 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1948 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1949 1950 if (CTX_INCLUDE_AARCH32_REGS) { 1951 /* Restore Aarch32 registers */ 1952 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1953 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1954 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1955 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1956 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1957 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1958 } 1959 1960 /* Restore counter-timer kernel control register */ 1961 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1962 #if NS_TIMER_SWITCH 1963 /* Restore NS Timer registers */ 1964 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1965 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1966 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1967 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1968 #endif 1969 1970 if (is_feat_mte2_supported()) { 1971 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1972 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1973 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1974 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1975 } 1976 1977 if (is_feat_ras_supported()) { 1978 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1979 } 1980 1981 if (is_feat_s1pie_supported()) { 1982 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1983 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1984 } 1985 1986 if (is_feat_s1poe_supported()) { 1987 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1988 } 1989 1990 if (is_feat_s2poe_supported()) { 1991 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1992 } 1993 1994 if (is_feat_tcr2_supported()) { 1995 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1996 } 1997 1998 if (is_feat_trf_supported()) { 1999 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 2000 } 2001 2002 if (is_feat_csv2_2_supported()) { 2003 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 2004 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 2005 } 2006 2007 if (is_feat_gcs_supported()) { 2008 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 2009 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 2010 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 2011 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 2012 } 2013 2014 if (is_feat_the_supported()) { 2015 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 2016 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 2017 } 2018 2019 if (is_feat_sctlr2_supported()) { 2020 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 2021 } 2022 2023 if (is_feat_ls64_accdata_supported()) { 2024 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 2025 } 2026 2027 if (is_feat_step2_supported()) { 2028 write_mdstepop_el1(read_el1_ctx_step2(ctx, mdstepop_el1)); 2029 } 2030 } 2031 2032 /******************************************************************************* 2033 * The next couple of functions are used by runtime services to save and restore 2034 * EL1 context on the 'cpu_context' structure for the specified security state. 2035 ******************************************************************************/ 2036 void cm_el1_sysregs_context_save(uint32_t security_state) 2037 { 2038 cpu_context_t *ctx; 2039 2040 ctx = cm_get_context(security_state); 2041 assert(ctx != NULL); 2042 2043 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 2044 2045 #if IMAGE_BL31 2046 if (is_feat_amu_supported()) { 2047 cm_sysregs_context_save_amu(security_state); 2048 } 2049 2050 if (security_state == SECURE) { 2051 PUBLISH_EVENT(cm_exited_secure_world); 2052 } else { 2053 PUBLISH_EVENT(cm_exited_normal_world); 2054 } 2055 #endif 2056 } 2057 2058 void cm_el1_sysregs_context_restore(uint32_t security_state) 2059 { 2060 cpu_context_t *ctx; 2061 2062 ctx = cm_get_context(security_state); 2063 assert(ctx != NULL); 2064 2065 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 2066 2067 #if IMAGE_BL31 2068 if (is_feat_amu_supported()) { 2069 cm_sysregs_context_restore_amu(security_state); 2070 } 2071 2072 if (security_state == SECURE) { 2073 PUBLISH_EVENT(cm_entering_secure_world); 2074 } else { 2075 PUBLISH_EVENT(cm_entering_normal_world); 2076 } 2077 #endif 2078 } 2079 2080 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 2081 2082 /******************************************************************************* 2083 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 2084 * given security state with the given entrypoint 2085 ******************************************************************************/ 2086 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 2087 { 2088 cpu_context_t *ctx; 2089 el3_state_t *state; 2090 2091 ctx = cm_get_context(security_state); 2092 assert(ctx != NULL); 2093 2094 /* Populate EL3 state so that ERET jumps to the correct entry */ 2095 state = get_el3state_ctx(ctx); 2096 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2097 } 2098 2099 /******************************************************************************* 2100 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 2101 * pertaining to the given security state 2102 ******************************************************************************/ 2103 void cm_set_elr_spsr_el3(uint32_t security_state, 2104 uintptr_t entrypoint, uint32_t spsr) 2105 { 2106 cpu_context_t *ctx; 2107 el3_state_t *state; 2108 2109 ctx = cm_get_context(security_state); 2110 assert(ctx != NULL); 2111 2112 /* Populate EL3 state so that ERET jumps to the correct entry */ 2113 state = get_el3state_ctx(ctx); 2114 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2115 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2116 } 2117 2118 /******************************************************************************* 2119 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2120 * pertaining to the given security state using the value and bit position 2121 * specified in the parameters. It preserves all other bits. 2122 ******************************************************************************/ 2123 void cm_write_scr_el3_bit(uint32_t security_state, 2124 uint32_t bit_pos, 2125 uint32_t value) 2126 { 2127 cpu_context_t *ctx; 2128 el3_state_t *state; 2129 u_register_t scr_el3; 2130 2131 ctx = cm_get_context(security_state); 2132 assert(ctx != NULL); 2133 2134 /* Ensure that the bit position is a valid one */ 2135 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2136 2137 /* Ensure that the 'value' is only a bit wide */ 2138 assert(value <= 1U); 2139 2140 /* 2141 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2142 * and set it to its new value. 2143 */ 2144 state = get_el3state_ctx(ctx); 2145 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2146 scr_el3 &= ~(1UL << bit_pos); 2147 scr_el3 |= (u_register_t)value << bit_pos; 2148 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2149 } 2150 2151 /******************************************************************************* 2152 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2153 * given security state. 2154 ******************************************************************************/ 2155 u_register_t cm_get_scr_el3(uint32_t security_state) 2156 { 2157 const cpu_context_t *ctx; 2158 const el3_state_t *state; 2159 2160 ctx = cm_get_context(security_state); 2161 assert(ctx != NULL); 2162 2163 /* Populate EL3 state so that ERET jumps to the correct entry */ 2164 state = get_el3state_ctx(ctx); 2165 return read_ctx_reg(state, CTX_SCR_EL3); 2166 } 2167 2168 /******************************************************************************* 2169 * This function is used to program the context that's used for exception 2170 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2171 * the required security state 2172 ******************************************************************************/ 2173 void cm_set_next_eret_context(uint32_t security_state) 2174 { 2175 cpu_context_t *ctx; 2176 2177 ctx = cm_get_context(security_state); 2178 assert(ctx != NULL); 2179 2180 cm_set_next_context(ctx); 2181 } 2182