1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/cpu_data.h> 24 #include <lib/el3_runtime/pubsub_events.h> 25 #include <lib/extensions/amu.h> 26 #include <lib/extensions/brbe.h> 27 #include <lib/extensions/mpam.h> 28 #include <lib/extensions/pmuv3.h> 29 #include <lib/extensions/sme.h> 30 #include <lib/extensions/spe.h> 31 #include <lib/extensions/sve.h> 32 #include <lib/extensions/sys_reg_trace.h> 33 #include <lib/extensions/trbe.h> 34 #include <lib/extensions/trf.h> 35 #include <lib/utils.h> 36 37 #if ENABLE_FEAT_TWED 38 /* Make sure delay value fits within the range(0-15) */ 39 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 40 #endif /* ENABLE_FEAT_TWED */ 41 42 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 43 static bool has_secure_perworld_init; 44 45 static void manage_extensions_nonsecure(cpu_context_t *ctx); 46 static void manage_extensions_secure(cpu_context_t *ctx); 47 static void manage_extensions_secure_per_world(void); 48 49 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 50 { 51 u_register_t sctlr_elx, actlr_elx; 52 53 /* 54 * Initialise SCTLR_EL1 to the reset value corresponding to the target 55 * execution state setting all fields rather than relying on the hw. 56 * Some fields have architecturally UNKNOWN reset values and these are 57 * set to zero. 58 * 59 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 60 * 61 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 62 * required by PSCI specification) 63 */ 64 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 65 if (GET_RW(ep->spsr) == MODE_RW_64) { 66 sctlr_elx |= SCTLR_EL1_RES1; 67 } else { 68 /* 69 * If the target execution state is AArch32 then the following 70 * fields need to be set. 71 * 72 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 73 * instructions are not trapped to EL1. 74 * 75 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 76 * instructions are not trapped to EL1. 77 * 78 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 79 * CP15DMB, CP15DSB, and CP15ISB instructions. 80 */ 81 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 82 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 83 } 84 85 #if ERRATA_A75_764081 86 /* 87 * If workaround of errata 764081 for Cortex-A75 is used then set 88 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 89 */ 90 sctlr_elx |= SCTLR_IESB_BIT; 91 #endif 92 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 93 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 94 95 /* 96 * Base the context ACTLR_EL1 on the current value, as it is 97 * implementation defined. The context restore process will write 98 * the value from the context to the actual register and can cause 99 * problems for processor cores that don't expect certain bits to 100 * be zero. 101 */ 102 actlr_elx = read_actlr_el1(); 103 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 104 } 105 106 /****************************************************************************** 107 * This function performs initializations that are specific to SECURE state 108 * and updates the cpu context specified by 'ctx'. 109 *****************************************************************************/ 110 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 111 { 112 u_register_t scr_el3; 113 el3_state_t *state; 114 115 state = get_el3state_ctx(ctx); 116 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 117 118 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 119 /* 120 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 121 * indicated by the interrupt routing model for BL31. 122 */ 123 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 124 #endif 125 126 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 127 if (is_feat_mte2_supported()) { 128 scr_el3 |= SCR_ATA_BIT; 129 } 130 131 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 132 133 /* 134 * Initialize EL1 context registers unless SPMC is running 135 * at S-EL2. 136 */ 137 #if !SPMD_SPM_AT_SEL2 138 setup_el1_context(ctx, ep); 139 #endif 140 141 manage_extensions_secure(ctx); 142 143 /** 144 * manage_extensions_secure_per_world api has to be executed once, 145 * as the registers getting initialised, maintain constant value across 146 * all the cpus for the secure world. 147 * Henceforth, this check ensures that the registers are initialised once 148 * and avoids re-initialization from multiple cores. 149 */ 150 if (!has_secure_perworld_init) { 151 manage_extensions_secure_per_world(); 152 } 153 154 } 155 156 #if ENABLE_RME 157 /****************************************************************************** 158 * This function performs initializations that are specific to REALM state 159 * and updates the cpu context specified by 'ctx'. 160 *****************************************************************************/ 161 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 162 { 163 u_register_t scr_el3; 164 el3_state_t *state; 165 166 state = get_el3state_ctx(ctx); 167 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 168 169 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 170 171 /* CSV2 version 2 and above */ 172 if (is_feat_csv2_2_supported()) { 173 /* Enable access to the SCXTNUM_ELx registers. */ 174 scr_el3 |= SCR_EnSCXT_BIT; 175 } 176 177 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 178 } 179 #endif /* ENABLE_RME */ 180 181 /****************************************************************************** 182 * This function performs initializations that are specific to NON-SECURE state 183 * and updates the cpu context specified by 'ctx'. 184 *****************************************************************************/ 185 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 186 { 187 u_register_t scr_el3; 188 el3_state_t *state; 189 190 state = get_el3state_ctx(ctx); 191 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 192 193 /* SCR_NS: Set the NS bit */ 194 scr_el3 |= SCR_NS_BIT; 195 196 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 197 if (is_feat_mte2_supported()) { 198 scr_el3 |= SCR_ATA_BIT; 199 } 200 201 #if !CTX_INCLUDE_PAUTH_REGS 202 /* 203 * Pointer Authentication feature, if present, is always enabled by default 204 * for Non secure lower exception levels. We do not have an explicit 205 * flag to set it. 206 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 207 * exception levels of secure and realm worlds. 208 * 209 * To prevent the leakage between the worlds during world switch, 210 * we enable it only for the non-secure world. 211 * 212 * If the Secure/realm world wants to use pointer authentication, 213 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 214 * it will be enabled globally for all the contexts. 215 * 216 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 217 * other than EL3 218 * 219 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 220 * than EL3 221 */ 222 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 223 224 #endif /* CTX_INCLUDE_PAUTH_REGS */ 225 226 #if HANDLE_EA_EL3_FIRST_NS 227 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 228 scr_el3 |= SCR_EA_BIT; 229 #endif 230 231 #if RAS_TRAP_NS_ERR_REC_ACCESS 232 /* 233 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 234 * and RAS ERX registers from EL1 and EL2(from any security state) 235 * are trapped to EL3. 236 * Set here to trap only for NS EL1/EL2 237 * 238 */ 239 scr_el3 |= SCR_TERR_BIT; 240 #endif 241 242 /* CSV2 version 2 and above */ 243 if (is_feat_csv2_2_supported()) { 244 /* Enable access to the SCXTNUM_ELx registers. */ 245 scr_el3 |= SCR_EnSCXT_BIT; 246 } 247 248 #ifdef IMAGE_BL31 249 /* 250 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 251 * indicated by the interrupt routing model for BL31. 252 */ 253 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 254 #endif 255 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 256 257 /* Initialize EL1 context registers */ 258 setup_el1_context(ctx, ep); 259 260 /* Initialize EL2 context registers */ 261 #if CTX_INCLUDE_EL2_REGS 262 263 /* 264 * Initialize SCTLR_EL2 context register with reset value. 265 */ 266 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 267 268 if (is_feat_hcx_supported()) { 269 /* 270 * Initialize register HCRX_EL2 with its init value. 271 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 272 * chance that this can lead to unexpected behavior in lower 273 * ELs that have not been updated since the introduction of 274 * this feature if not properly initialized, especially when 275 * it comes to those bits that enable/disable traps. 276 */ 277 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 278 HCRX_EL2_INIT_VAL); 279 } 280 281 if (is_feat_fgt_supported()) { 282 /* 283 * Initialize HFG*_EL2 registers with a default value so legacy 284 * systems unaware of FEAT_FGT do not get trapped due to their lack 285 * of initialization for this feature. 286 */ 287 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 288 HFGITR_EL2_INIT_VAL); 289 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 290 HFGRTR_EL2_INIT_VAL); 291 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 292 HFGWTR_EL2_INIT_VAL); 293 } 294 295 #endif /* CTX_INCLUDE_EL2_REGS */ 296 297 manage_extensions_nonsecure(ctx); 298 } 299 300 /******************************************************************************* 301 * The following function performs initialization of the cpu_context 'ctx' 302 * for first use that is common to all security states, and sets the 303 * initial entrypoint state as specified by the entry_point_info structure. 304 * 305 * The EE and ST attributes are used to configure the endianness and secure 306 * timer availability for the new execution context. 307 ******************************************************************************/ 308 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 309 { 310 u_register_t scr_el3; 311 el3_state_t *state; 312 gp_regs_t *gp_regs; 313 314 state = get_el3state_ctx(ctx); 315 316 /* Clear any residual register values from the context */ 317 zeromem(ctx, sizeof(*ctx)); 318 319 /* 320 * The lower-EL context is zeroed so that no stale values leak to a world. 321 * It is assumed that an all-zero lower-EL context is good enough for it 322 * to boot correctly. However, there are very few registers where this 323 * is not true and some values need to be recreated. 324 */ 325 #if CTX_INCLUDE_EL2_REGS 326 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 327 328 /* 329 * These bits are set in the gicv3 driver. Losing them (especially the 330 * SRE bit) is problematic for all worlds. Henceforth recreate them. 331 */ 332 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 333 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 334 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 335 #endif /* CTX_INCLUDE_EL2_REGS */ 336 337 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 338 scr_el3 = SCR_RESET_VAL; 339 340 /* 341 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 342 * EL2, EL1 and EL0 are not trapped to EL3. 343 * 344 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 345 * EL2, EL1 and EL0 are not trapped to EL3. 346 * 347 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 348 * both Security states and both Execution states. 349 * 350 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 351 * Non-secure memory. 352 */ 353 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 354 355 scr_el3 |= SCR_SIF_BIT; 356 357 /* 358 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 359 * Exception level as specified by SPSR. 360 */ 361 if (GET_RW(ep->spsr) == MODE_RW_64) { 362 scr_el3 |= SCR_RW_BIT; 363 } 364 365 /* 366 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 367 * Secure timer registers to EL3, from AArch64 state only, if specified 368 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 369 * bit always behaves as 1 (i.e. secure physical timer register access 370 * is not trapped) 371 */ 372 if (EP_GET_ST(ep->h.attr) != 0U) { 373 scr_el3 |= SCR_ST_BIT; 374 } 375 376 /* 377 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 378 * SCR_EL3.HXEn. 379 */ 380 if (is_feat_hcx_supported()) { 381 scr_el3 |= SCR_HXEn_BIT; 382 } 383 384 /* 385 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 386 * registers are trapped to EL3. 387 */ 388 #if ENABLE_FEAT_RNG_TRAP 389 scr_el3 |= SCR_TRNDR_BIT; 390 #endif 391 392 #if FAULT_INJECTION_SUPPORT 393 /* Enable fault injection from lower ELs */ 394 scr_el3 |= SCR_FIEN_BIT; 395 #endif 396 397 #if CTX_INCLUDE_PAUTH_REGS 398 /* 399 * Enable Pointer Authentication globally for all the worlds. 400 * 401 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 402 * other than EL3 403 * 404 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 405 * than EL3 406 */ 407 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 408 #endif /* CTX_INCLUDE_PAUTH_REGS */ 409 410 /* 411 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 412 */ 413 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 414 scr_el3 |= SCR_TCR2EN_BIT; 415 } 416 417 /* 418 * SCR_EL3.PIEN: Enable permission indirection and overlay 419 * registers for AArch64 if present. 420 */ 421 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 422 scr_el3 |= SCR_PIEN_BIT; 423 } 424 425 /* 426 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 427 */ 428 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 429 scr_el3 |= SCR_GCSEn_BIT; 430 } 431 432 /* 433 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 434 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 435 * next mode is Hyp. 436 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 437 * same conditions as HVC instructions and when the processor supports 438 * ARMv8.6-FGT. 439 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 440 * CNTPOFF_EL2 register under the same conditions as HVC instructions 441 * and when the processor supports ECV. 442 */ 443 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 444 || ((GET_RW(ep->spsr) != MODE_RW_64) 445 && (GET_M32(ep->spsr) == MODE32_hyp))) { 446 scr_el3 |= SCR_HCE_BIT; 447 448 if (is_feat_fgt_supported()) { 449 scr_el3 |= SCR_FGTEN_BIT; 450 } 451 452 if (is_feat_ecv_supported()) { 453 scr_el3 |= SCR_ECVEN_BIT; 454 } 455 } 456 457 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 458 if (is_feat_twed_supported()) { 459 /* Set delay in SCR_EL3 */ 460 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 461 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 462 << SCR_TWEDEL_SHIFT); 463 464 /* Enable WFE delay */ 465 scr_el3 |= SCR_TWEDEn_BIT; 466 } 467 468 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 469 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 470 if (is_feat_sel2_supported()) { 471 scr_el3 |= SCR_EEL2_BIT; 472 } 473 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 474 475 /* 476 * Populate EL3 state so that we've the right context 477 * before doing ERET 478 */ 479 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 480 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 481 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 482 483 /* 484 * Store the X0-X7 value from the entrypoint into the context 485 * Use memcpy as we are in control of the layout of the structures 486 */ 487 gp_regs = get_gpregs_ctx(ctx); 488 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 489 } 490 491 /******************************************************************************* 492 * Context management library initialization routine. This library is used by 493 * runtime services to share pointers to 'cpu_context' structures for secure 494 * non-secure and realm states. Management of the structures and their associated 495 * memory is not done by the context management library e.g. the PSCI service 496 * manages the cpu context used for entry from and exit to the non-secure state. 497 * The Secure payload dispatcher service manages the context(s) corresponding to 498 * the secure state. It also uses this library to get access to the non-secure 499 * state cpu context pointers. 500 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 501 * which will be used for programming an entry into a lower EL. The same context 502 * will be used to save state upon exception entry from that EL. 503 ******************************************************************************/ 504 void __init cm_init(void) 505 { 506 /* 507 * The context management library has only global data to initialize, but 508 * that will be done when the BSS is zeroed out. 509 */ 510 } 511 512 /******************************************************************************* 513 * This is the high-level function used to initialize the cpu_context 'ctx' for 514 * first use. It performs initializations that are common to all security states 515 * and initializations specific to the security state specified in 'ep' 516 ******************************************************************************/ 517 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 518 { 519 unsigned int security_state; 520 521 assert(ctx != NULL); 522 523 /* 524 * Perform initializations that are common 525 * to all security states 526 */ 527 setup_context_common(ctx, ep); 528 529 security_state = GET_SECURITY_STATE(ep->h.attr); 530 531 /* Perform security state specific initializations */ 532 switch (security_state) { 533 case SECURE: 534 setup_secure_context(ctx, ep); 535 break; 536 #if ENABLE_RME 537 case REALM: 538 setup_realm_context(ctx, ep); 539 break; 540 #endif 541 case NON_SECURE: 542 setup_ns_context(ctx, ep); 543 break; 544 default: 545 ERROR("Invalid security state\n"); 546 panic(); 547 break; 548 } 549 } 550 551 /******************************************************************************* 552 * Enable architecture extensions for EL3 execution. This function only updates 553 * registers in-place which are expected to either never change or be 554 * overwritten by el3_exit. 555 ******************************************************************************/ 556 #if IMAGE_BL31 557 void cm_manage_extensions_el3(void) 558 { 559 if (is_feat_spe_supported()) { 560 spe_init_el3(); 561 } 562 563 if (is_feat_amu_supported()) { 564 amu_init_el3(); 565 } 566 567 if (is_feat_sme_supported()) { 568 sme_init_el3(); 569 } 570 571 if (is_feat_trbe_supported()) { 572 trbe_init_el3(); 573 } 574 575 if (is_feat_brbe_supported()) { 576 brbe_init_el3(); 577 } 578 579 if (is_feat_trf_supported()) { 580 trf_init_el3(); 581 } 582 583 pmuv3_init_el3(); 584 } 585 #endif /* IMAGE_BL31 */ 586 587 /****************************************************************************** 588 * Function to initialise the registers with the RESET values in the context 589 * memory, which are maintained per world. 590 ******************************************************************************/ 591 #if IMAGE_BL31 592 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 593 { 594 /* 595 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 596 * 597 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 598 * by Advanced SIMD, floating-point or SVE instructions (if 599 * implemented) do not trap to EL3. 600 * 601 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 602 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 603 */ 604 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 605 606 per_world_ctx->ctx_cptr_el3 = cptr_el3; 607 608 /* 609 * Initialize MPAM3_EL3 to its default reset value 610 * 611 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 612 * all lower ELn MPAM3_EL3 register access to, trap to EL3 613 */ 614 615 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 616 } 617 #endif /* IMAGE_BL31 */ 618 619 /******************************************************************************* 620 * Initialise per_world_context for Non-Secure world. 621 * This function enables the architecture extensions, which have same value 622 * across the cores for the non-secure world. 623 ******************************************************************************/ 624 #if IMAGE_BL31 625 void manage_extensions_nonsecure_per_world(void) 626 { 627 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 628 629 if (is_feat_sme_supported()) { 630 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 631 } 632 633 if (is_feat_sve_supported()) { 634 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 635 } 636 637 if (is_feat_amu_supported()) { 638 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 639 } 640 641 if (is_feat_sys_reg_trace_supported()) { 642 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 643 } 644 645 if (is_feat_mpam_supported()) { 646 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 647 } 648 } 649 #endif /* IMAGE_BL31 */ 650 651 /******************************************************************************* 652 * Initialise per_world_context for Secure world. 653 * This function enables the architecture extensions, which have same value 654 * across the cores for the secure world. 655 ******************************************************************************/ 656 static void manage_extensions_secure_per_world(void) 657 { 658 #if IMAGE_BL31 659 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 660 661 if (is_feat_sme_supported()) { 662 663 if (ENABLE_SME_FOR_SWD) { 664 /* 665 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 666 * SME, SVE, and FPU/SIMD context properly managed. 667 */ 668 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 669 } else { 670 /* 671 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 672 * world can safely use the associated registers. 673 */ 674 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 675 } 676 } 677 if (is_feat_sve_supported()) { 678 if (ENABLE_SVE_FOR_SWD) { 679 /* 680 * Enable SVE and FPU in secure context, SPM must ensure 681 * that the SVE and FPU register contexts are properly managed. 682 */ 683 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 684 } else { 685 /* 686 * Disable SVE and FPU in secure context so non-secure world 687 * can safely use them. 688 */ 689 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 690 } 691 } 692 693 /* NS can access this but Secure shouldn't */ 694 if (is_feat_sys_reg_trace_supported()) { 695 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 696 } 697 698 has_secure_perworld_init = true; 699 #endif /* IMAGE_BL31 */ 700 } 701 702 /******************************************************************************* 703 * Enable architecture extensions on first entry to Non-secure world. 704 ******************************************************************************/ 705 static void manage_extensions_nonsecure(cpu_context_t *ctx) 706 { 707 #if IMAGE_BL31 708 if (is_feat_amu_supported()) { 709 amu_enable(ctx); 710 } 711 712 if (is_feat_sme_supported()) { 713 sme_enable(ctx); 714 } 715 716 pmuv3_enable(ctx); 717 #endif /* IMAGE_BL31 */ 718 } 719 720 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 721 static __unused void enable_pauth_el2(void) 722 { 723 u_register_t hcr_el2 = read_hcr_el2(); 724 /* 725 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 726 * accessing key registers or using pointer authentication instructions 727 * from lower ELs. 728 */ 729 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 730 731 write_hcr_el2(hcr_el2); 732 } 733 734 #if INIT_UNUSED_NS_EL2 735 /******************************************************************************* 736 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 737 * world when EL2 is empty and unused. 738 ******************************************************************************/ 739 static void manage_extensions_nonsecure_el2_unused(void) 740 { 741 #if IMAGE_BL31 742 if (is_feat_spe_supported()) { 743 spe_init_el2_unused(); 744 } 745 746 if (is_feat_amu_supported()) { 747 amu_init_el2_unused(); 748 } 749 750 if (is_feat_mpam_supported()) { 751 mpam_init_el2_unused(); 752 } 753 754 if (is_feat_trbe_supported()) { 755 trbe_init_el2_unused(); 756 } 757 758 if (is_feat_sys_reg_trace_supported()) { 759 sys_reg_trace_init_el2_unused(); 760 } 761 762 if (is_feat_trf_supported()) { 763 trf_init_el2_unused(); 764 } 765 766 pmuv3_init_el2_unused(); 767 768 if (is_feat_sve_supported()) { 769 sve_init_el2_unused(); 770 } 771 772 if (is_feat_sme_supported()) { 773 sme_init_el2_unused(); 774 } 775 776 #if ENABLE_PAUTH 777 enable_pauth_el2(); 778 #endif /* ENABLE_PAUTH */ 779 #endif /* IMAGE_BL31 */ 780 } 781 #endif /* INIT_UNUSED_NS_EL2 */ 782 783 /******************************************************************************* 784 * Enable architecture extensions on first entry to Secure world. 785 ******************************************************************************/ 786 static void manage_extensions_secure(cpu_context_t *ctx) 787 { 788 #if IMAGE_BL31 789 if (is_feat_sme_supported()) { 790 if (ENABLE_SME_FOR_SWD) { 791 /* 792 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 793 * must ensure SME, SVE, and FPU/SIMD context properly managed. 794 */ 795 sme_init_el3(); 796 sme_enable(ctx); 797 } else { 798 /* 799 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 800 * world can safely use the associated registers. 801 */ 802 sme_disable(ctx); 803 } 804 } 805 #endif /* IMAGE_BL31 */ 806 } 807 808 #if !IMAGE_BL1 809 /******************************************************************************* 810 * The following function initializes the cpu_context for a CPU specified by 811 * its `cpu_idx` for first use, and sets the initial entrypoint state as 812 * specified by the entry_point_info structure. 813 ******************************************************************************/ 814 void cm_init_context_by_index(unsigned int cpu_idx, 815 const entry_point_info_t *ep) 816 { 817 cpu_context_t *ctx; 818 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 819 cm_setup_context(ctx, ep); 820 } 821 #endif /* !IMAGE_BL1 */ 822 823 /******************************************************************************* 824 * The following function initializes the cpu_context for the current CPU 825 * for first use, and sets the initial entrypoint state as specified by the 826 * entry_point_info structure. 827 ******************************************************************************/ 828 void cm_init_my_context(const entry_point_info_t *ep) 829 { 830 cpu_context_t *ctx; 831 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 832 cm_setup_context(ctx, ep); 833 } 834 835 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 836 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 837 { 838 #if INIT_UNUSED_NS_EL2 839 u_register_t hcr_el2 = HCR_RESET_VAL; 840 u_register_t mdcr_el2; 841 u_register_t scr_el3; 842 843 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 844 845 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 846 if ((scr_el3 & SCR_RW_BIT) != 0U) { 847 hcr_el2 |= HCR_RW_BIT; 848 } 849 850 write_hcr_el2(hcr_el2); 851 852 /* 853 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 854 * All fields have architecturally UNKNOWN reset values. 855 */ 856 write_cptr_el2(CPTR_EL2_RESET_VAL); 857 858 /* 859 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 860 * reset and are set to zero except for field(s) listed below. 861 * 862 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 863 * Non-secure EL0 and EL1 accesses to the physical timer registers. 864 * 865 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 866 * Non-secure EL0 and EL1 accesses to the physical counter registers. 867 */ 868 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 869 870 /* 871 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 872 * UNKNOWN value. 873 */ 874 write_cntvoff_el2(0); 875 876 /* 877 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 878 * respectively. 879 */ 880 write_vpidr_el2(read_midr_el1()); 881 write_vmpidr_el2(read_mpidr_el1()); 882 883 /* 884 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 885 * 886 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 887 * translation is disabled, cache maintenance operations depend on the 888 * VMID. 889 * 890 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 891 * disabled. 892 */ 893 write_vttbr_el2(VTTBR_RESET_VAL & 894 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 895 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 896 897 /* 898 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 899 * Some fields are architecturally UNKNOWN on reset. 900 * 901 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 902 * register accesses to the Debug ROM registers are not trapped to EL2. 903 * 904 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 905 * accesses to the powerdown debug registers are not trapped to EL2. 906 * 907 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 908 * debug registers do not trap to EL2. 909 * 910 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 911 * EL2. 912 */ 913 mdcr_el2 = MDCR_EL2_RESET_VAL & 914 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 915 MDCR_EL2_TDE_BIT); 916 917 write_mdcr_el2(mdcr_el2); 918 919 /* 920 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 921 * 922 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 923 * EL1 accesses to System registers do not trap to EL2. 924 */ 925 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 926 927 /* 928 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 929 * reset. 930 * 931 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 932 * and prevent timer interrupts. 933 */ 934 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 935 936 manage_extensions_nonsecure_el2_unused(); 937 #endif /* INIT_UNUSED_NS_EL2 */ 938 } 939 940 /******************************************************************************* 941 * Prepare the CPU system registers for first entry into realm, secure, or 942 * normal world. 943 * 944 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 945 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 946 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 947 * For all entries, the EL1 registers are initialized from the cpu_context 948 ******************************************************************************/ 949 void cm_prepare_el3_exit(uint32_t security_state) 950 { 951 u_register_t sctlr_el2, scr_el3; 952 cpu_context_t *ctx = cm_get_context(security_state); 953 954 assert(ctx != NULL); 955 956 if (security_state == NON_SECURE) { 957 uint64_t el2_implemented = el_implemented(2); 958 959 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 960 CTX_SCR_EL3); 961 962 if (el2_implemented != EL_IMPL_NONE) { 963 964 /* 965 * If context is not being used for EL2, initialize 966 * HCRX_EL2 with its init value here. 967 */ 968 if (is_feat_hcx_supported()) { 969 write_hcrx_el2(HCRX_EL2_INIT_VAL); 970 } 971 972 /* 973 * Initialize Fine-grained trap registers introduced 974 * by FEAT_FGT so all traps are initially disabled when 975 * switching to EL2 or a lower EL, preventing undesired 976 * behavior. 977 */ 978 if (is_feat_fgt_supported()) { 979 /* 980 * Initialize HFG*_EL2 registers with a default 981 * value so legacy systems unaware of FEAT_FGT 982 * do not get trapped due to their lack of 983 * initialization for this feature. 984 */ 985 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 986 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 987 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 988 } 989 990 /* Condition to ensure EL2 is being used. */ 991 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 992 /* Initialize SCTLR_EL2 register with reset value. */ 993 sctlr_el2 = SCTLR_EL2_RES1; 994 #if ERRATA_A75_764081 995 /* 996 * If workaround of errata 764081 for Cortex-A75 997 * is used then set SCTLR_EL2.IESB to enable 998 * Implicit Error Synchronization Barrier. 999 */ 1000 sctlr_el2 |= SCTLR_IESB_BIT; 1001 #endif 1002 write_sctlr_el2(sctlr_el2); 1003 } else { 1004 /* 1005 * (scr_el3 & SCR_HCE_BIT==0) 1006 * EL2 implemented but unused. 1007 */ 1008 init_nonsecure_el2_unused(ctx); 1009 } 1010 } 1011 } 1012 cm_el1_sysregs_context_restore(security_state); 1013 cm_set_next_eret_context(security_state); 1014 } 1015 1016 #if CTX_INCLUDE_EL2_REGS 1017 1018 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1019 { 1020 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1021 if (is_feat_amu_supported()) { 1022 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1023 } 1024 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1025 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1026 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1027 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1028 } 1029 1030 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1031 { 1032 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1033 if (is_feat_amu_supported()) { 1034 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1035 } 1036 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1037 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1038 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1039 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1040 } 1041 1042 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1043 { 1044 u_register_t mpam_idr = read_mpamidr_el1(); 1045 1046 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1047 1048 /* 1049 * The context registers that we intend to save would be part of the 1050 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1051 */ 1052 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1053 return; 1054 } 1055 1056 /* 1057 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1058 * MPAMIDR_HAS_HCR_BIT == 1. 1059 */ 1060 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1061 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1062 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1063 1064 /* 1065 * The number of MPAMVPM registers is implementation defined, their 1066 * number is stored in the MPAMIDR_EL1 register. 1067 */ 1068 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1069 case 7: 1070 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1071 __fallthrough; 1072 case 6: 1073 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1074 __fallthrough; 1075 case 5: 1076 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1077 __fallthrough; 1078 case 4: 1079 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1080 __fallthrough; 1081 case 3: 1082 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1083 __fallthrough; 1084 case 2: 1085 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1086 __fallthrough; 1087 case 1: 1088 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1089 break; 1090 } 1091 } 1092 1093 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1094 { 1095 u_register_t mpam_idr = read_mpamidr_el1(); 1096 1097 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1098 1099 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1100 return; 1101 } 1102 1103 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1104 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1105 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1106 1107 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1108 case 7: 1109 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1110 __fallthrough; 1111 case 6: 1112 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1113 __fallthrough; 1114 case 5: 1115 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1116 __fallthrough; 1117 case 4: 1118 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1119 __fallthrough; 1120 case 3: 1121 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1122 __fallthrough; 1123 case 2: 1124 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1125 __fallthrough; 1126 case 1: 1127 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1128 break; 1129 } 1130 } 1131 1132 /* --------------------------------------------------------------------------- 1133 * The following registers are not added: 1134 * ICH_AP0R<n>_EL2 1135 * ICH_AP1R<n>_EL2 1136 * ICH_LR<n>_EL2 1137 * 1138 * NOTE: For a system with S-EL2 present but not enabled, accessing 1139 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1140 * SCR_EL3.NS = 1 before accessing this register. 1141 * --------------------------------------------------------------------------- 1142 */ 1143 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1144 { 1145 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1146 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1147 #else 1148 u_register_t scr_el3 = read_scr_el3(); 1149 write_scr_el3(scr_el3 | SCR_NS_BIT); 1150 isb(); 1151 1152 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1153 1154 write_scr_el3(scr_el3); 1155 isb(); 1156 #endif 1157 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1158 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1159 } 1160 1161 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1162 { 1163 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1164 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1165 #else 1166 u_register_t scr_el3 = read_scr_el3(); 1167 write_scr_el3(scr_el3 | SCR_NS_BIT); 1168 isb(); 1169 1170 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1171 1172 write_scr_el3(scr_el3); 1173 isb(); 1174 #endif 1175 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1176 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1177 } 1178 1179 /* ----------------------------------------------------- 1180 * The following registers are not added: 1181 * AMEVCNTVOFF0<n>_EL2 1182 * AMEVCNTVOFF1<n>_EL2 1183 * ----------------------------------------------------- 1184 */ 1185 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1186 { 1187 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1188 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1189 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1190 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1191 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1192 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1193 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1194 if (CTX_INCLUDE_AARCH32_REGS) { 1195 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1196 } 1197 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1198 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1199 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1200 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1201 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1202 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1203 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1204 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1205 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1206 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1207 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1208 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1209 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1210 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1211 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2()); 1212 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1213 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1214 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1215 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1216 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2()); 1217 } 1218 1219 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1220 { 1221 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1222 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1223 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1224 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1225 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1226 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1227 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1228 if (CTX_INCLUDE_AARCH32_REGS) { 1229 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1230 } 1231 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1232 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1233 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1234 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1235 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1236 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1237 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1238 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1239 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1240 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1241 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1242 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1243 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1244 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1245 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1246 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1247 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1248 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1249 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1250 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1251 } 1252 1253 /******************************************************************************* 1254 * Save EL2 sysreg context 1255 ******************************************************************************/ 1256 void cm_el2_sysregs_context_save(uint32_t security_state) 1257 { 1258 cpu_context_t *ctx; 1259 el2_sysregs_t *el2_sysregs_ctx; 1260 1261 ctx = cm_get_context(security_state); 1262 assert(ctx != NULL); 1263 1264 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1265 1266 el2_sysregs_context_save_common(el2_sysregs_ctx); 1267 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1268 1269 if (is_feat_mte2_supported()) { 1270 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1271 } 1272 1273 if (is_feat_mpam_supported()) { 1274 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1275 } 1276 1277 if (is_feat_fgt_supported()) { 1278 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1279 } 1280 1281 if (is_feat_ecv_v2_supported()) { 1282 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1283 } 1284 1285 if (is_feat_vhe_supported()) { 1286 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1287 read_contextidr_el2()); 1288 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1289 } 1290 1291 if (is_feat_ras_supported()) { 1292 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1293 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1294 } 1295 1296 if (is_feat_nv2_supported()) { 1297 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1298 } 1299 1300 if (is_feat_trf_supported()) { 1301 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1302 } 1303 1304 if (is_feat_csv2_2_supported()) { 1305 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1306 read_scxtnum_el2()); 1307 } 1308 1309 if (is_feat_hcx_supported()) { 1310 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1311 } 1312 1313 if (is_feat_tcr2_supported()) { 1314 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1315 } 1316 1317 if (is_feat_sxpie_supported()) { 1318 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1319 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1320 } 1321 1322 if (is_feat_sxpoe_supported()) { 1323 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1324 } 1325 1326 if (is_feat_s2pie_supported()) { 1327 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1328 } 1329 1330 if (is_feat_gcs_supported()) { 1331 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1332 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1333 } 1334 } 1335 1336 /******************************************************************************* 1337 * Restore EL2 sysreg context 1338 ******************************************************************************/ 1339 void cm_el2_sysregs_context_restore(uint32_t security_state) 1340 { 1341 cpu_context_t *ctx; 1342 el2_sysregs_t *el2_sysregs_ctx; 1343 1344 ctx = cm_get_context(security_state); 1345 assert(ctx != NULL); 1346 1347 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1348 1349 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1350 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1351 1352 if (is_feat_mte2_supported()) { 1353 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1354 } 1355 1356 if (is_feat_mpam_supported()) { 1357 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1358 } 1359 1360 if (is_feat_fgt_supported()) { 1361 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1362 } 1363 1364 if (is_feat_ecv_v2_supported()) { 1365 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1366 } 1367 1368 if (is_feat_vhe_supported()) { 1369 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1370 contextidr_el2)); 1371 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1372 } 1373 1374 if (is_feat_ras_supported()) { 1375 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1376 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1377 } 1378 1379 if (is_feat_nv2_supported()) { 1380 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1381 } 1382 1383 if (is_feat_trf_supported()) { 1384 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1385 } 1386 1387 if (is_feat_csv2_2_supported()) { 1388 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1389 scxtnum_el2)); 1390 } 1391 1392 if (is_feat_hcx_supported()) { 1393 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1394 } 1395 1396 if (is_feat_tcr2_supported()) { 1397 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1398 } 1399 1400 if (is_feat_sxpie_supported()) { 1401 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1402 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1403 } 1404 1405 if (is_feat_sxpoe_supported()) { 1406 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1407 } 1408 1409 if (is_feat_s2pie_supported()) { 1410 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1411 } 1412 1413 if (is_feat_gcs_supported()) { 1414 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1415 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1416 } 1417 } 1418 #endif /* CTX_INCLUDE_EL2_REGS */ 1419 1420 /******************************************************************************* 1421 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1422 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1423 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1424 * cm_prepare_el3_exit function. 1425 ******************************************************************************/ 1426 void cm_prepare_el3_exit_ns(void) 1427 { 1428 #if CTX_INCLUDE_EL2_REGS 1429 #if ENABLE_ASSERTIONS 1430 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1431 assert(ctx != NULL); 1432 1433 /* Assert that EL2 is used. */ 1434 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1435 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1436 (el_implemented(2U) != EL_IMPL_NONE)); 1437 #endif /* ENABLE_ASSERTIONS */ 1438 1439 /* Restore EL2 and EL1 sysreg contexts */ 1440 cm_el2_sysregs_context_restore(NON_SECURE); 1441 cm_el1_sysregs_context_restore(NON_SECURE); 1442 cm_set_next_eret_context(NON_SECURE); 1443 #else 1444 cm_prepare_el3_exit(NON_SECURE); 1445 #endif /* CTX_INCLUDE_EL2_REGS */ 1446 } 1447 1448 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1449 { 1450 write_ctx_reg(ctx, CTX_SPSR_EL1, read_spsr_el1()); 1451 write_ctx_reg(ctx, CTX_ELR_EL1, read_elr_el1()); 1452 1453 #if !ERRATA_SPECULATIVE_AT 1454 write_ctx_reg(ctx, CTX_SCTLR_EL1, read_sctlr_el1()); 1455 write_ctx_reg(ctx, CTX_TCR_EL1, read_tcr_el1()); 1456 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1457 1458 write_ctx_reg(ctx, CTX_CPACR_EL1, read_cpacr_el1()); 1459 write_ctx_reg(ctx, CTX_CSSELR_EL1, read_csselr_el1()); 1460 write_ctx_reg(ctx, CTX_SP_EL1, read_sp_el1()); 1461 write_ctx_reg(ctx, CTX_ESR_EL1, read_esr_el1()); 1462 write_ctx_reg(ctx, CTX_TTBR0_EL1, read_ttbr0_el1()); 1463 write_ctx_reg(ctx, CTX_TTBR1_EL1, read_ttbr1_el1()); 1464 write_ctx_reg(ctx, CTX_MAIR_EL1, read_mair_el1()); 1465 write_ctx_reg(ctx, CTX_AMAIR_EL1, read_amair_el1()); 1466 write_ctx_reg(ctx, CTX_ACTLR_EL1, read_actlr_el1()); 1467 write_ctx_reg(ctx, CTX_TPIDR_EL1, read_tpidr_el1()); 1468 write_ctx_reg(ctx, CTX_TPIDR_EL0, read_tpidr_el0()); 1469 write_ctx_reg(ctx, CTX_TPIDRRO_EL0, read_tpidrro_el0()); 1470 write_ctx_reg(ctx, CTX_PAR_EL1, read_par_el1()); 1471 write_ctx_reg(ctx, CTX_FAR_EL1, read_far_el1()); 1472 write_ctx_reg(ctx, CTX_AFSR0_EL1, read_afsr0_el1()); 1473 write_ctx_reg(ctx, CTX_AFSR1_EL1, read_afsr1_el1()); 1474 write_ctx_reg(ctx, CTX_CONTEXTIDR_EL1, read_contextidr_el1()); 1475 write_ctx_reg(ctx, CTX_VBAR_EL1, read_vbar_el1()); 1476 write_ctx_reg(ctx, CTX_MDCCINT_EL1, read_mdccint_el1()); 1477 write_ctx_reg(ctx, CTX_MDSCR_EL1, read_mdscr_el1()); 1478 1479 #if CTX_INCLUDE_AARCH32_REGS 1480 write_ctx_reg(ctx, CTX_SPSR_ABT, read_spsr_abt()); 1481 write_ctx_reg(ctx, CTX_SPSR_UND, read_spsr_und()); 1482 write_ctx_reg(ctx, CTX_SPSR_IRQ, read_spsr_irq()); 1483 write_ctx_reg(ctx, CTX_SPSR_FIQ, read_spsr_fiq()); 1484 write_ctx_reg(ctx, CTX_DACR32_EL2, read_dacr32_el2()); 1485 write_ctx_reg(ctx, CTX_IFSR32_EL2, read_ifsr32_el2()); 1486 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1487 1488 #if NS_TIMER_SWITCH 1489 write_ctx_reg(ctx, CTX_CNTP_CTL_EL0, read_cntp_ctl_el0()); 1490 write_ctx_reg(ctx, CTX_CNTP_CVAL_EL0, read_cntp_cval_el0()); 1491 write_ctx_reg(ctx, CTX_CNTV_CTL_EL0, read_cntv_ctl_el0()); 1492 write_ctx_reg(ctx, CTX_CNTV_CVAL_EL0, read_cntv_cval_el0()); 1493 write_ctx_reg(ctx, CTX_CNTKCTL_EL1, read_cntkctl_el1()); 1494 #endif /* NS_TIMER_SWITCH */ 1495 1496 #if ENABLE_FEAT_MTE2 1497 write_ctx_reg(ctx, CTX_TFSRE0_EL1, read_tfsre0_el1()); 1498 write_ctx_reg(ctx, CTX_TFSR_EL1, read_tfsr_el1()); 1499 write_ctx_reg(ctx, CTX_RGSR_EL1, read_rgsr_el1()); 1500 write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1()); 1501 #endif /* ENABLE_FEAT_MTE2 */ 1502 1503 #if ENABLE_FEAT_RAS 1504 if (is_feat_ras_supported()) { 1505 write_ctx_reg(ctx, CTX_DISR_EL1, read_disr_el1()); 1506 } 1507 #endif 1508 1509 #if ENABLE_FEAT_S1PIE 1510 if (is_feat_s1pie_supported()) { 1511 write_ctx_reg(ctx, CTX_PIRE0_EL1, read_pire0_el1()); 1512 write_ctx_reg(ctx, CTX_PIR_EL1, read_pir_el1()); 1513 } 1514 #endif 1515 1516 #if ENABLE_FEAT_S1POE 1517 if (is_feat_s1poe_supported()) { 1518 write_ctx_reg(ctx, CTX_POR_EL1, read_por_el1()); 1519 } 1520 #endif 1521 1522 #if ENABLE_FEAT_S2POE 1523 if (is_feat_s2poe_supported()) { 1524 write_ctx_reg(ctx, CTX_S2POR_EL1, read_s2por_el1()); 1525 } 1526 #endif 1527 1528 #if ENABLE_FEAT_TCR2 1529 if (is_feat_tcr2_supported()) { 1530 write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1()); 1531 } 1532 #endif 1533 1534 #if ENABLE_TRF_FOR_NS 1535 if (is_feat_trf_supported()) { 1536 write_ctx_reg(ctx, CTX_TRFCR_EL1, read_trfcr_el1()); 1537 } 1538 #endif 1539 1540 #if ENABLE_FEAT_CSV2_2 1541 if (is_feat_csv2_2_supported()) { 1542 write_ctx_reg(ctx, CTX_SCXTNUM_EL0, read_scxtnum_el0()); 1543 write_ctx_reg(ctx, CTX_SCXTNUM_EL1, read_scxtnum_el1()); 1544 } 1545 #endif 1546 1547 #if ENABLE_FEAT_GCS 1548 if (is_feat_gcs_supported()) { 1549 write_ctx_reg(ctx, CTX_GCSCR_EL1, read_gcscr_el1()); 1550 write_ctx_reg(ctx, CTX_GCSCRE0_EL1, read_gcscre0_el1()); 1551 write_ctx_reg(ctx, CTX_GCSPR_EL1, read_gcspr_el1()); 1552 write_ctx_reg(ctx, CTX_GCSPR_EL0, read_gcspr_el0()); 1553 } 1554 #endif 1555 } 1556 1557 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1558 { 1559 write_spsr_el1(read_ctx_reg(ctx, CTX_SPSR_EL1)); 1560 write_elr_el1(read_ctx_reg(ctx, CTX_ELR_EL1)); 1561 1562 #if !ERRATA_SPECULATIVE_AT 1563 write_sctlr_el1(read_ctx_reg(ctx, CTX_SCTLR_EL1)); 1564 write_tcr_el1(read_ctx_reg(ctx, CTX_TCR_EL1)); 1565 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1566 1567 write_cpacr_el1(read_ctx_reg(ctx, CTX_CPACR_EL1)); 1568 write_csselr_el1(read_ctx_reg(ctx, CTX_CSSELR_EL1)); 1569 write_sp_el1(read_ctx_reg(ctx, CTX_SP_EL1)); 1570 write_esr_el1(read_ctx_reg(ctx, CTX_ESR_EL1)); 1571 write_ttbr0_el1(read_ctx_reg(ctx, CTX_TTBR0_EL1)); 1572 write_ttbr1_el1(read_ctx_reg(ctx, CTX_TTBR1_EL1)); 1573 write_mair_el1(read_ctx_reg(ctx, CTX_MAIR_EL1)); 1574 write_amair_el1(read_ctx_reg(ctx, CTX_AMAIR_EL1)); 1575 write_actlr_el1(read_ctx_reg(ctx, CTX_ACTLR_EL1)); 1576 write_tpidr_el1(read_ctx_reg(ctx, CTX_TPIDR_EL1)); 1577 write_tpidr_el0(read_ctx_reg(ctx, CTX_TPIDR_EL0)); 1578 write_tpidrro_el0(read_ctx_reg(ctx, CTX_TPIDRRO_EL0)); 1579 write_par_el1(read_ctx_reg(ctx, CTX_PAR_EL1)); 1580 write_far_el1(read_ctx_reg(ctx, CTX_FAR_EL1)); 1581 write_afsr0_el1(read_ctx_reg(ctx, CTX_AFSR0_EL1)); 1582 write_afsr1_el1(read_ctx_reg(ctx, CTX_AFSR1_EL1)); 1583 write_contextidr_el1(read_ctx_reg(ctx, CTX_CONTEXTIDR_EL1)); 1584 write_vbar_el1(read_ctx_reg(ctx, CTX_VBAR_EL1)); 1585 write_mdccint_el1(read_ctx_reg(ctx, CTX_MDCCINT_EL1)); 1586 write_mdscr_el1(read_ctx_reg(ctx, CTX_MDSCR_EL1)); 1587 1588 #if CTX_INCLUDE_AARCH32_REGS 1589 write_spsr_abt(read_ctx_reg(ctx, CTX_SPSR_ABT)); 1590 write_spsr_und(read_ctx_reg(ctx, CTX_SPSR_UND)); 1591 write_spsr_irq(read_ctx_reg(ctx, CTX_SPSR_IRQ)); 1592 write_spsr_fiq(read_ctx_reg(ctx, CTX_SPSR_FIQ)); 1593 write_dacr32_el2(read_ctx_reg(ctx, CTX_DACR32_EL2)); 1594 write_ifsr32_el2(read_ctx_reg(ctx, CTX_IFSR32_EL2)); 1595 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1596 1597 #if NS_TIMER_SWITCH 1598 write_cntp_ctl_el0(read_ctx_reg(ctx, CTX_CNTP_CTL_EL0)); 1599 write_cntp_cval_el0(read_ctx_reg(ctx, CTX_CNTP_CVAL_EL0)); 1600 write_cntv_ctl_el0(read_ctx_reg(ctx, CTX_CNTV_CTL_EL0)); 1601 write_cntv_cval_el0(read_ctx_reg(ctx, CTX_CNTV_CVAL_EL0)); 1602 write_cntkctl_el1(read_ctx_reg(ctx, CTX_CNTKCTL_EL1)); 1603 #endif /* NS_TIMER_SWITCH */ 1604 1605 #if ENABLE_FEAT_MTE2 1606 write_tfsre0_el1(read_ctx_reg(ctx, CTX_TFSRE0_EL1)); 1607 write_tfsr_el1(read_ctx_reg(ctx, CTX_TFSR_EL1)); 1608 write_rgsr_el1(read_ctx_reg(ctx, CTX_RGSR_EL1)); 1609 write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1)); 1610 #endif /* ENABLE_FEAT_MTE2 */ 1611 1612 #if ENABLE_FEAT_RAS 1613 if (is_feat_ras_supported()) { 1614 write_disr_el1(read_ctx_reg(ctx, CTX_DISR_EL1)); 1615 } 1616 #endif 1617 1618 #if ENABLE_FEAT_S1PIE 1619 if (is_feat_s1pie_supported()) { 1620 write_pire0_el1(read_ctx_reg(ctx, CTX_PIRE0_EL1)); 1621 write_pir_el1(read_ctx_reg(ctx, CTX_PIR_EL1)); 1622 } 1623 #endif 1624 1625 #if ENABLE_FEAT_S1POE 1626 if (is_feat_s1poe_supported()) { 1627 write_por_el1(read_ctx_reg(ctx, CTX_POR_EL1)); 1628 } 1629 #endif 1630 1631 #if ENABLE_FEAT_S2POE 1632 if (is_feat_s2poe_supported()) { 1633 write_s2por_el1(read_ctx_reg(ctx, CTX_S2POR_EL1)); 1634 } 1635 #endif 1636 1637 #if ENABLE_FEAT_TCR2 1638 if (is_feat_tcr2_supported()) { 1639 write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1)); 1640 } 1641 #endif 1642 1643 #if ENABLE_TRF_FOR_NS 1644 if (is_feat_trf_supported()) { 1645 write_trfcr_el1(read_ctx_reg(ctx, CTX_TRFCR_EL1)); 1646 } 1647 #endif 1648 1649 #if ENABLE_FEAT_CSV2_2 1650 if (is_feat_csv2_2_supported()) { 1651 write_scxtnum_el0(read_ctx_reg(ctx, CTX_SCXTNUM_EL0)); 1652 write_scxtnum_el1(read_ctx_reg(ctx, CTX_SCXTNUM_EL1)); 1653 } 1654 #endif 1655 1656 #if ENABLE_FEAT_GCS 1657 if (is_feat_gcs_supported()) { 1658 write_gcscr_el1(read_ctx_reg(ctx, CTX_GCSCR_EL1)); 1659 write_gcscre0_el1(read_ctx_reg(ctx, CTX_GCSCRE0_EL1)); 1660 write_gcspr_el1(read_ctx_reg(ctx, CTX_GCSPR_EL1)); 1661 write_gcspr_el0(read_ctx_reg(ctx, CTX_GCSPR_EL0)); 1662 } 1663 #endif 1664 } 1665 1666 /******************************************************************************* 1667 * The next four functions are used by runtime services to save and restore 1668 * EL1 context on the 'cpu_context' structure for the specified security 1669 * state. 1670 ******************************************************************************/ 1671 void cm_el1_sysregs_context_save(uint32_t security_state) 1672 { 1673 cpu_context_t *ctx; 1674 1675 ctx = cm_get_context(security_state); 1676 assert(ctx != NULL); 1677 1678 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1679 1680 #if IMAGE_BL31 1681 if (security_state == SECURE) 1682 PUBLISH_EVENT(cm_exited_secure_world); 1683 else 1684 PUBLISH_EVENT(cm_exited_normal_world); 1685 #endif 1686 } 1687 1688 void cm_el1_sysregs_context_restore(uint32_t security_state) 1689 { 1690 cpu_context_t *ctx; 1691 1692 ctx = cm_get_context(security_state); 1693 assert(ctx != NULL); 1694 1695 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1696 1697 #if IMAGE_BL31 1698 if (security_state == SECURE) 1699 PUBLISH_EVENT(cm_entering_secure_world); 1700 else 1701 PUBLISH_EVENT(cm_entering_normal_world); 1702 #endif 1703 } 1704 1705 /******************************************************************************* 1706 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1707 * given security state with the given entrypoint 1708 ******************************************************************************/ 1709 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1710 { 1711 cpu_context_t *ctx; 1712 el3_state_t *state; 1713 1714 ctx = cm_get_context(security_state); 1715 assert(ctx != NULL); 1716 1717 /* Populate EL3 state so that ERET jumps to the correct entry */ 1718 state = get_el3state_ctx(ctx); 1719 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1720 } 1721 1722 /******************************************************************************* 1723 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1724 * pertaining to the given security state 1725 ******************************************************************************/ 1726 void cm_set_elr_spsr_el3(uint32_t security_state, 1727 uintptr_t entrypoint, uint32_t spsr) 1728 { 1729 cpu_context_t *ctx; 1730 el3_state_t *state; 1731 1732 ctx = cm_get_context(security_state); 1733 assert(ctx != NULL); 1734 1735 /* Populate EL3 state so that ERET jumps to the correct entry */ 1736 state = get_el3state_ctx(ctx); 1737 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1738 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1739 } 1740 1741 /******************************************************************************* 1742 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1743 * pertaining to the given security state using the value and bit position 1744 * specified in the parameters. It preserves all other bits. 1745 ******************************************************************************/ 1746 void cm_write_scr_el3_bit(uint32_t security_state, 1747 uint32_t bit_pos, 1748 uint32_t value) 1749 { 1750 cpu_context_t *ctx; 1751 el3_state_t *state; 1752 u_register_t scr_el3; 1753 1754 ctx = cm_get_context(security_state); 1755 assert(ctx != NULL); 1756 1757 /* Ensure that the bit position is a valid one */ 1758 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1759 1760 /* Ensure that the 'value' is only a bit wide */ 1761 assert(value <= 1U); 1762 1763 /* 1764 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1765 * and set it to its new value. 1766 */ 1767 state = get_el3state_ctx(ctx); 1768 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1769 scr_el3 &= ~(1UL << bit_pos); 1770 scr_el3 |= (u_register_t)value << bit_pos; 1771 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1772 } 1773 1774 /******************************************************************************* 1775 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1776 * given security state. 1777 ******************************************************************************/ 1778 u_register_t cm_get_scr_el3(uint32_t security_state) 1779 { 1780 cpu_context_t *ctx; 1781 el3_state_t *state; 1782 1783 ctx = cm_get_context(security_state); 1784 assert(ctx != NULL); 1785 1786 /* Populate EL3 state so that ERET jumps to the correct entry */ 1787 state = get_el3state_ctx(ctx); 1788 return read_ctx_reg(state, CTX_SCR_EL3); 1789 } 1790 1791 /******************************************************************************* 1792 * This function is used to program the context that's used for exception 1793 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1794 * the required security state 1795 ******************************************************************************/ 1796 void cm_set_next_eret_context(uint32_t security_state) 1797 { 1798 cpu_context_t *ctx; 1799 1800 ctx = cm_get_context(security_state); 1801 assert(ctx != NULL); 1802 1803 cm_set_next_context(ctx); 1804 } 1805