1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/sme.h> 28 #include <lib/extensions/spe.h> 29 #include <lib/extensions/sve.h> 30 #include <lib/extensions/sys_reg_trace.h> 31 #include <lib/extensions/trbe.h> 32 #include <lib/extensions/trf.h> 33 #include <lib/utils.h> 34 35 #if ENABLE_FEAT_TWED 36 /* Make sure delay value fits within the range(0-15) */ 37 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 38 #endif /* ENABLE_FEAT_TWED */ 39 40 static void manage_extensions_secure(cpu_context_t *ctx); 41 42 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 43 { 44 u_register_t sctlr_elx, actlr_elx; 45 46 /* 47 * Initialise SCTLR_EL1 to the reset value corresponding to the target 48 * execution state setting all fields rather than relying on the hw. 49 * Some fields have architecturally UNKNOWN reset values and these are 50 * set to zero. 51 * 52 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 53 * 54 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 55 * required by PSCI specification) 56 */ 57 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 58 if (GET_RW(ep->spsr) == MODE_RW_64) { 59 sctlr_elx |= SCTLR_EL1_RES1; 60 } else { 61 /* 62 * If the target execution state is AArch32 then the following 63 * fields need to be set. 64 * 65 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 66 * instructions are not trapped to EL1. 67 * 68 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 69 * instructions are not trapped to EL1. 70 * 71 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 72 * CP15DMB, CP15DSB, and CP15ISB instructions. 73 */ 74 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 75 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 76 } 77 78 #if ERRATA_A75_764081 79 /* 80 * If workaround of errata 764081 for Cortex-A75 is used then set 81 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 82 */ 83 sctlr_elx |= SCTLR_IESB_BIT; 84 #endif 85 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 86 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 87 88 /* 89 * Base the context ACTLR_EL1 on the current value, as it is 90 * implementation defined. The context restore process will write 91 * the value from the context to the actual register and can cause 92 * problems for processor cores that don't expect certain bits to 93 * be zero. 94 */ 95 actlr_elx = read_actlr_el1(); 96 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 97 } 98 99 /****************************************************************************** 100 * This function performs initializations that are specific to SECURE state 101 * and updates the cpu context specified by 'ctx'. 102 *****************************************************************************/ 103 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 104 { 105 u_register_t scr_el3; 106 el3_state_t *state; 107 108 state = get_el3state_ctx(ctx); 109 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 110 111 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 112 /* 113 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 114 * indicated by the interrupt routing model for BL31. 115 */ 116 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 117 #endif 118 119 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 120 /* Get Memory Tagging Extension support level */ 121 unsigned int mte = get_armv8_5_mte_support(); 122 #endif 123 /* 124 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 125 * is set, or when MTE is only implemented at EL0. 126 */ 127 #if CTX_INCLUDE_MTE_REGS 128 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 129 scr_el3 |= SCR_ATA_BIT; 130 #else 131 if (mte == MTE_IMPLEMENTED_EL0) { 132 scr_el3 |= SCR_ATA_BIT; 133 } 134 #endif /* CTX_INCLUDE_MTE_REGS */ 135 136 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 137 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) { 138 if (GET_RW(ep->spsr) != MODE_RW_64) { 139 ERROR("S-EL2 can not be used in AArch32\n."); 140 panic(); 141 } 142 143 scr_el3 |= SCR_EEL2_BIT; 144 } 145 146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 147 148 /* 149 * Initialize EL1 context registers unless SPMC is running 150 * at S-EL2. 151 */ 152 #if !SPMD_SPM_AT_SEL2 153 setup_el1_context(ctx, ep); 154 #endif 155 156 manage_extensions_secure(ctx); 157 } 158 159 #if ENABLE_RME 160 /****************************************************************************** 161 * This function performs initializations that are specific to REALM state 162 * and updates the cpu context specified by 'ctx'. 163 *****************************************************************************/ 164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 165 { 166 u_register_t scr_el3; 167 el3_state_t *state; 168 169 state = get_el3state_ctx(ctx); 170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT; 173 174 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 175 } 176 #endif /* ENABLE_RME */ 177 178 /****************************************************************************** 179 * This function performs initializations that are specific to NON-SECURE state 180 * and updates the cpu context specified by 'ctx'. 181 *****************************************************************************/ 182 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 183 { 184 u_register_t scr_el3; 185 el3_state_t *state; 186 187 state = get_el3state_ctx(ctx); 188 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 189 190 /* SCR_NS: Set the NS bit */ 191 scr_el3 |= SCR_NS_BIT; 192 193 #if !CTX_INCLUDE_PAUTH_REGS 194 /* 195 * If the pointer authentication registers aren't saved during world 196 * switches the value of the registers can be leaked from the Secure to 197 * the Non-secure world. To prevent this, rather than enabling pointer 198 * authentication everywhere, we only enable it in the Non-secure world. 199 * 200 * If the Secure world wants to use pointer authentication, 201 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 202 */ 203 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 204 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 205 206 /* Allow access to Allocation Tags when MTE is implemented. */ 207 scr_el3 |= SCR_ATA_BIT; 208 209 #if RAS_TRAP_NS_ERR_REC_ACCESS 210 /* 211 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 212 * and RAS ERX registers from EL1 and EL2(from any security state) 213 * are trapped to EL3. 214 * Set here to trap only for NS EL1/EL2 215 * 216 */ 217 scr_el3 |= SCR_TERR_BIT; 218 #endif 219 220 #ifdef IMAGE_BL31 221 /* 222 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 223 * indicated by the interrupt routing model for BL31. 224 */ 225 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 226 #endif 227 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 228 229 /* Initialize EL1 context registers */ 230 setup_el1_context(ctx, ep); 231 232 /* Initialize EL2 context registers */ 233 #if CTX_INCLUDE_EL2_REGS 234 235 /* 236 * Initialize SCTLR_EL2 context register using Endianness value 237 * taken from the entrypoint attribute. 238 */ 239 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 240 sctlr_el2 |= SCTLR_EL2_RES1; 241 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 242 sctlr_el2); 243 244 /* 245 * Program the ICC_SRE_EL2 to make sure the correct bits are set 246 * when restoring NS context. 247 */ 248 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 249 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 250 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 251 icc_sre_el2); 252 253 /* 254 * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't 255 * throw anyone off who expects this to be sensible. 256 * TODO: A similar thing happens in cm_prepare_el3_exit. They should be 257 * unified with the proper PMU implementation 258 */ 259 u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & 260 PMCR_EL0_N_MASK); 261 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2); 262 #endif /* CTX_INCLUDE_EL2_REGS */ 263 } 264 265 /******************************************************************************* 266 * The following function performs initialization of the cpu_context 'ctx' 267 * for first use that is common to all security states, and sets the 268 * initial entrypoint state as specified by the entry_point_info structure. 269 * 270 * The EE and ST attributes are used to configure the endianness and secure 271 * timer availability for the new execution context. 272 ******************************************************************************/ 273 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 274 { 275 u_register_t scr_el3; 276 el3_state_t *state; 277 gp_regs_t *gp_regs; 278 279 /* Clear any residual register values from the context */ 280 zeromem(ctx, sizeof(*ctx)); 281 282 /* 283 * SCR_EL3 was initialised during reset sequence in macro 284 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 285 * affect the next EL. 286 * 287 * The following fields are initially set to zero and then updated to 288 * the required value depending on the state of the SPSR_EL3 and the 289 * Security state and entrypoint attributes of the next EL. 290 */ 291 scr_el3 = read_scr(); 292 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 293 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 294 295 /* 296 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 297 * Exception level as specified by SPSR. 298 */ 299 if (GET_RW(ep->spsr) == MODE_RW_64) { 300 scr_el3 |= SCR_RW_BIT; 301 } 302 303 /* 304 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 305 * Secure timer registers to EL3, from AArch64 state only, if specified 306 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 307 * bit always behaves as 1 (i.e. secure physical timer register access 308 * is not trapped) 309 */ 310 if (EP_GET_ST(ep->h.attr) != 0U) { 311 scr_el3 |= SCR_ST_BIT; 312 } 313 314 /* 315 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 316 * SCR_EL3.HXEn. 317 */ 318 #if ENABLE_FEAT_HCX 319 scr_el3 |= SCR_HXEn_BIT; 320 #endif 321 322 /* 323 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 324 * registers are trapped to EL3. 325 */ 326 #if ENABLE_FEAT_RNG_TRAP 327 scr_el3 |= SCR_TRNDR_BIT; 328 #endif 329 330 #if !HANDLE_EA_EL3_FIRST 331 /* 332 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 333 * to EL3 when executing at a lower EL. When executing at EL3, External 334 * Aborts are taken to EL3. 335 */ 336 scr_el3 &= ~SCR_EA_BIT; 337 #endif 338 339 #if FAULT_INJECTION_SUPPORT 340 /* Enable fault injection from lower ELs */ 341 scr_el3 |= SCR_FIEN_BIT; 342 #endif 343 344 /* 345 * CPTR_EL3 was initialized out of reset, copy that value to the 346 * context register. 347 */ 348 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 349 350 /* 351 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 352 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 353 * next mode is Hyp. 354 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 355 * same conditions as HVC instructions and when the processor supports 356 * ARMv8.6-FGT. 357 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 358 * CNTPOFF_EL2 register under the same conditions as HVC instructions 359 * and when the processor supports ECV. 360 */ 361 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 362 || ((GET_RW(ep->spsr) != MODE_RW_64) 363 && (GET_M32(ep->spsr) == MODE32_hyp))) { 364 scr_el3 |= SCR_HCE_BIT; 365 366 if (is_armv8_6_fgt_present()) { 367 scr_el3 |= SCR_FGTEN_BIT; 368 } 369 370 if (get_armv8_6_ecv_support() 371 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 372 scr_el3 |= SCR_ECVEN_BIT; 373 } 374 } 375 376 #if ENABLE_FEAT_TWED 377 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 378 /* Set delay in SCR_EL3 */ 379 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 380 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 381 << SCR_TWEDEL_SHIFT); 382 383 /* Enable WFE delay */ 384 scr_el3 |= SCR_TWEDEn_BIT; 385 #endif /* ENABLE_FEAT_TWED */ 386 387 /* 388 * Populate EL3 state so that we've the right context 389 * before doing ERET 390 */ 391 state = get_el3state_ctx(ctx); 392 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 393 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 394 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 395 396 /* 397 * Store the X0-X7 value from the entrypoint into the context 398 * Use memcpy as we are in control of the layout of the structures 399 */ 400 gp_regs = get_gpregs_ctx(ctx); 401 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 402 } 403 404 /******************************************************************************* 405 * Context management library initialization routine. This library is used by 406 * runtime services to share pointers to 'cpu_context' structures for secure 407 * non-secure and realm states. Management of the structures and their associated 408 * memory is not done by the context management library e.g. the PSCI service 409 * manages the cpu context used for entry from and exit to the non-secure state. 410 * The Secure payload dispatcher service manages the context(s) corresponding to 411 * the secure state. It also uses this library to get access to the non-secure 412 * state cpu context pointers. 413 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 414 * which will be used for programming an entry into a lower EL. The same context 415 * will be used to save state upon exception entry from that EL. 416 ******************************************************************************/ 417 void __init cm_init(void) 418 { 419 /* 420 * The context management library has only global data to intialize, but 421 * that will be done when the BSS is zeroed out. 422 */ 423 } 424 425 /******************************************************************************* 426 * This is the high-level function used to initialize the cpu_context 'ctx' for 427 * first use. It performs initializations that are common to all security states 428 * and initializations specific to the security state specified in 'ep' 429 ******************************************************************************/ 430 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 431 { 432 unsigned int security_state; 433 434 assert(ctx != NULL); 435 436 /* 437 * Perform initializations that are common 438 * to all security states 439 */ 440 setup_context_common(ctx, ep); 441 442 security_state = GET_SECURITY_STATE(ep->h.attr); 443 444 /* Perform security state specific initializations */ 445 switch (security_state) { 446 case SECURE: 447 setup_secure_context(ctx, ep); 448 break; 449 #if ENABLE_RME 450 case REALM: 451 setup_realm_context(ctx, ep); 452 break; 453 #endif 454 case NON_SECURE: 455 setup_ns_context(ctx, ep); 456 break; 457 default: 458 ERROR("Invalid security state\n"); 459 panic(); 460 break; 461 } 462 } 463 464 /******************************************************************************* 465 * Enable architecture extensions on first entry to Non-secure world. 466 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 467 * it is zero. 468 ******************************************************************************/ 469 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 470 { 471 #if IMAGE_BL31 472 #if ENABLE_SPE_FOR_LOWER_ELS 473 spe_enable(el2_unused); 474 #endif 475 476 #if ENABLE_AMU 477 amu_enable(el2_unused, ctx); 478 #endif 479 480 #if ENABLE_SME_FOR_NS 481 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 482 sme_enable(ctx); 483 #elif ENABLE_SVE_FOR_NS 484 /* Enable SVE and FPU/SIMD for non-secure world. */ 485 sve_enable(ctx); 486 #endif 487 488 #if ENABLE_MPAM_FOR_LOWER_ELS 489 mpam_enable(el2_unused); 490 #endif 491 492 #if ENABLE_TRBE_FOR_NS 493 trbe_enable(); 494 #endif /* ENABLE_TRBE_FOR_NS */ 495 496 #if ENABLE_BRBE_FOR_NS 497 brbe_enable(); 498 #endif /* ENABLE_BRBE_FOR_NS */ 499 500 #if ENABLE_SYS_REG_TRACE_FOR_NS 501 sys_reg_trace_enable(ctx); 502 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 503 504 #if ENABLE_TRF_FOR_NS 505 trf_enable(); 506 #endif /* ENABLE_TRF_FOR_NS */ 507 #endif 508 } 509 510 /******************************************************************************* 511 * Enable architecture extensions on first entry to Secure world. 512 ******************************************************************************/ 513 static void manage_extensions_secure(cpu_context_t *ctx) 514 { 515 #if IMAGE_BL31 516 #if ENABLE_SME_FOR_NS 517 #if ENABLE_SME_FOR_SWD 518 /* 519 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must 520 * ensure SME, SVE, and FPU/SIMD context properly managed. 521 */ 522 sme_enable(ctx); 523 #else /* ENABLE_SME_FOR_SWD */ 524 /* 525 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can 526 * safely use the associated registers. 527 */ 528 sme_disable(ctx); 529 #endif /* ENABLE_SME_FOR_SWD */ 530 #elif ENABLE_SVE_FOR_NS 531 #if ENABLE_SVE_FOR_SWD 532 /* 533 * Enable SVE and FPU in secure context, secure manager must ensure that 534 * the SVE and FPU register contexts are properly managed. 535 */ 536 sve_enable(ctx); 537 #else /* ENABLE_SVE_FOR_SWD */ 538 /* 539 * Disable SVE and FPU in secure context so non-secure world can safely 540 * use them. 541 */ 542 sve_disable(ctx); 543 #endif /* ENABLE_SVE_FOR_SWD */ 544 #endif /* ENABLE_SVE_FOR_NS */ 545 #endif /* IMAGE_BL31 */ 546 } 547 548 /******************************************************************************* 549 * The following function initializes the cpu_context for a CPU specified by 550 * its `cpu_idx` for first use, and sets the initial entrypoint state as 551 * specified by the entry_point_info structure. 552 ******************************************************************************/ 553 void cm_init_context_by_index(unsigned int cpu_idx, 554 const entry_point_info_t *ep) 555 { 556 cpu_context_t *ctx; 557 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 558 cm_setup_context(ctx, ep); 559 } 560 561 /******************************************************************************* 562 * The following function initializes the cpu_context for the current CPU 563 * for first use, and sets the initial entrypoint state as specified by the 564 * entry_point_info structure. 565 ******************************************************************************/ 566 void cm_init_my_context(const entry_point_info_t *ep) 567 { 568 cpu_context_t *ctx; 569 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 570 cm_setup_context(ctx, ep); 571 } 572 573 /******************************************************************************* 574 * Prepare the CPU system registers for first entry into realm, secure, or 575 * normal world. 576 * 577 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 578 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 579 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 580 * For all entries, the EL1 registers are initialized from the cpu_context 581 ******************************************************************************/ 582 void cm_prepare_el3_exit(uint32_t security_state) 583 { 584 u_register_t sctlr_elx, scr_el3, mdcr_el2; 585 cpu_context_t *ctx = cm_get_context(security_state); 586 bool el2_unused = false; 587 uint64_t hcr_el2 = 0U; 588 589 assert(ctx != NULL); 590 591 if (security_state == NON_SECURE) { 592 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 593 CTX_SCR_EL3); 594 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 595 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 596 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 597 CTX_SCTLR_EL1); 598 sctlr_elx &= SCTLR_EE_BIT; 599 sctlr_elx |= SCTLR_EL2_RES1; 600 #if ERRATA_A75_764081 601 /* 602 * If workaround of errata 764081 for Cortex-A75 is used 603 * then set SCTLR_EL2.IESB to enable Implicit Error 604 * Synchronization Barrier. 605 */ 606 sctlr_elx |= SCTLR_IESB_BIT; 607 #endif 608 write_sctlr_el2(sctlr_elx); 609 } else if (el_implemented(2) != EL_IMPL_NONE) { 610 el2_unused = true; 611 612 /* 613 * EL2 present but unused, need to disable safely. 614 * SCTLR_EL2 can be ignored in this case. 615 * 616 * Set EL2 register width appropriately: Set HCR_EL2 617 * field to match SCR_EL3.RW. 618 */ 619 if ((scr_el3 & SCR_RW_BIT) != 0U) 620 hcr_el2 |= HCR_RW_BIT; 621 622 /* 623 * For Armv8.3 pointer authentication feature, disable 624 * traps to EL2 when accessing key registers or using 625 * pointer authentication instructions from lower ELs. 626 */ 627 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 628 629 write_hcr_el2(hcr_el2); 630 631 /* 632 * Initialise CPTR_EL2 setting all fields rather than 633 * relying on the hw. All fields have architecturally 634 * UNKNOWN reset values. 635 * 636 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 637 * accesses to the CPACR_EL1 or CPACR from both 638 * Execution states do not trap to EL2. 639 * 640 * CPTR_EL2.TTA: Set to zero so that Non-secure System 641 * register accesses to the trace registers from both 642 * Execution states do not trap to EL2. 643 * If PE trace unit System registers are not implemented 644 * then this bit is reserved, and must be set to zero. 645 * 646 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 647 * to SIMD and floating-point functionality from both 648 * Execution states do not trap to EL2. 649 */ 650 write_cptr_el2(CPTR_EL2_RESET_VAL & 651 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 652 | CPTR_EL2_TFP_BIT)); 653 654 /* 655 * Initialise CNTHCTL_EL2. All fields are 656 * architecturally UNKNOWN on reset and are set to zero 657 * except for field(s) listed below. 658 * 659 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 660 * Hyp mode of Non-secure EL0 and EL1 accesses to the 661 * physical timer registers. 662 * 663 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 664 * Hyp mode of Non-secure EL0 and EL1 accesses to the 665 * physical counter registers. 666 */ 667 write_cnthctl_el2(CNTHCTL_RESET_VAL | 668 EL1PCEN_BIT | EL1PCTEN_BIT); 669 670 /* 671 * Initialise CNTVOFF_EL2 to zero as it resets to an 672 * architecturally UNKNOWN value. 673 */ 674 write_cntvoff_el2(0); 675 676 /* 677 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 678 * MPIDR_EL1 respectively. 679 */ 680 write_vpidr_el2(read_midr_el1()); 681 write_vmpidr_el2(read_mpidr_el1()); 682 683 /* 684 * Initialise VTTBR_EL2. All fields are architecturally 685 * UNKNOWN on reset. 686 * 687 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 688 * 2 address translation is disabled, cache maintenance 689 * operations depend on the VMID. 690 * 691 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 692 * translation is disabled. 693 */ 694 write_vttbr_el2(VTTBR_RESET_VAL & 695 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 696 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 697 698 /* 699 * Initialise MDCR_EL2, setting all fields rather than 700 * relying on hw. Some fields are architecturally 701 * UNKNOWN on reset. 702 * 703 * MDCR_EL2.HLP: Set to one so that event counter 704 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 705 * occurs on the increment that changes 706 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 707 * implemented. This bit is RES0 in versions of the 708 * architecture earlier than ARMv8.5, setting it to 1 709 * doesn't have any effect on them. 710 * 711 * MDCR_EL2.TTRF: Set to zero so that access to Trace 712 * Filter Control register TRFCR_EL1 at EL1 is not 713 * trapped to EL2. This bit is RES0 in versions of 714 * the architecture earlier than ARMv8.4. 715 * 716 * MDCR_EL2.HPMD: Set to one so that event counting is 717 * prohibited at EL2. This bit is RES0 in versions of 718 * the architecture earlier than ARMv8.1, setting it 719 * to 1 doesn't have any effect on them. 720 * 721 * MDCR_EL2.TPMS: Set to zero so that accesses to 722 * Statistical Profiling control registers from EL1 723 * do not trap to EL2. This bit is RES0 when SPE is 724 * not implemented. 725 * 726 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 727 * EL1 System register accesses to the Debug ROM 728 * registers are not trapped to EL2. 729 * 730 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 731 * System register accesses to the powerdown debug 732 * registers are not trapped to EL2. 733 * 734 * MDCR_EL2.TDA: Set to zero so that System register 735 * accesses to the debug registers do not trap to EL2. 736 * 737 * MDCR_EL2.TDE: Set to zero so that debug exceptions 738 * are not routed to EL2. 739 * 740 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 741 * Monitors. 742 * 743 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 744 * EL1 accesses to all Performance Monitors registers 745 * are not trapped to EL2. 746 * 747 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 748 * and EL1 accesses to the PMCR_EL0 or PMCR are not 749 * trapped to EL2. 750 * 751 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 752 * architecturally-defined reset value. 753 * 754 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 755 * owning exception level is NS-EL1 and, tracing is 756 * prohibited at NS-EL2. These bits are RES0 when 757 * FEAT_TRBE is not implemented. 758 */ 759 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 760 MDCR_EL2_HPMD) | 761 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 762 >> PMCR_EL0_N_SHIFT)) & 763 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 764 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 765 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 766 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 767 MDCR_EL2_TPMCR_BIT | 768 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 769 770 write_mdcr_el2(mdcr_el2); 771 772 /* 773 * Initialise HSTR_EL2. All fields are architecturally 774 * UNKNOWN on reset. 775 * 776 * HSTR_EL2.T<n>: Set all these fields to zero so that 777 * Non-secure EL0 or EL1 accesses to System registers 778 * do not trap to EL2. 779 */ 780 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 781 /* 782 * Initialise CNTHP_CTL_EL2. All fields are 783 * architecturally UNKNOWN on reset. 784 * 785 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 786 * physical timer and prevent timer interrupts. 787 */ 788 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 789 ~(CNTHP_CTL_ENABLE_BIT)); 790 } 791 manage_extensions_nonsecure(el2_unused, ctx); 792 } 793 794 cm_el1_sysregs_context_restore(security_state); 795 cm_set_next_eret_context(security_state); 796 } 797 798 #if CTX_INCLUDE_EL2_REGS 799 /******************************************************************************* 800 * Save EL2 sysreg context 801 ******************************************************************************/ 802 void cm_el2_sysregs_context_save(uint32_t security_state) 803 { 804 u_register_t scr_el3 = read_scr(); 805 806 /* 807 * Always save the non-secure and realm EL2 context, only save the 808 * S-EL2 context if S-EL2 is enabled. 809 */ 810 if ((security_state != SECURE) || 811 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 812 cpu_context_t *ctx; 813 el2_sysregs_t *el2_sysregs_ctx; 814 815 ctx = cm_get_context(security_state); 816 assert(ctx != NULL); 817 818 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 819 820 el2_sysregs_context_save_common(el2_sysregs_ctx); 821 #if ENABLE_SPE_FOR_LOWER_ELS 822 el2_sysregs_context_save_spe(el2_sysregs_ctx); 823 #endif 824 #if CTX_INCLUDE_MTE_REGS 825 el2_sysregs_context_save_mte(el2_sysregs_ctx); 826 #endif 827 #if ENABLE_MPAM_FOR_LOWER_ELS 828 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 829 #endif 830 #if ENABLE_FEAT_FGT 831 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 832 #endif 833 #if ENABLE_FEAT_ECV 834 el2_sysregs_context_save_ecv(el2_sysregs_ctx); 835 #endif 836 #if ENABLE_FEAT_VHE 837 el2_sysregs_context_save_vhe(el2_sysregs_ctx); 838 #endif 839 #if RAS_EXTENSION 840 el2_sysregs_context_save_ras(el2_sysregs_ctx); 841 #endif 842 #if CTX_INCLUDE_NEVE_REGS 843 el2_sysregs_context_save_nv2(el2_sysregs_ctx); 844 #endif 845 #if ENABLE_TRF_FOR_NS 846 el2_sysregs_context_save_trf(el2_sysregs_ctx); 847 #endif 848 #if ENABLE_FEAT_CSV2_2 849 el2_sysregs_context_save_csv2(el2_sysregs_ctx); 850 #endif 851 #if ENABLE_FEAT_HCX 852 el2_sysregs_context_save_hcx(el2_sysregs_ctx); 853 #endif 854 } 855 } 856 857 /******************************************************************************* 858 * Restore EL2 sysreg context 859 ******************************************************************************/ 860 void cm_el2_sysregs_context_restore(uint32_t security_state) 861 { 862 u_register_t scr_el3 = read_scr(); 863 864 /* 865 * Always restore the non-secure and realm EL2 context, only restore the 866 * S-EL2 context if S-EL2 is enabled. 867 */ 868 if ((security_state != SECURE) || 869 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 870 cpu_context_t *ctx; 871 el2_sysregs_t *el2_sysregs_ctx; 872 873 ctx = cm_get_context(security_state); 874 assert(ctx != NULL); 875 876 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 877 878 el2_sysregs_context_restore_common(el2_sysregs_ctx); 879 #if ENABLE_SPE_FOR_LOWER_ELS 880 el2_sysregs_context_restore_spe(el2_sysregs_ctx); 881 #endif 882 #if CTX_INCLUDE_MTE_REGS 883 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 884 #endif 885 #if ENABLE_MPAM_FOR_LOWER_ELS 886 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 887 #endif 888 #if ENABLE_FEAT_FGT 889 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 890 #endif 891 #if ENABLE_FEAT_ECV 892 el2_sysregs_context_restore_ecv(el2_sysregs_ctx); 893 #endif 894 #if ENABLE_FEAT_VHE 895 el2_sysregs_context_restore_vhe(el2_sysregs_ctx); 896 #endif 897 #if RAS_EXTENSION 898 el2_sysregs_context_restore_ras(el2_sysregs_ctx); 899 #endif 900 #if CTX_INCLUDE_NEVE_REGS 901 el2_sysregs_context_restore_nv2(el2_sysregs_ctx); 902 #endif 903 #if ENABLE_TRF_FOR_NS 904 el2_sysregs_context_restore_trf(el2_sysregs_ctx); 905 #endif 906 #if ENABLE_FEAT_CSV2_2 907 el2_sysregs_context_restore_csv2(el2_sysregs_ctx); 908 #endif 909 #if ENABLE_FEAT_HCX 910 el2_sysregs_context_restore_hcx(el2_sysregs_ctx); 911 #endif 912 } 913 } 914 #endif /* CTX_INCLUDE_EL2_REGS */ 915 916 /******************************************************************************* 917 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 918 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 919 * updating EL1 and EL2 registers. Otherwise, it calls the generic 920 * cm_prepare_el3_exit function. 921 ******************************************************************************/ 922 void cm_prepare_el3_exit_ns(void) 923 { 924 #if CTX_INCLUDE_EL2_REGS 925 cpu_context_t *ctx = cm_get_context(NON_SECURE); 926 assert(ctx != NULL); 927 928 /* Assert that EL2 is used. */ 929 #if ENABLE_ASSERTIONS 930 el3_state_t *state = get_el3state_ctx(ctx); 931 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 932 #endif 933 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 934 (el_implemented(2U) != EL_IMPL_NONE)); 935 936 /* 937 * Currently some extensions are configured using 938 * direct register updates. Therefore, do this here 939 * instead of when setting up context. 940 */ 941 manage_extensions_nonsecure(0, ctx); 942 943 /* 944 * Set the NS bit to be able to access the ICC_SRE_EL2 945 * register when restoring context. 946 */ 947 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 948 949 /* 950 * Ensure the NS bit change is committed before the EL2/EL1 951 * state restoration. 952 */ 953 isb(); 954 955 /* Restore EL2 and EL1 sysreg contexts */ 956 cm_el2_sysregs_context_restore(NON_SECURE); 957 cm_el1_sysregs_context_restore(NON_SECURE); 958 cm_set_next_eret_context(NON_SECURE); 959 #else 960 cm_prepare_el3_exit(NON_SECURE); 961 #endif /* CTX_INCLUDE_EL2_REGS */ 962 } 963 964 /******************************************************************************* 965 * The next four functions are used by runtime services to save and restore 966 * EL1 context on the 'cpu_context' structure for the specified security 967 * state. 968 ******************************************************************************/ 969 void cm_el1_sysregs_context_save(uint32_t security_state) 970 { 971 cpu_context_t *ctx; 972 973 ctx = cm_get_context(security_state); 974 assert(ctx != NULL); 975 976 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 977 978 #if IMAGE_BL31 979 if (security_state == SECURE) 980 PUBLISH_EVENT(cm_exited_secure_world); 981 else 982 PUBLISH_EVENT(cm_exited_normal_world); 983 #endif 984 } 985 986 void cm_el1_sysregs_context_restore(uint32_t security_state) 987 { 988 cpu_context_t *ctx; 989 990 ctx = cm_get_context(security_state); 991 assert(ctx != NULL); 992 993 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 994 995 #if IMAGE_BL31 996 if (security_state == SECURE) 997 PUBLISH_EVENT(cm_entering_secure_world); 998 else 999 PUBLISH_EVENT(cm_entering_normal_world); 1000 #endif 1001 } 1002 1003 /******************************************************************************* 1004 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1005 * given security state with the given entrypoint 1006 ******************************************************************************/ 1007 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1008 { 1009 cpu_context_t *ctx; 1010 el3_state_t *state; 1011 1012 ctx = cm_get_context(security_state); 1013 assert(ctx != NULL); 1014 1015 /* Populate EL3 state so that ERET jumps to the correct entry */ 1016 state = get_el3state_ctx(ctx); 1017 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1018 } 1019 1020 /******************************************************************************* 1021 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1022 * pertaining to the given security state 1023 ******************************************************************************/ 1024 void cm_set_elr_spsr_el3(uint32_t security_state, 1025 uintptr_t entrypoint, uint32_t spsr) 1026 { 1027 cpu_context_t *ctx; 1028 el3_state_t *state; 1029 1030 ctx = cm_get_context(security_state); 1031 assert(ctx != NULL); 1032 1033 /* Populate EL3 state so that ERET jumps to the correct entry */ 1034 state = get_el3state_ctx(ctx); 1035 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1036 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1037 } 1038 1039 /******************************************************************************* 1040 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1041 * pertaining to the given security state using the value and bit position 1042 * specified in the parameters. It preserves all other bits. 1043 ******************************************************************************/ 1044 void cm_write_scr_el3_bit(uint32_t security_state, 1045 uint32_t bit_pos, 1046 uint32_t value) 1047 { 1048 cpu_context_t *ctx; 1049 el3_state_t *state; 1050 u_register_t scr_el3; 1051 1052 ctx = cm_get_context(security_state); 1053 assert(ctx != NULL); 1054 1055 /* Ensure that the bit position is a valid one */ 1056 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1057 1058 /* Ensure that the 'value' is only a bit wide */ 1059 assert(value <= 1U); 1060 1061 /* 1062 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1063 * and set it to its new value. 1064 */ 1065 state = get_el3state_ctx(ctx); 1066 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1067 scr_el3 &= ~(1UL << bit_pos); 1068 scr_el3 |= (u_register_t)value << bit_pos; 1069 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1070 } 1071 1072 /******************************************************************************* 1073 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1074 * given security state. 1075 ******************************************************************************/ 1076 u_register_t cm_get_scr_el3(uint32_t security_state) 1077 { 1078 cpu_context_t *ctx; 1079 el3_state_t *state; 1080 1081 ctx = cm_get_context(security_state); 1082 assert(ctx != NULL); 1083 1084 /* Populate EL3 state so that ERET jumps to the correct entry */ 1085 state = get_el3state_ctx(ctx); 1086 return read_ctx_reg(state, CTX_SCR_EL3); 1087 } 1088 1089 /******************************************************************************* 1090 * This function is used to program the context that's used for exception 1091 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1092 * the required security state 1093 ******************************************************************************/ 1094 void cm_set_next_eret_context(uint32_t security_state) 1095 { 1096 cpu_context_t *ctx; 1097 1098 ctx = cm_get_context(security_state); 1099 assert(ctx != NULL); 1100 1101 cm_set_next_context(ctx); 1102 } 1103