1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <amu.h> 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <bl_common.h> 12 #include <context.h> 13 #include <context_mgmt.h> 14 #include <interrupt_mgmt.h> 15 #include <platform.h> 16 #include <platform_def.h> 17 #include <pubsub_events.h> 18 #include <smcc_helpers.h> 19 #include <spe.h> 20 #include <string.h> 21 #include <sve.h> 22 #include <utils.h> 23 24 25 /******************************************************************************* 26 * Context management library initialisation routine. This library is used by 27 * runtime services to share pointers to 'cpu_context' structures for the secure 28 * and non-secure states. Management of the structures and their associated 29 * memory is not done by the context management library e.g. the PSCI service 30 * manages the cpu context used for entry from and exit to the non-secure state. 31 * The Secure payload dispatcher service manages the context(s) corresponding to 32 * the secure state. It also uses this library to get access to the non-secure 33 * state cpu context pointers. 34 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 35 * which will used for programming an entry into a lower EL. The same context 36 * will used to save state upon exception entry from that EL. 37 ******************************************************************************/ 38 void cm_init(void) 39 { 40 /* 41 * The context management library has only global data to intialize, but 42 * that will be done when the BSS is zeroed out 43 */ 44 } 45 46 /******************************************************************************* 47 * The following function initializes the cpu_context 'ctx' for 48 * first use, and sets the initial entrypoint state as specified by the 49 * entry_point_info structure. 50 * 51 * The security state to initialize is determined by the SECURE attribute 52 * of the entry_point_info. The function returns a pointer to the initialized 53 * context and sets this as the next context to return to. 54 * 55 * The EE and ST attributes are used to configure the endianess and secure 56 * timer availability for the new execution context. 57 * 58 * To prepare the register state for entry call cm_prepare_el3_exit() and 59 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 60 * cm_e1_sysreg_context_restore(). 61 ******************************************************************************/ 62 static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 63 { 64 unsigned int security_state; 65 uint32_t scr_el3, pmcr_el0; 66 el3_state_t *state; 67 gp_regs_t *gp_regs; 68 unsigned long sctlr_elx; 69 70 assert(ctx); 71 72 security_state = GET_SECURITY_STATE(ep->h.attr); 73 74 /* Clear any residual register values from the context */ 75 zeromem(ctx, sizeof(*ctx)); 76 77 /* 78 * SCR_EL3 was initialised during reset sequence in macro 79 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 80 * affect the next EL. 81 * 82 * The following fields are initially set to zero and then updated to 83 * the required value depending on the state of the SPSR_EL3 and the 84 * Security state and entrypoint attributes of the next EL. 85 */ 86 scr_el3 = read_scr(); 87 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 88 SCR_ST_BIT | SCR_HCE_BIT); 89 /* 90 * SCR_NS: Set the security state of the next EL. 91 */ 92 if (security_state != SECURE) 93 scr_el3 |= SCR_NS_BIT; 94 /* 95 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 96 * Exception level as specified by SPSR. 97 */ 98 if (GET_RW(ep->spsr) == MODE_RW_64) 99 scr_el3 |= SCR_RW_BIT; 100 /* 101 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 102 * Secure timer registers to EL3, from AArch64 state only, if specified 103 * by the entrypoint attributes. 104 */ 105 if (EP_GET_ST(ep->h.attr)) 106 scr_el3 |= SCR_ST_BIT; 107 108 #ifndef HANDLE_EA_EL3_FIRST 109 /* 110 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 111 * to EL3 when executing at a lower EL. When executing at EL3, External 112 * Aborts are taken to EL3. 113 */ 114 scr_el3 &= ~SCR_EA_BIT; 115 #endif 116 117 #ifdef IMAGE_BL31 118 /* 119 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ rounting as 120 * indicated by the interrupt routing model for BL31. 121 */ 122 scr_el3 |= get_scr_el3_from_routing_model(security_state); 123 #endif 124 125 /* 126 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 127 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 128 * next mode is Hyp. 129 */ 130 if ((GET_RW(ep->spsr) == MODE_RW_64 131 && GET_EL(ep->spsr) == MODE_EL2) 132 || (GET_RW(ep->spsr) != MODE_RW_64 133 && GET_M32(ep->spsr) == MODE32_hyp)) { 134 scr_el3 |= SCR_HCE_BIT; 135 } 136 137 /* 138 * Initialise SCTLR_EL1 to the reset value corresponding to the target 139 * execution state setting all fields rather than relying of the hw. 140 * Some fields have architecturally UNKNOWN reset values and these are 141 * set to zero. 142 * 143 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 144 * 145 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 146 * required by PSCI specification) 147 */ 148 sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; 149 if (GET_RW(ep->spsr) == MODE_RW_64) 150 sctlr_elx |= SCTLR_EL1_RES1; 151 else { 152 /* 153 * If the target execution state is AArch32 then the following 154 * fields need to be set. 155 * 156 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 157 * instructions are not trapped to EL1. 158 * 159 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 160 * instructions are not trapped to EL1. 161 * 162 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 163 * CP15DMB, CP15DSB, and CP15ISB instructions. 164 */ 165 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 166 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 167 } 168 169 /* 170 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 171 * and other EL2 registers are set up by cm_preapre_ns_entry() as they 172 * are not part of the stored cpu_context. 173 */ 174 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 175 176 if (security_state == SECURE) { 177 /* 178 * Initialise PMCR_EL0 for secure context only, setting all 179 * fields rather than relying on hw. Some fields are 180 * architecturally UNKNOWN on reset. 181 * 182 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 183 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 184 * that changes PMCCNTR_EL0[63] from 1 to 0. 185 * 186 * PMCR_EL0.DP: Set to one so that the cycle counter, 187 * PMCCNTR_EL0 does not count when event counting is prohibited. 188 * 189 * PMCR_EL0.X: Set to zero to disable export of events. 190 * 191 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 192 * counts on every clock cycle. 193 */ 194 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT 195 | PMCR_EL0_DP_BIT) 196 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)); 197 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0); 198 } 199 200 /* Populate EL3 state so that we've the right context before doing ERET */ 201 state = get_el3state_ctx(ctx); 202 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 203 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 204 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 205 206 /* 207 * Store the X0-X7 value from the entrypoint into the context 208 * Use memcpy as we are in control of the layout of the structures 209 */ 210 gp_regs = get_gpregs_ctx(ctx); 211 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 212 } 213 214 /******************************************************************************* 215 * Enable architecture extensions on first entry to Non-secure world. 216 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 217 * it is zero. 218 ******************************************************************************/ 219 static void enable_extensions_nonsecure(int el2_unused) 220 { 221 #if IMAGE_BL31 222 #if ENABLE_SPE_FOR_LOWER_ELS 223 spe_enable(el2_unused); 224 #endif 225 226 #if ENABLE_AMU 227 amu_enable(el2_unused); 228 #endif 229 230 #if ENABLE_SVE_FOR_NS 231 sve_enable(el2_unused); 232 #endif 233 #endif 234 } 235 236 /******************************************************************************* 237 * The following function initializes the cpu_context for a CPU specified by 238 * its `cpu_idx` for first use, and sets the initial entrypoint state as 239 * specified by the entry_point_info structure. 240 ******************************************************************************/ 241 void cm_init_context_by_index(unsigned int cpu_idx, 242 const entry_point_info_t *ep) 243 { 244 cpu_context_t *ctx; 245 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 246 cm_init_context_common(ctx, ep); 247 } 248 249 /******************************************************************************* 250 * The following function initializes the cpu_context for the current CPU 251 * for first use, and sets the initial entrypoint state as specified by the 252 * entry_point_info structure. 253 ******************************************************************************/ 254 void cm_init_my_context(const entry_point_info_t *ep) 255 { 256 cpu_context_t *ctx; 257 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 258 cm_init_context_common(ctx, ep); 259 } 260 261 /******************************************************************************* 262 * Prepare the CPU system registers for first entry into secure or normal world 263 * 264 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 265 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 266 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 267 * For all entries, the EL1 registers are initialized from the cpu_context 268 ******************************************************************************/ 269 void cm_prepare_el3_exit(uint32_t security_state) 270 { 271 uint32_t sctlr_elx, scr_el3, mdcr_el2; 272 cpu_context_t *ctx = cm_get_context(security_state); 273 int el2_unused = 0; 274 275 assert(ctx); 276 277 if (security_state == NON_SECURE) { 278 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 279 if (scr_el3 & SCR_HCE_BIT) { 280 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 281 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), 282 CTX_SCTLR_EL1); 283 sctlr_elx &= SCTLR_EE_BIT; 284 sctlr_elx |= SCTLR_EL2_RES1; 285 write_sctlr_el2(sctlr_elx); 286 } else if (EL_IMPLEMENTED(2)) { 287 el2_unused = 1; 288 289 /* 290 * EL2 present but unused, need to disable safely. 291 * SCTLR_EL2 can be ignored in this case. 292 * 293 * Initialise all fields in HCR_EL2, except HCR_EL2.RW, 294 * to zero so that Non-secure operations do not trap to 295 * EL2. 296 * 297 * HCR_EL2.RW: Set this field to match SCR_EL3.RW 298 */ 299 write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0); 300 301 /* 302 * Initialise CPTR_EL2 setting all fields rather than 303 * relying on the hw. All fields have architecturally 304 * UNKNOWN reset values. 305 * 306 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 307 * accesses to the CPACR_EL1 or CPACR from both 308 * Execution states do not trap to EL2. 309 * 310 * CPTR_EL2.TTA: Set to zero so that Non-secure System 311 * register accesses to the trace registers from both 312 * Execution states do not trap to EL2. 313 * 314 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 315 * to SIMD and floating-point functionality from both 316 * Execution states do not trap to EL2. 317 */ 318 write_cptr_el2(CPTR_EL2_RESET_VAL & 319 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 320 | CPTR_EL2_TFP_BIT)); 321 322 /* 323 * Initiliase CNTHCTL_EL2. All fields are 324 * architecturally UNKNOWN on reset and are set to zero 325 * except for field(s) listed below. 326 * 327 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 328 * Hyp mode of Non-secure EL0 and EL1 accesses to the 329 * physical timer registers. 330 * 331 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 332 * Hyp mode of Non-secure EL0 and EL1 accesses to the 333 * physical counter registers. 334 */ 335 write_cnthctl_el2(CNTHCTL_RESET_VAL | 336 EL1PCEN_BIT | EL1PCTEN_BIT); 337 338 /* 339 * Initialise CNTVOFF_EL2 to zero as it resets to an 340 * architecturally UNKNOWN value. 341 */ 342 write_cntvoff_el2(0); 343 344 /* 345 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 346 * MPIDR_EL1 respectively. 347 */ 348 write_vpidr_el2(read_midr_el1()); 349 write_vmpidr_el2(read_mpidr_el1()); 350 351 /* 352 * Initialise VTTBR_EL2. All fields are architecturally 353 * UNKNOWN on reset. 354 * 355 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 356 * 2 address translation is disabled, cache maintenance 357 * operations depend on the VMID. 358 * 359 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 360 * translation is disabled. 361 */ 362 write_vttbr_el2(VTTBR_RESET_VAL & 363 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 364 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 365 366 /* 367 * Initialise MDCR_EL2, setting all fields rather than 368 * relying on hw. Some fields are architecturally 369 * UNKNOWN on reset. 370 * 371 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 372 * EL1 System register accesses to the Debug ROM 373 * registers are not trapped to EL2. 374 * 375 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 376 * System register accesses to the powerdown debug 377 * registers are not trapped to EL2. 378 * 379 * MDCR_EL2.TDA: Set to zero so that System register 380 * accesses to the debug registers do not trap to EL2. 381 * 382 * MDCR_EL2.TDE: Set to zero so that debug exceptions 383 * are not routed to EL2. 384 * 385 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 386 * Monitors. 387 * 388 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 389 * EL1 accesses to all Performance Monitors registers 390 * are not trapped to EL2. 391 * 392 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 393 * and EL1 accesses to the PMCR_EL0 or PMCR are not 394 * trapped to EL2. 395 * 396 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 397 * architecturally-defined reset value. 398 */ 399 mdcr_el2 = ((MDCR_EL2_RESET_VAL | 400 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 401 >> PMCR_EL0_N_SHIFT)) & 402 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT 403 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT 404 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT 405 | MDCR_EL2_TPMCR_BIT)); 406 407 write_mdcr_el2(mdcr_el2); 408 409 /* 410 * Initialise HSTR_EL2. All fields are architecturally 411 * UNKNOWN on reset. 412 * 413 * HSTR_EL2.T<n>: Set all these fields to zero so that 414 * Non-secure EL0 or EL1 accesses to System registers 415 * do not trap to EL2. 416 */ 417 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 418 /* 419 * Initialise CNTHP_CTL_EL2. All fields are 420 * architecturally UNKNOWN on reset. 421 * 422 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 423 * physical timer and prevent timer interrupts. 424 */ 425 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 426 ~(CNTHP_CTL_ENABLE_BIT)); 427 } 428 enable_extensions_nonsecure(el2_unused); 429 } 430 431 cm_el1_sysregs_context_restore(security_state); 432 cm_set_next_eret_context(security_state); 433 } 434 435 /******************************************************************************* 436 * The next four functions are used by runtime services to save and restore 437 * EL1 context on the 'cpu_context' structure for the specified security 438 * state. 439 ******************************************************************************/ 440 void cm_el1_sysregs_context_save(uint32_t security_state) 441 { 442 cpu_context_t *ctx; 443 444 ctx = cm_get_context(security_state); 445 assert(ctx); 446 447 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 448 449 #if IMAGE_BL31 450 if (security_state == SECURE) 451 PUBLISH_EVENT(cm_exited_secure_world); 452 else 453 PUBLISH_EVENT(cm_exited_normal_world); 454 #endif 455 } 456 457 void cm_el1_sysregs_context_restore(uint32_t security_state) 458 { 459 cpu_context_t *ctx; 460 461 ctx = cm_get_context(security_state); 462 assert(ctx); 463 464 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 465 466 #if IMAGE_BL31 467 if (security_state == SECURE) 468 PUBLISH_EVENT(cm_entering_secure_world); 469 else 470 PUBLISH_EVENT(cm_entering_normal_world); 471 #endif 472 } 473 474 /******************************************************************************* 475 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 476 * given security state with the given entrypoint 477 ******************************************************************************/ 478 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 479 { 480 cpu_context_t *ctx; 481 el3_state_t *state; 482 483 ctx = cm_get_context(security_state); 484 assert(ctx); 485 486 /* Populate EL3 state so that ERET jumps to the correct entry */ 487 state = get_el3state_ctx(ctx); 488 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 489 } 490 491 /******************************************************************************* 492 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 493 * pertaining to the given security state 494 ******************************************************************************/ 495 void cm_set_elr_spsr_el3(uint32_t security_state, 496 uintptr_t entrypoint, uint32_t spsr) 497 { 498 cpu_context_t *ctx; 499 el3_state_t *state; 500 501 ctx = cm_get_context(security_state); 502 assert(ctx); 503 504 /* Populate EL3 state so that ERET jumps to the correct entry */ 505 state = get_el3state_ctx(ctx); 506 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 507 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 508 } 509 510 /******************************************************************************* 511 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 512 * pertaining to the given security state using the value and bit position 513 * specified in the parameters. It preserves all other bits. 514 ******************************************************************************/ 515 void cm_write_scr_el3_bit(uint32_t security_state, 516 uint32_t bit_pos, 517 uint32_t value) 518 { 519 cpu_context_t *ctx; 520 el3_state_t *state; 521 uint32_t scr_el3; 522 523 ctx = cm_get_context(security_state); 524 assert(ctx); 525 526 /* Ensure that the bit position is a valid one */ 527 assert((1 << bit_pos) & SCR_VALID_BIT_MASK); 528 529 /* Ensure that the 'value' is only a bit wide */ 530 assert(value <= 1); 531 532 /* 533 * Get the SCR_EL3 value from the cpu context, clear the desired bit 534 * and set it to its new value. 535 */ 536 state = get_el3state_ctx(ctx); 537 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 538 scr_el3 &= ~(1 << bit_pos); 539 scr_el3 |= value << bit_pos; 540 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 541 } 542 543 /******************************************************************************* 544 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 545 * given security state. 546 ******************************************************************************/ 547 uint32_t cm_get_scr_el3(uint32_t security_state) 548 { 549 cpu_context_t *ctx; 550 el3_state_t *state; 551 552 ctx = cm_get_context(security_state); 553 assert(ctx); 554 555 /* Populate EL3 state so that ERET jumps to the correct entry */ 556 state = get_el3state_ctx(ctx); 557 return read_ctx_reg(state, CTX_SCR_EL3); 558 } 559 560 /******************************************************************************* 561 * This function is used to program the context that's used for exception 562 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 563 * the required security state 564 ******************************************************************************/ 565 void cm_set_next_eret_context(uint32_t security_state) 566 { 567 cpu_context_t *ctx; 568 569 ctx = cm_get_context(security_state); 570 assert(ctx); 571 572 cm_set_next_context(ctx); 573 } 574