1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <bl31/interrupt_mgmt.h> 16 #include <common/bl_common.h> 17 #include <context.h> 18 #include <lib/el3_runtime/context_mgmt.h> 19 #include <lib/el3_runtime/pubsub_events.h> 20 #include <lib/extensions/amu.h> 21 #include <lib/extensions/mpam.h> 22 #include <lib/extensions/spe.h> 23 #include <lib/extensions/sve.h> 24 #include <lib/utils.h> 25 #include <plat/common/platform.h> 26 #include <smccc_helpers.h> 27 28 29 /******************************************************************************* 30 * Context management library initialisation routine. This library is used by 31 * runtime services to share pointers to 'cpu_context' structures for the secure 32 * and non-secure states. Management of the structures and their associated 33 * memory is not done by the context management library e.g. the PSCI service 34 * manages the cpu context used for entry from and exit to the non-secure state. 35 * The Secure payload dispatcher service manages the context(s) corresponding to 36 * the secure state. It also uses this library to get access to the non-secure 37 * state cpu context pointers. 38 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 39 * which will used for programming an entry into a lower EL. The same context 40 * will used to save state upon exception entry from that EL. 41 ******************************************************************************/ 42 void __init cm_init(void) 43 { 44 /* 45 * The context management library has only global data to intialize, but 46 * that will be done when the BSS is zeroed out 47 */ 48 } 49 50 /******************************************************************************* 51 * The following function initializes the cpu_context 'ctx' for 52 * first use, and sets the initial entrypoint state as specified by the 53 * entry_point_info structure. 54 * 55 * The security state to initialize is determined by the SECURE attribute 56 * of the entry_point_info. 57 * 58 * The EE and ST attributes are used to configure the endianness and secure 59 * timer availability for the new execution context. 60 * 61 * To prepare the register state for entry call cm_prepare_el3_exit() and 62 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 63 * cm_e1_sysreg_context_restore(). 64 ******************************************************************************/ 65 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 66 { 67 unsigned int security_state; 68 uint32_t scr_el3, pmcr_el0; 69 el3_state_t *state; 70 gp_regs_t *gp_regs; 71 unsigned long sctlr_elx, actlr_elx; 72 73 assert(ctx != NULL); 74 75 security_state = GET_SECURITY_STATE(ep->h.attr); 76 77 /* Clear any residual register values from the context */ 78 zeromem(ctx, sizeof(*ctx)); 79 80 /* 81 * SCR_EL3 was initialised during reset sequence in macro 82 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 83 * affect the next EL. 84 * 85 * The following fields are initially set to zero and then updated to 86 * the required value depending on the state of the SPSR_EL3 and the 87 * Security state and entrypoint attributes of the next EL. 88 */ 89 scr_el3 = (uint32_t)read_scr(); 90 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 91 SCR_ST_BIT | SCR_HCE_BIT); 92 /* 93 * SCR_NS: Set the security state of the next EL. 94 */ 95 if (security_state != SECURE) 96 scr_el3 |= SCR_NS_BIT; 97 /* 98 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 99 * Exception level as specified by SPSR. 100 */ 101 if (GET_RW(ep->spsr) == MODE_RW_64) 102 scr_el3 |= SCR_RW_BIT; 103 /* 104 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 105 * Secure timer registers to EL3, from AArch64 state only, if specified 106 * by the entrypoint attributes. 107 */ 108 if (EP_GET_ST(ep->h.attr) != 0U) 109 scr_el3 |= SCR_ST_BIT; 110 111 #if !HANDLE_EA_EL3_FIRST 112 /* 113 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 114 * to EL3 when executing at a lower EL. When executing at EL3, External 115 * Aborts are taken to EL3. 116 */ 117 scr_el3 &= ~SCR_EA_BIT; 118 #endif 119 120 #if FAULT_INJECTION_SUPPORT 121 /* Enable fault injection from lower ELs */ 122 scr_el3 |= SCR_FIEN_BIT; 123 #endif 124 125 #if !CTX_INCLUDE_PAUTH_REGS 126 /* 127 * If the pointer authentication registers aren't saved during world 128 * switches the value of the registers can be leaked from the Secure to 129 * the Non-secure world. To prevent this, rather than enabling pointer 130 * authentication everywhere, we only enable it in the Non-secure world. 131 * 132 * If the Secure world wants to use pointer authentication, 133 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 134 */ 135 if (security_state == NON_SECURE) 136 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 137 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 138 139 #ifdef IMAGE_BL31 140 /* 141 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 142 * indicated by the interrupt routing model for BL31. 143 */ 144 scr_el3 |= get_scr_el3_from_routing_model(security_state); 145 #endif 146 147 /* 148 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 149 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 150 * next mode is Hyp. 151 */ 152 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 153 || ((GET_RW(ep->spsr) != MODE_RW_64) 154 && (GET_M32(ep->spsr) == MODE32_hyp))) { 155 scr_el3 |= SCR_HCE_BIT; 156 } 157 158 /* 159 * Initialise SCTLR_EL1 to the reset value corresponding to the target 160 * execution state setting all fields rather than relying of the hw. 161 * Some fields have architecturally UNKNOWN reset values and these are 162 * set to zero. 163 * 164 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 165 * 166 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 167 * required by PSCI specification) 168 */ 169 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 170 if (GET_RW(ep->spsr) == MODE_RW_64) 171 sctlr_elx |= SCTLR_EL1_RES1; 172 else { 173 /* 174 * If the target execution state is AArch32 then the following 175 * fields need to be set. 176 * 177 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 178 * instructions are not trapped to EL1. 179 * 180 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 181 * instructions are not trapped to EL1. 182 * 183 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 184 * CP15DMB, CP15DSB, and CP15ISB instructions. 185 */ 186 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 187 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 188 } 189 190 /* 191 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 192 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 193 * are not part of the stored cpu_context. 194 */ 195 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 196 197 /* 198 * Base the context ACTLR_EL1 on the current value, as it is 199 * implementation defined. The context restore process will write 200 * the value from the context to the actual register and can cause 201 * problems for processor cores that don't expect certain bits to 202 * be zero. 203 */ 204 actlr_elx = read_actlr_el1(); 205 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 206 207 if (security_state == SECURE) { 208 /* 209 * Initialise PMCR_EL0 for secure context only, setting all 210 * fields rather than relying on hw. Some fields are 211 * architecturally UNKNOWN on reset. 212 * 213 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 214 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 215 * that changes PMCCNTR_EL0[63] from 1 to 0. 216 * 217 * PMCR_EL0.DP: Set to one so that the cycle counter, 218 * PMCCNTR_EL0 does not count when event counting is prohibited. 219 * 220 * PMCR_EL0.X: Set to zero to disable export of events. 221 * 222 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 223 * counts on every clock cycle. 224 */ 225 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT 226 | PMCR_EL0_DP_BIT) 227 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)); 228 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0); 229 } 230 231 /* Populate EL3 state so that we've the right context before doing ERET */ 232 state = get_el3state_ctx(ctx); 233 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 234 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 235 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 236 237 /* 238 * Store the X0-X7 value from the entrypoint into the context 239 * Use memcpy as we are in control of the layout of the structures 240 */ 241 gp_regs = get_gpregs_ctx(ctx); 242 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 243 } 244 245 /******************************************************************************* 246 * Enable architecture extensions on first entry to Non-secure world. 247 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 248 * it is zero. 249 ******************************************************************************/ 250 static void enable_extensions_nonsecure(bool el2_unused) 251 { 252 #if IMAGE_BL31 253 #if ENABLE_SPE_FOR_LOWER_ELS 254 spe_enable(el2_unused); 255 #endif 256 257 #if ENABLE_AMU 258 amu_enable(el2_unused); 259 #endif 260 261 #if ENABLE_SVE_FOR_NS 262 sve_enable(el2_unused); 263 #endif 264 265 #if ENABLE_MPAM_FOR_LOWER_ELS 266 mpam_enable(el2_unused); 267 #endif 268 #endif 269 } 270 271 /******************************************************************************* 272 * The following function initializes the cpu_context for a CPU specified by 273 * its `cpu_idx` for first use, and sets the initial entrypoint state as 274 * specified by the entry_point_info structure. 275 ******************************************************************************/ 276 void cm_init_context_by_index(unsigned int cpu_idx, 277 const entry_point_info_t *ep) 278 { 279 cpu_context_t *ctx; 280 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 281 cm_setup_context(ctx, ep); 282 } 283 284 /******************************************************************************* 285 * The following function initializes the cpu_context for the current CPU 286 * for first use, and sets the initial entrypoint state as specified by the 287 * entry_point_info structure. 288 ******************************************************************************/ 289 void cm_init_my_context(const entry_point_info_t *ep) 290 { 291 cpu_context_t *ctx; 292 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 293 cm_setup_context(ctx, ep); 294 } 295 296 /******************************************************************************* 297 * Prepare the CPU system registers for first entry into secure or normal world 298 * 299 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 300 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 301 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 302 * For all entries, the EL1 registers are initialized from the cpu_context 303 ******************************************************************************/ 304 void cm_prepare_el3_exit(uint32_t security_state) 305 { 306 uint32_t sctlr_elx, scr_el3, mdcr_el2; 307 cpu_context_t *ctx = cm_get_context(security_state); 308 bool el2_unused = false; 309 uint64_t hcr_el2 = 0U; 310 311 assert(ctx != NULL); 312 313 if (security_state == NON_SECURE) { 314 scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx), 315 CTX_SCR_EL3); 316 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 317 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 318 sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx), 319 CTX_SCTLR_EL1); 320 sctlr_elx &= SCTLR_EE_BIT; 321 sctlr_elx |= SCTLR_EL2_RES1; 322 write_sctlr_el2(sctlr_elx); 323 } else if (el_implemented(2) != EL_IMPL_NONE) { 324 el2_unused = true; 325 326 /* 327 * EL2 present but unused, need to disable safely. 328 * SCTLR_EL2 can be ignored in this case. 329 * 330 * Set EL2 register width appropriately: Set HCR_EL2 331 * field to match SCR_EL3.RW. 332 */ 333 if ((scr_el3 & SCR_RW_BIT) != 0U) 334 hcr_el2 |= HCR_RW_BIT; 335 336 /* 337 * For Armv8.3 pointer authentication feature, disable 338 * traps to EL2 when accessing key registers or using 339 * pointer authentication instructions from lower ELs. 340 */ 341 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 342 343 write_hcr_el2(hcr_el2); 344 345 /* 346 * Initialise CPTR_EL2 setting all fields rather than 347 * relying on the hw. All fields have architecturally 348 * UNKNOWN reset values. 349 * 350 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 351 * accesses to the CPACR_EL1 or CPACR from both 352 * Execution states do not trap to EL2. 353 * 354 * CPTR_EL2.TTA: Set to zero so that Non-secure System 355 * register accesses to the trace registers from both 356 * Execution states do not trap to EL2. 357 * 358 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 359 * to SIMD and floating-point functionality from both 360 * Execution states do not trap to EL2. 361 */ 362 write_cptr_el2(CPTR_EL2_RESET_VAL & 363 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 364 | CPTR_EL2_TFP_BIT)); 365 366 /* 367 * Initialise CNTHCTL_EL2. All fields are 368 * architecturally UNKNOWN on reset and are set to zero 369 * except for field(s) listed below. 370 * 371 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 372 * Hyp mode of Non-secure EL0 and EL1 accesses to the 373 * physical timer registers. 374 * 375 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 376 * Hyp mode of Non-secure EL0 and EL1 accesses to the 377 * physical counter registers. 378 */ 379 write_cnthctl_el2(CNTHCTL_RESET_VAL | 380 EL1PCEN_BIT | EL1PCTEN_BIT); 381 382 /* 383 * Initialise CNTVOFF_EL2 to zero as it resets to an 384 * architecturally UNKNOWN value. 385 */ 386 write_cntvoff_el2(0); 387 388 /* 389 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 390 * MPIDR_EL1 respectively. 391 */ 392 write_vpidr_el2(read_midr_el1()); 393 write_vmpidr_el2(read_mpidr_el1()); 394 395 /* 396 * Initialise VTTBR_EL2. All fields are architecturally 397 * UNKNOWN on reset. 398 * 399 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 400 * 2 address translation is disabled, cache maintenance 401 * operations depend on the VMID. 402 * 403 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 404 * translation is disabled. 405 */ 406 write_vttbr_el2(VTTBR_RESET_VAL & 407 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 408 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 409 410 /* 411 * Initialise MDCR_EL2, setting all fields rather than 412 * relying on hw. Some fields are architecturally 413 * UNKNOWN on reset. 414 * 415 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 416 * EL1 System register accesses to the Debug ROM 417 * registers are not trapped to EL2. 418 * 419 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 420 * System register accesses to the powerdown debug 421 * registers are not trapped to EL2. 422 * 423 * MDCR_EL2.TDA: Set to zero so that System register 424 * accesses to the debug registers do not trap to EL2. 425 * 426 * MDCR_EL2.TDE: Set to zero so that debug exceptions 427 * are not routed to EL2. 428 * 429 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 430 * Monitors. 431 * 432 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 433 * EL1 accesses to all Performance Monitors registers 434 * are not trapped to EL2. 435 * 436 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 437 * and EL1 accesses to the PMCR_EL0 or PMCR are not 438 * trapped to EL2. 439 * 440 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 441 * architecturally-defined reset value. 442 */ 443 mdcr_el2 = ((MDCR_EL2_RESET_VAL | 444 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 445 >> PMCR_EL0_N_SHIFT)) & 446 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT 447 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT 448 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT 449 | MDCR_EL2_TPMCR_BIT)); 450 451 write_mdcr_el2(mdcr_el2); 452 453 /* 454 * Initialise HSTR_EL2. All fields are architecturally 455 * UNKNOWN on reset. 456 * 457 * HSTR_EL2.T<n>: Set all these fields to zero so that 458 * Non-secure EL0 or EL1 accesses to System registers 459 * do not trap to EL2. 460 */ 461 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 462 /* 463 * Initialise CNTHP_CTL_EL2. All fields are 464 * architecturally UNKNOWN on reset. 465 * 466 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 467 * physical timer and prevent timer interrupts. 468 */ 469 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 470 ~(CNTHP_CTL_ENABLE_BIT)); 471 } 472 enable_extensions_nonsecure(el2_unused); 473 } 474 475 cm_el1_sysregs_context_restore(security_state); 476 cm_set_next_eret_context(security_state); 477 } 478 479 /******************************************************************************* 480 * The next four functions are used by runtime services to save and restore 481 * EL1 context on the 'cpu_context' structure for the specified security 482 * state. 483 ******************************************************************************/ 484 void cm_el1_sysregs_context_save(uint32_t security_state) 485 { 486 cpu_context_t *ctx; 487 488 ctx = cm_get_context(security_state); 489 assert(ctx != NULL); 490 491 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 492 493 #if IMAGE_BL31 494 if (security_state == SECURE) 495 PUBLISH_EVENT(cm_exited_secure_world); 496 else 497 PUBLISH_EVENT(cm_exited_normal_world); 498 #endif 499 } 500 501 void cm_el1_sysregs_context_restore(uint32_t security_state) 502 { 503 cpu_context_t *ctx; 504 505 ctx = cm_get_context(security_state); 506 assert(ctx != NULL); 507 508 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 509 510 #if IMAGE_BL31 511 if (security_state == SECURE) 512 PUBLISH_EVENT(cm_entering_secure_world); 513 else 514 PUBLISH_EVENT(cm_entering_normal_world); 515 #endif 516 } 517 518 /******************************************************************************* 519 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 520 * given security state with the given entrypoint 521 ******************************************************************************/ 522 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 523 { 524 cpu_context_t *ctx; 525 el3_state_t *state; 526 527 ctx = cm_get_context(security_state); 528 assert(ctx != NULL); 529 530 /* Populate EL3 state so that ERET jumps to the correct entry */ 531 state = get_el3state_ctx(ctx); 532 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 533 } 534 535 /******************************************************************************* 536 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 537 * pertaining to the given security state 538 ******************************************************************************/ 539 void cm_set_elr_spsr_el3(uint32_t security_state, 540 uintptr_t entrypoint, uint32_t spsr) 541 { 542 cpu_context_t *ctx; 543 el3_state_t *state; 544 545 ctx = cm_get_context(security_state); 546 assert(ctx != NULL); 547 548 /* Populate EL3 state so that ERET jumps to the correct entry */ 549 state = get_el3state_ctx(ctx); 550 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 551 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 552 } 553 554 /******************************************************************************* 555 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 556 * pertaining to the given security state using the value and bit position 557 * specified in the parameters. It preserves all other bits. 558 ******************************************************************************/ 559 void cm_write_scr_el3_bit(uint32_t security_state, 560 uint32_t bit_pos, 561 uint32_t value) 562 { 563 cpu_context_t *ctx; 564 el3_state_t *state; 565 uint32_t scr_el3; 566 567 ctx = cm_get_context(security_state); 568 assert(ctx != NULL); 569 570 /* Ensure that the bit position is a valid one */ 571 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 572 573 /* Ensure that the 'value' is only a bit wide */ 574 assert(value <= 1U); 575 576 /* 577 * Get the SCR_EL3 value from the cpu context, clear the desired bit 578 * and set it to its new value. 579 */ 580 state = get_el3state_ctx(ctx); 581 scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 582 scr_el3 &= ~(1U << bit_pos); 583 scr_el3 |= value << bit_pos; 584 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 585 } 586 587 /******************************************************************************* 588 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 589 * given security state. 590 ******************************************************************************/ 591 uint32_t cm_get_scr_el3(uint32_t security_state) 592 { 593 cpu_context_t *ctx; 594 el3_state_t *state; 595 596 ctx = cm_get_context(security_state); 597 assert(ctx != NULL); 598 599 /* Populate EL3 state so that ERET jumps to the correct entry */ 600 state = get_el3state_ctx(ctx); 601 return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 602 } 603 604 /******************************************************************************* 605 * This function is used to program the context that's used for exception 606 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 607 * the required security state 608 ******************************************************************************/ 609 void cm_set_next_eret_context(uint32_t security_state) 610 { 611 cpu_context_t *ctx; 612 613 ctx = cm_get_context(security_state); 614 assert(ctx != NULL); 615 616 cm_set_next_context(ctx); 617 } 618