1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/sme.h> 28 #include <lib/extensions/spe.h> 29 #include <lib/extensions/sve.h> 30 #include <lib/extensions/sys_reg_trace.h> 31 #include <lib/extensions/trbe.h> 32 #include <lib/extensions/trf.h> 33 #include <lib/utils.h> 34 35 #if ENABLE_FEAT_TWED 36 /* Make sure delay value fits within the range(0-15) */ 37 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 38 #endif /* ENABLE_FEAT_TWED */ 39 40 static void manage_extensions_secure(cpu_context_t *ctx); 41 42 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 43 { 44 u_register_t sctlr_elx, actlr_elx; 45 46 /* 47 * Initialise SCTLR_EL1 to the reset value corresponding to the target 48 * execution state setting all fields rather than relying on the hw. 49 * Some fields have architecturally UNKNOWN reset values and these are 50 * set to zero. 51 * 52 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 53 * 54 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 55 * required by PSCI specification) 56 */ 57 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 58 if (GET_RW(ep->spsr) == MODE_RW_64) { 59 sctlr_elx |= SCTLR_EL1_RES1; 60 } else { 61 /* 62 * If the target execution state is AArch32 then the following 63 * fields need to be set. 64 * 65 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 66 * instructions are not trapped to EL1. 67 * 68 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 69 * instructions are not trapped to EL1. 70 * 71 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 72 * CP15DMB, CP15DSB, and CP15ISB instructions. 73 */ 74 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 75 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 76 } 77 78 #if ERRATA_A75_764081 79 /* 80 * If workaround of errata 764081 for Cortex-A75 is used then set 81 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 82 */ 83 sctlr_elx |= SCTLR_IESB_BIT; 84 #endif 85 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 86 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 87 88 /* 89 * Base the context ACTLR_EL1 on the current value, as it is 90 * implementation defined. The context restore process will write 91 * the value from the context to the actual register and can cause 92 * problems for processor cores that don't expect certain bits to 93 * be zero. 94 */ 95 actlr_elx = read_actlr_el1(); 96 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 97 } 98 99 /****************************************************************************** 100 * This function performs initializations that are specific to SECURE state 101 * and updates the cpu context specified by 'ctx'. 102 *****************************************************************************/ 103 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 104 { 105 u_register_t scr_el3; 106 el3_state_t *state; 107 108 state = get_el3state_ctx(ctx); 109 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 110 111 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 112 /* 113 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 114 * indicated by the interrupt routing model for BL31. 115 */ 116 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 117 #endif 118 119 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 120 /* Get Memory Tagging Extension support level */ 121 unsigned int mte = get_armv8_5_mte_support(); 122 #endif 123 /* 124 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 125 * is set, or when MTE is only implemented at EL0. 126 */ 127 #if CTX_INCLUDE_MTE_REGS 128 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 129 scr_el3 |= SCR_ATA_BIT; 130 #else 131 if (mte == MTE_IMPLEMENTED_EL0) { 132 scr_el3 |= SCR_ATA_BIT; 133 } 134 #endif /* CTX_INCLUDE_MTE_REGS */ 135 136 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 137 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) { 138 if (GET_RW(ep->spsr) != MODE_RW_64) { 139 ERROR("S-EL2 can not be used in AArch32\n."); 140 panic(); 141 } 142 143 scr_el3 |= SCR_EEL2_BIT; 144 } 145 146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 147 148 /* 149 * Initialize EL1 context registers unless SPMC is running 150 * at S-EL2. 151 */ 152 #if !SPMD_SPM_AT_SEL2 153 setup_el1_context(ctx, ep); 154 #endif 155 156 manage_extensions_secure(ctx); 157 } 158 159 #if ENABLE_RME 160 /****************************************************************************** 161 * This function performs initializations that are specific to REALM state 162 * and updates the cpu context specified by 'ctx'. 163 *****************************************************************************/ 164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 165 { 166 u_register_t scr_el3; 167 el3_state_t *state; 168 169 state = get_el3state_ctx(ctx); 170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT; 173 174 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 175 } 176 #endif /* ENABLE_RME */ 177 178 /****************************************************************************** 179 * This function performs initializations that are specific to NON-SECURE state 180 * and updates the cpu context specified by 'ctx'. 181 *****************************************************************************/ 182 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 183 { 184 u_register_t scr_el3; 185 el3_state_t *state; 186 187 state = get_el3state_ctx(ctx); 188 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 189 190 /* SCR_NS: Set the NS bit */ 191 scr_el3 |= SCR_NS_BIT; 192 193 #if !CTX_INCLUDE_PAUTH_REGS 194 /* 195 * If the pointer authentication registers aren't saved during world 196 * switches the value of the registers can be leaked from the Secure to 197 * the Non-secure world. To prevent this, rather than enabling pointer 198 * authentication everywhere, we only enable it in the Non-secure world. 199 * 200 * If the Secure world wants to use pointer authentication, 201 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 202 */ 203 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 204 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 205 206 /* Allow access to Allocation Tags when MTE is implemented. */ 207 scr_el3 |= SCR_ATA_BIT; 208 209 #if RAS_TRAP_NS_ERR_REC_ACCESS 210 /* 211 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 212 * and RAS ERX registers from EL1 and EL2(from any security state) 213 * are trapped to EL3. 214 * Set here to trap only for NS EL1/EL2 215 * 216 */ 217 scr_el3 |= SCR_TERR_BIT; 218 #endif 219 220 #ifdef IMAGE_BL31 221 /* 222 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 223 * indicated by the interrupt routing model for BL31. 224 */ 225 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 226 #endif 227 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 228 229 /* Initialize EL1 context registers */ 230 setup_el1_context(ctx, ep); 231 232 /* Initialize EL2 context registers */ 233 #if CTX_INCLUDE_EL2_REGS 234 235 /* 236 * Initialize SCTLR_EL2 context register using Endianness value 237 * taken from the entrypoint attribute. 238 */ 239 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 240 sctlr_el2 |= SCTLR_EL2_RES1; 241 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 242 sctlr_el2); 243 244 /* 245 * Program the ICC_SRE_EL2 to make sure the correct bits are set 246 * when restoring NS context. 247 */ 248 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 249 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 250 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 251 icc_sre_el2); 252 #endif /* CTX_INCLUDE_EL2_REGS */ 253 } 254 255 /******************************************************************************* 256 * The following function performs initialization of the cpu_context 'ctx' 257 * for first use that is common to all security states, and sets the 258 * initial entrypoint state as specified by the entry_point_info structure. 259 * 260 * The EE and ST attributes are used to configure the endianness and secure 261 * timer availability for the new execution context. 262 ******************************************************************************/ 263 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 264 { 265 u_register_t scr_el3; 266 el3_state_t *state; 267 gp_regs_t *gp_regs; 268 269 /* Clear any residual register values from the context */ 270 zeromem(ctx, sizeof(*ctx)); 271 272 /* 273 * SCR_EL3 was initialised during reset sequence in macro 274 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 275 * affect the next EL. 276 * 277 * The following fields are initially set to zero and then updated to 278 * the required value depending on the state of the SPSR_EL3 and the 279 * Security state and entrypoint attributes of the next EL. 280 */ 281 scr_el3 = read_scr(); 282 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 283 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 284 285 /* 286 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 287 * Exception level as specified by SPSR. 288 */ 289 if (GET_RW(ep->spsr) == MODE_RW_64) { 290 scr_el3 |= SCR_RW_BIT; 291 } 292 293 /* 294 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 295 * Secure timer registers to EL3, from AArch64 state only, if specified 296 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 297 * bit always behaves as 1 (i.e. secure physical timer register access 298 * is not trapped) 299 */ 300 if (EP_GET_ST(ep->h.attr) != 0U) { 301 scr_el3 |= SCR_ST_BIT; 302 } 303 304 /* 305 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 306 * SCR_EL3.HXEn. 307 */ 308 #if ENABLE_FEAT_HCX 309 scr_el3 |= SCR_HXEn_BIT; 310 #endif 311 312 /* 313 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 314 * registers are trapped to EL3. 315 */ 316 #if ENABLE_FEAT_RNG_TRAP 317 scr_el3 |= SCR_TRNDR_BIT; 318 #endif 319 320 #if !HANDLE_EA_EL3_FIRST 321 /* 322 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 323 * to EL3 when executing at a lower EL. When executing at EL3, External 324 * Aborts are taken to EL3. 325 */ 326 scr_el3 &= ~SCR_EA_BIT; 327 #endif 328 329 #if FAULT_INJECTION_SUPPORT 330 /* Enable fault injection from lower ELs */ 331 scr_el3 |= SCR_FIEN_BIT; 332 #endif 333 334 /* 335 * CPTR_EL3 was initialized out of reset, copy that value to the 336 * context register. 337 */ 338 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 339 340 /* 341 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 342 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 343 * next mode is Hyp. 344 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 345 * same conditions as HVC instructions and when the processor supports 346 * ARMv8.6-FGT. 347 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 348 * CNTPOFF_EL2 register under the same conditions as HVC instructions 349 * and when the processor supports ECV. 350 */ 351 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 352 || ((GET_RW(ep->spsr) != MODE_RW_64) 353 && (GET_M32(ep->spsr) == MODE32_hyp))) { 354 scr_el3 |= SCR_HCE_BIT; 355 356 if (is_armv8_6_fgt_present()) { 357 scr_el3 |= SCR_FGTEN_BIT; 358 } 359 360 if (get_armv8_6_ecv_support() 361 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 362 scr_el3 |= SCR_ECVEN_BIT; 363 } 364 } 365 366 #if ENABLE_FEAT_TWED 367 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 368 /* Set delay in SCR_EL3 */ 369 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 370 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 371 << SCR_TWEDEL_SHIFT); 372 373 /* Enable WFE delay */ 374 scr_el3 |= SCR_TWEDEn_BIT; 375 #endif /* ENABLE_FEAT_TWED */ 376 377 /* 378 * Populate EL3 state so that we've the right context 379 * before doing ERET 380 */ 381 state = get_el3state_ctx(ctx); 382 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 383 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 384 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 385 386 /* 387 * Store the X0-X7 value from the entrypoint into the context 388 * Use memcpy as we are in control of the layout of the structures 389 */ 390 gp_regs = get_gpregs_ctx(ctx); 391 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 392 } 393 394 /******************************************************************************* 395 * Context management library initialization routine. This library is used by 396 * runtime services to share pointers to 'cpu_context' structures for secure 397 * non-secure and realm states. Management of the structures and their associated 398 * memory is not done by the context management library e.g. the PSCI service 399 * manages the cpu context used for entry from and exit to the non-secure state. 400 * The Secure payload dispatcher service manages the context(s) corresponding to 401 * the secure state. It also uses this library to get access to the non-secure 402 * state cpu context pointers. 403 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 404 * which will be used for programming an entry into a lower EL. The same context 405 * will be used to save state upon exception entry from that EL. 406 ******************************************************************************/ 407 void __init cm_init(void) 408 { 409 /* 410 * The context management library has only global data to intialize, but 411 * that will be done when the BSS is zeroed out. 412 */ 413 } 414 415 /******************************************************************************* 416 * This is the high-level function used to initialize the cpu_context 'ctx' for 417 * first use. It performs initializations that are common to all security states 418 * and initializations specific to the security state specified in 'ep' 419 ******************************************************************************/ 420 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 421 { 422 unsigned int security_state; 423 424 assert(ctx != NULL); 425 426 /* 427 * Perform initializations that are common 428 * to all security states 429 */ 430 setup_context_common(ctx, ep); 431 432 security_state = GET_SECURITY_STATE(ep->h.attr); 433 434 /* Perform security state specific initializations */ 435 switch (security_state) { 436 case SECURE: 437 setup_secure_context(ctx, ep); 438 break; 439 #if ENABLE_RME 440 case REALM: 441 setup_realm_context(ctx, ep); 442 break; 443 #endif 444 case NON_SECURE: 445 setup_ns_context(ctx, ep); 446 break; 447 default: 448 ERROR("Invalid security state\n"); 449 panic(); 450 break; 451 } 452 } 453 454 /******************************************************************************* 455 * Enable architecture extensions on first entry to Non-secure world. 456 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 457 * it is zero. 458 ******************************************************************************/ 459 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 460 { 461 #if IMAGE_BL31 462 #if ENABLE_SPE_FOR_LOWER_ELS 463 spe_enable(el2_unused); 464 #endif 465 466 #if ENABLE_AMU 467 amu_enable(el2_unused, ctx); 468 #endif 469 470 #if ENABLE_SME_FOR_NS 471 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 472 sme_enable(ctx); 473 #elif ENABLE_SVE_FOR_NS 474 /* Enable SVE and FPU/SIMD for non-secure world. */ 475 sve_enable(ctx); 476 #endif 477 478 #if ENABLE_MPAM_FOR_LOWER_ELS 479 mpam_enable(el2_unused); 480 #endif 481 482 #if ENABLE_TRBE_FOR_NS 483 trbe_enable(); 484 #endif /* ENABLE_TRBE_FOR_NS */ 485 486 #if ENABLE_BRBE_FOR_NS 487 brbe_enable(); 488 #endif /* ENABLE_BRBE_FOR_NS */ 489 490 #if ENABLE_SYS_REG_TRACE_FOR_NS 491 sys_reg_trace_enable(ctx); 492 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 493 494 #if ENABLE_TRF_FOR_NS 495 trf_enable(); 496 #endif /* ENABLE_TRF_FOR_NS */ 497 #endif 498 } 499 500 /******************************************************************************* 501 * Enable architecture extensions on first entry to Secure world. 502 ******************************************************************************/ 503 static void manage_extensions_secure(cpu_context_t *ctx) 504 { 505 #if IMAGE_BL31 506 #if ENABLE_SME_FOR_NS 507 #if ENABLE_SME_FOR_SWD 508 /* 509 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must 510 * ensure SME, SVE, and FPU/SIMD context properly managed. 511 */ 512 sme_enable(ctx); 513 #else /* ENABLE_SME_FOR_SWD */ 514 /* 515 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can 516 * safely use the associated registers. 517 */ 518 sme_disable(ctx); 519 #endif /* ENABLE_SME_FOR_SWD */ 520 #elif ENABLE_SVE_FOR_NS 521 #if ENABLE_SVE_FOR_SWD 522 /* 523 * Enable SVE and FPU in secure context, secure manager must ensure that 524 * the SVE and FPU register contexts are properly managed. 525 */ 526 sve_enable(ctx); 527 #else /* ENABLE_SVE_FOR_SWD */ 528 /* 529 * Disable SVE and FPU in secure context so non-secure world can safely 530 * use them. 531 */ 532 sve_disable(ctx); 533 #endif /* ENABLE_SVE_FOR_SWD */ 534 #endif /* ENABLE_SVE_FOR_NS */ 535 #endif /* IMAGE_BL31 */ 536 } 537 538 /******************************************************************************* 539 * The following function initializes the cpu_context for a CPU specified by 540 * its `cpu_idx` for first use, and sets the initial entrypoint state as 541 * specified by the entry_point_info structure. 542 ******************************************************************************/ 543 void cm_init_context_by_index(unsigned int cpu_idx, 544 const entry_point_info_t *ep) 545 { 546 cpu_context_t *ctx; 547 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 548 cm_setup_context(ctx, ep); 549 } 550 551 /******************************************************************************* 552 * The following function initializes the cpu_context for the current CPU 553 * for first use, and sets the initial entrypoint state as specified by the 554 * entry_point_info structure. 555 ******************************************************************************/ 556 void cm_init_my_context(const entry_point_info_t *ep) 557 { 558 cpu_context_t *ctx; 559 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 560 cm_setup_context(ctx, ep); 561 } 562 563 /******************************************************************************* 564 * Prepare the CPU system registers for first entry into realm, secure, or 565 * normal world. 566 * 567 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 568 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 569 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 570 * For all entries, the EL1 registers are initialized from the cpu_context 571 ******************************************************************************/ 572 void cm_prepare_el3_exit(uint32_t security_state) 573 { 574 u_register_t sctlr_elx, scr_el3, mdcr_el2; 575 cpu_context_t *ctx = cm_get_context(security_state); 576 bool el2_unused = false; 577 uint64_t hcr_el2 = 0U; 578 579 assert(ctx != NULL); 580 581 if (security_state == NON_SECURE) { 582 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 583 CTX_SCR_EL3); 584 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 585 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 586 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 587 CTX_SCTLR_EL1); 588 sctlr_elx &= SCTLR_EE_BIT; 589 sctlr_elx |= SCTLR_EL2_RES1; 590 #if ERRATA_A75_764081 591 /* 592 * If workaround of errata 764081 for Cortex-A75 is used 593 * then set SCTLR_EL2.IESB to enable Implicit Error 594 * Synchronization Barrier. 595 */ 596 sctlr_elx |= SCTLR_IESB_BIT; 597 #endif 598 write_sctlr_el2(sctlr_elx); 599 } else if (el_implemented(2) != EL_IMPL_NONE) { 600 el2_unused = true; 601 602 /* 603 * EL2 present but unused, need to disable safely. 604 * SCTLR_EL2 can be ignored in this case. 605 * 606 * Set EL2 register width appropriately: Set HCR_EL2 607 * field to match SCR_EL3.RW. 608 */ 609 if ((scr_el3 & SCR_RW_BIT) != 0U) 610 hcr_el2 |= HCR_RW_BIT; 611 612 /* 613 * For Armv8.3 pointer authentication feature, disable 614 * traps to EL2 when accessing key registers or using 615 * pointer authentication instructions from lower ELs. 616 */ 617 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 618 619 write_hcr_el2(hcr_el2); 620 621 /* 622 * Initialise CPTR_EL2 setting all fields rather than 623 * relying on the hw. All fields have architecturally 624 * UNKNOWN reset values. 625 * 626 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 627 * accesses to the CPACR_EL1 or CPACR from both 628 * Execution states do not trap to EL2. 629 * 630 * CPTR_EL2.TTA: Set to zero so that Non-secure System 631 * register accesses to the trace registers from both 632 * Execution states do not trap to EL2. 633 * If PE trace unit System registers are not implemented 634 * then this bit is reserved, and must be set to zero. 635 * 636 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 637 * to SIMD and floating-point functionality from both 638 * Execution states do not trap to EL2. 639 */ 640 write_cptr_el2(CPTR_EL2_RESET_VAL & 641 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 642 | CPTR_EL2_TFP_BIT)); 643 644 /* 645 * Initialise CNTHCTL_EL2. All fields are 646 * architecturally UNKNOWN on reset and are set to zero 647 * except for field(s) listed below. 648 * 649 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 650 * Hyp mode of Non-secure EL0 and EL1 accesses to the 651 * physical timer registers. 652 * 653 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 654 * Hyp mode of Non-secure EL0 and EL1 accesses to the 655 * physical counter registers. 656 */ 657 write_cnthctl_el2(CNTHCTL_RESET_VAL | 658 EL1PCEN_BIT | EL1PCTEN_BIT); 659 660 /* 661 * Initialise CNTVOFF_EL2 to zero as it resets to an 662 * architecturally UNKNOWN value. 663 */ 664 write_cntvoff_el2(0); 665 666 /* 667 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 668 * MPIDR_EL1 respectively. 669 */ 670 write_vpidr_el2(read_midr_el1()); 671 write_vmpidr_el2(read_mpidr_el1()); 672 673 /* 674 * Initialise VTTBR_EL2. All fields are architecturally 675 * UNKNOWN on reset. 676 * 677 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 678 * 2 address translation is disabled, cache maintenance 679 * operations depend on the VMID. 680 * 681 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 682 * translation is disabled. 683 */ 684 write_vttbr_el2(VTTBR_RESET_VAL & 685 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 686 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 687 688 /* 689 * Initialise MDCR_EL2, setting all fields rather than 690 * relying on hw. Some fields are architecturally 691 * UNKNOWN on reset. 692 * 693 * MDCR_EL2.HLP: Set to one so that event counter 694 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 695 * occurs on the increment that changes 696 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 697 * implemented. This bit is RES0 in versions of the 698 * architecture earlier than ARMv8.5, setting it to 1 699 * doesn't have any effect on them. 700 * 701 * MDCR_EL2.TTRF: Set to zero so that access to Trace 702 * Filter Control register TRFCR_EL1 at EL1 is not 703 * trapped to EL2. This bit is RES0 in versions of 704 * the architecture earlier than ARMv8.4. 705 * 706 * MDCR_EL2.HPMD: Set to one so that event counting is 707 * prohibited at EL2. This bit is RES0 in versions of 708 * the architecture earlier than ARMv8.1, setting it 709 * to 1 doesn't have any effect on them. 710 * 711 * MDCR_EL2.TPMS: Set to zero so that accesses to 712 * Statistical Profiling control registers from EL1 713 * do not trap to EL2. This bit is RES0 when SPE is 714 * not implemented. 715 * 716 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 717 * EL1 System register accesses to the Debug ROM 718 * registers are not trapped to EL2. 719 * 720 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 721 * System register accesses to the powerdown debug 722 * registers are not trapped to EL2. 723 * 724 * MDCR_EL2.TDA: Set to zero so that System register 725 * accesses to the debug registers do not trap to EL2. 726 * 727 * MDCR_EL2.TDE: Set to zero so that debug exceptions 728 * are not routed to EL2. 729 * 730 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 731 * Monitors. 732 * 733 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 734 * EL1 accesses to all Performance Monitors registers 735 * are not trapped to EL2. 736 * 737 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 738 * and EL1 accesses to the PMCR_EL0 or PMCR are not 739 * trapped to EL2. 740 * 741 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 742 * architecturally-defined reset value. 743 * 744 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 745 * owning exception level is NS-EL1 and, tracing is 746 * prohibited at NS-EL2. These bits are RES0 when 747 * FEAT_TRBE is not implemented. 748 */ 749 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 750 MDCR_EL2_HPMD) | 751 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 752 >> PMCR_EL0_N_SHIFT)) & 753 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 754 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 755 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 756 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 757 MDCR_EL2_TPMCR_BIT | 758 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 759 760 write_mdcr_el2(mdcr_el2); 761 762 /* 763 * Initialise HSTR_EL2. All fields are architecturally 764 * UNKNOWN on reset. 765 * 766 * HSTR_EL2.T<n>: Set all these fields to zero so that 767 * Non-secure EL0 or EL1 accesses to System registers 768 * do not trap to EL2. 769 */ 770 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 771 /* 772 * Initialise CNTHP_CTL_EL2. All fields are 773 * architecturally UNKNOWN on reset. 774 * 775 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 776 * physical timer and prevent timer interrupts. 777 */ 778 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 779 ~(CNTHP_CTL_ENABLE_BIT)); 780 } 781 manage_extensions_nonsecure(el2_unused, ctx); 782 } 783 784 cm_el1_sysregs_context_restore(security_state); 785 cm_set_next_eret_context(security_state); 786 } 787 788 #if CTX_INCLUDE_EL2_REGS 789 /******************************************************************************* 790 * Save EL2 sysreg context 791 ******************************************************************************/ 792 void cm_el2_sysregs_context_save(uint32_t security_state) 793 { 794 u_register_t scr_el3 = read_scr(); 795 796 /* 797 * Always save the non-secure and realm EL2 context, only save the 798 * S-EL2 context if S-EL2 is enabled. 799 */ 800 if ((security_state != SECURE) || 801 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 802 cpu_context_t *ctx; 803 el2_sysregs_t *el2_sysregs_ctx; 804 805 ctx = cm_get_context(security_state); 806 assert(ctx != NULL); 807 808 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 809 810 el2_sysregs_context_save_common(el2_sysregs_ctx); 811 #if ENABLE_SPE_FOR_LOWER_ELS 812 el2_sysregs_context_save_spe(el2_sysregs_ctx); 813 #endif 814 #if CTX_INCLUDE_MTE_REGS 815 el2_sysregs_context_save_mte(el2_sysregs_ctx); 816 #endif 817 #if ENABLE_MPAM_FOR_LOWER_ELS 818 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 819 #endif 820 #if ENABLE_FEAT_FGT 821 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 822 #endif 823 #if ENABLE_FEAT_ECV 824 el2_sysregs_context_save_ecv(el2_sysregs_ctx); 825 #endif 826 #if ENABLE_FEAT_VHE 827 el2_sysregs_context_save_vhe(el2_sysregs_ctx); 828 #endif 829 #if RAS_EXTENSION 830 el2_sysregs_context_save_ras(el2_sysregs_ctx); 831 #endif 832 #if CTX_INCLUDE_NEVE_REGS 833 el2_sysregs_context_save_nv2(el2_sysregs_ctx); 834 #endif 835 #if ENABLE_TRF_FOR_NS 836 el2_sysregs_context_save_trf(el2_sysregs_ctx); 837 #endif 838 #if ENABLE_FEAT_CSV2_2 839 el2_sysregs_context_save_csv2(el2_sysregs_ctx); 840 #endif 841 #if ENABLE_FEAT_HCX 842 el2_sysregs_context_save_hcx(el2_sysregs_ctx); 843 #endif 844 } 845 } 846 847 /******************************************************************************* 848 * Restore EL2 sysreg context 849 ******************************************************************************/ 850 void cm_el2_sysregs_context_restore(uint32_t security_state) 851 { 852 u_register_t scr_el3 = read_scr(); 853 854 /* 855 * Always restore the non-secure and realm EL2 context, only restore the 856 * S-EL2 context if S-EL2 is enabled. 857 */ 858 if ((security_state != SECURE) || 859 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 860 cpu_context_t *ctx; 861 el2_sysregs_t *el2_sysregs_ctx; 862 863 ctx = cm_get_context(security_state); 864 assert(ctx != NULL); 865 866 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 867 868 el2_sysregs_context_restore_common(el2_sysregs_ctx); 869 #if ENABLE_SPE_FOR_LOWER_ELS 870 el2_sysregs_context_restore_spe(el2_sysregs_ctx); 871 #endif 872 #if CTX_INCLUDE_MTE_REGS 873 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 874 #endif 875 #if ENABLE_MPAM_FOR_LOWER_ELS 876 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 877 #endif 878 #if ENABLE_FEAT_FGT 879 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 880 #endif 881 #if ENABLE_FEAT_ECV 882 el2_sysregs_context_restore_ecv(el2_sysregs_ctx); 883 #endif 884 #if ENABLE_FEAT_VHE 885 el2_sysregs_context_restore_vhe(el2_sysregs_ctx); 886 #endif 887 #if RAS_EXTENSION 888 el2_sysregs_context_restore_ras(el2_sysregs_ctx); 889 #endif 890 #if CTX_INCLUDE_NEVE_REGS 891 el2_sysregs_context_restore_nv2(el2_sysregs_ctx); 892 #endif 893 #if ENABLE_TRF_FOR_NS 894 el2_sysregs_context_restore_trf(el2_sysregs_ctx); 895 #endif 896 #if ENABLE_FEAT_CSV2_2 897 el2_sysregs_context_restore_csv2(el2_sysregs_ctx); 898 #endif 899 #if ENABLE_FEAT_HCX 900 el2_sysregs_context_restore_hcx(el2_sysregs_ctx); 901 #endif 902 } 903 } 904 #endif /* CTX_INCLUDE_EL2_REGS */ 905 906 /******************************************************************************* 907 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 908 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 909 * updating EL1 and EL2 registers. Otherwise, it calls the generic 910 * cm_prepare_el3_exit function. 911 ******************************************************************************/ 912 void cm_prepare_el3_exit_ns(void) 913 { 914 #if CTX_INCLUDE_EL2_REGS 915 cpu_context_t *ctx = cm_get_context(NON_SECURE); 916 assert(ctx != NULL); 917 918 /* Assert that EL2 is used. */ 919 #if ENABLE_ASSERTIONS 920 el3_state_t *state = get_el3state_ctx(ctx); 921 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 922 #endif 923 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 924 (el_implemented(2U) != EL_IMPL_NONE)); 925 926 /* 927 * Currently some extensions are configured using 928 * direct register updates. Therefore, do this here 929 * instead of when setting up context. 930 */ 931 manage_extensions_nonsecure(0, ctx); 932 933 /* 934 * Set the NS bit to be able to access the ICC_SRE_EL2 935 * register when restoring context. 936 */ 937 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 938 939 /* 940 * Ensure the NS bit change is committed before the EL2/EL1 941 * state restoration. 942 */ 943 isb(); 944 945 /* Restore EL2 and EL1 sysreg contexts */ 946 cm_el2_sysregs_context_restore(NON_SECURE); 947 cm_el1_sysregs_context_restore(NON_SECURE); 948 cm_set_next_eret_context(NON_SECURE); 949 #else 950 cm_prepare_el3_exit(NON_SECURE); 951 #endif /* CTX_INCLUDE_EL2_REGS */ 952 } 953 954 /******************************************************************************* 955 * The next four functions are used by runtime services to save and restore 956 * EL1 context on the 'cpu_context' structure for the specified security 957 * state. 958 ******************************************************************************/ 959 void cm_el1_sysregs_context_save(uint32_t security_state) 960 { 961 cpu_context_t *ctx; 962 963 ctx = cm_get_context(security_state); 964 assert(ctx != NULL); 965 966 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 967 968 #if IMAGE_BL31 969 if (security_state == SECURE) 970 PUBLISH_EVENT(cm_exited_secure_world); 971 else 972 PUBLISH_EVENT(cm_exited_normal_world); 973 #endif 974 } 975 976 void cm_el1_sysregs_context_restore(uint32_t security_state) 977 { 978 cpu_context_t *ctx; 979 980 ctx = cm_get_context(security_state); 981 assert(ctx != NULL); 982 983 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 984 985 #if IMAGE_BL31 986 if (security_state == SECURE) 987 PUBLISH_EVENT(cm_entering_secure_world); 988 else 989 PUBLISH_EVENT(cm_entering_normal_world); 990 #endif 991 } 992 993 /******************************************************************************* 994 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 995 * given security state with the given entrypoint 996 ******************************************************************************/ 997 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 998 { 999 cpu_context_t *ctx; 1000 el3_state_t *state; 1001 1002 ctx = cm_get_context(security_state); 1003 assert(ctx != NULL); 1004 1005 /* Populate EL3 state so that ERET jumps to the correct entry */ 1006 state = get_el3state_ctx(ctx); 1007 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1008 } 1009 1010 /******************************************************************************* 1011 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1012 * pertaining to the given security state 1013 ******************************************************************************/ 1014 void cm_set_elr_spsr_el3(uint32_t security_state, 1015 uintptr_t entrypoint, uint32_t spsr) 1016 { 1017 cpu_context_t *ctx; 1018 el3_state_t *state; 1019 1020 ctx = cm_get_context(security_state); 1021 assert(ctx != NULL); 1022 1023 /* Populate EL3 state so that ERET jumps to the correct entry */ 1024 state = get_el3state_ctx(ctx); 1025 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1026 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1027 } 1028 1029 /******************************************************************************* 1030 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1031 * pertaining to the given security state using the value and bit position 1032 * specified in the parameters. It preserves all other bits. 1033 ******************************************************************************/ 1034 void cm_write_scr_el3_bit(uint32_t security_state, 1035 uint32_t bit_pos, 1036 uint32_t value) 1037 { 1038 cpu_context_t *ctx; 1039 el3_state_t *state; 1040 u_register_t scr_el3; 1041 1042 ctx = cm_get_context(security_state); 1043 assert(ctx != NULL); 1044 1045 /* Ensure that the bit position is a valid one */ 1046 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1047 1048 /* Ensure that the 'value' is only a bit wide */ 1049 assert(value <= 1U); 1050 1051 /* 1052 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1053 * and set it to its new value. 1054 */ 1055 state = get_el3state_ctx(ctx); 1056 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1057 scr_el3 &= ~(1UL << bit_pos); 1058 scr_el3 |= (u_register_t)value << bit_pos; 1059 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1060 } 1061 1062 /******************************************************************************* 1063 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1064 * given security state. 1065 ******************************************************************************/ 1066 u_register_t cm_get_scr_el3(uint32_t security_state) 1067 { 1068 cpu_context_t *ctx; 1069 el3_state_t *state; 1070 1071 ctx = cm_get_context(security_state); 1072 assert(ctx != NULL); 1073 1074 /* Populate EL3 state so that ERET jumps to the correct entry */ 1075 state = get_el3state_ctx(ctx); 1076 return read_ctx_reg(state, CTX_SCR_EL3); 1077 } 1078 1079 /******************************************************************************* 1080 * This function is used to program the context that's used for exception 1081 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1082 * the required security state 1083 ******************************************************************************/ 1084 void cm_set_next_eret_context(uint32_t security_state) 1085 { 1086 cpu_context_t *ctx; 1087 1088 ctx = cm_get_context(security_state); 1089 assert(ctx != NULL); 1090 1091 cm_set_next_context(ctx); 1092 } 1093