1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/pmuv3.h> 28 #include <lib/extensions/sme.h> 29 #include <lib/extensions/spe.h> 30 #include <lib/extensions/sve.h> 31 #include <lib/extensions/sys_reg_trace.h> 32 #include <lib/extensions/trbe.h> 33 #include <lib/extensions/trf.h> 34 #include <lib/utils.h> 35 36 #if ENABLE_FEAT_TWED 37 /* Make sure delay value fits within the range(0-15) */ 38 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 39 #endif /* ENABLE_FEAT_TWED */ 40 41 static void manage_extensions_nonsecure(cpu_context_t *ctx); 42 static void manage_extensions_secure(cpu_context_t *ctx); 43 44 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 45 { 46 u_register_t sctlr_elx, actlr_elx; 47 48 /* 49 * Initialise SCTLR_EL1 to the reset value corresponding to the target 50 * execution state setting all fields rather than relying on the hw. 51 * Some fields have architecturally UNKNOWN reset values and these are 52 * set to zero. 53 * 54 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 55 * 56 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 57 * required by PSCI specification) 58 */ 59 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 60 if (GET_RW(ep->spsr) == MODE_RW_64) { 61 sctlr_elx |= SCTLR_EL1_RES1; 62 } else { 63 /* 64 * If the target execution state is AArch32 then the following 65 * fields need to be set. 66 * 67 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 68 * instructions are not trapped to EL1. 69 * 70 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 71 * instructions are not trapped to EL1. 72 * 73 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 74 * CP15DMB, CP15DSB, and CP15ISB instructions. 75 */ 76 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 77 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 78 } 79 80 #if ERRATA_A75_764081 81 /* 82 * If workaround of errata 764081 for Cortex-A75 is used then set 83 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 84 */ 85 sctlr_elx |= SCTLR_IESB_BIT; 86 #endif 87 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 88 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 89 90 /* 91 * Base the context ACTLR_EL1 on the current value, as it is 92 * implementation defined. The context restore process will write 93 * the value from the context to the actual register and can cause 94 * problems for processor cores that don't expect certain bits to 95 * be zero. 96 */ 97 actlr_elx = read_actlr_el1(); 98 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 99 } 100 101 /****************************************************************************** 102 * This function performs initializations that are specific to SECURE state 103 * and updates the cpu context specified by 'ctx'. 104 *****************************************************************************/ 105 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 106 { 107 u_register_t scr_el3; 108 el3_state_t *state; 109 110 state = get_el3state_ctx(ctx); 111 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 112 113 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 114 /* 115 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 116 * indicated by the interrupt routing model for BL31. 117 */ 118 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 119 #endif 120 121 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 122 /* Get Memory Tagging Extension support level */ 123 unsigned int mte = get_armv8_5_mte_support(); 124 #endif 125 /* 126 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 127 * is set, or when MTE is only implemented at EL0. 128 */ 129 #if CTX_INCLUDE_MTE_REGS 130 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 131 scr_el3 |= SCR_ATA_BIT; 132 #else 133 if (mte == MTE_IMPLEMENTED_EL0) { 134 scr_el3 |= SCR_ATA_BIT; 135 } 136 #endif /* CTX_INCLUDE_MTE_REGS */ 137 138 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 139 140 /* 141 * Initialize EL1 context registers unless SPMC is running 142 * at S-EL2. 143 */ 144 #if !SPMD_SPM_AT_SEL2 145 setup_el1_context(ctx, ep); 146 #endif 147 148 manage_extensions_secure(ctx); 149 } 150 151 #if ENABLE_RME 152 /****************************************************************************** 153 * This function performs initializations that are specific to REALM state 154 * and updates the cpu context specified by 'ctx'. 155 *****************************************************************************/ 156 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 157 { 158 u_register_t scr_el3; 159 el3_state_t *state; 160 161 state = get_el3state_ctx(ctx); 162 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 163 164 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 165 166 if (is_feat_csv2_2_supported()) { 167 /* Enable access to the SCXTNUM_ELx registers. */ 168 scr_el3 |= SCR_EnSCXT_BIT; 169 } 170 171 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 172 } 173 #endif /* ENABLE_RME */ 174 175 /****************************************************************************** 176 * This function performs initializations that are specific to NON-SECURE state 177 * and updates the cpu context specified by 'ctx'. 178 *****************************************************************************/ 179 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 180 { 181 u_register_t scr_el3; 182 el3_state_t *state; 183 184 state = get_el3state_ctx(ctx); 185 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 186 187 /* SCR_NS: Set the NS bit */ 188 scr_el3 |= SCR_NS_BIT; 189 190 /* Allow access to Allocation Tags when MTE is implemented. */ 191 scr_el3 |= SCR_ATA_BIT; 192 193 #if !CTX_INCLUDE_PAUTH_REGS 194 /* 195 * Pointer Authentication feature, if present, is always enabled by default 196 * for Non secure lower exception levels. We do not have an explicit 197 * flag to set it. 198 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 199 * exception levels of secure and realm worlds. 200 * 201 * To prevent the leakage between the worlds during world switch, 202 * we enable it only for the non-secure world. 203 * 204 * If the Secure/realm world wants to use pointer authentication, 205 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 206 * it will be enabled globally for all the contexts. 207 * 208 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 209 * other than EL3 210 * 211 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 212 * than EL3 213 */ 214 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 215 216 #endif /* CTX_INCLUDE_PAUTH_REGS */ 217 218 #if HANDLE_EA_EL3_FIRST_NS 219 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 220 scr_el3 |= SCR_EA_BIT; 221 #endif 222 223 #if RAS_TRAP_NS_ERR_REC_ACCESS 224 /* 225 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 226 * and RAS ERX registers from EL1 and EL2(from any security state) 227 * are trapped to EL3. 228 * Set here to trap only for NS EL1/EL2 229 * 230 */ 231 scr_el3 |= SCR_TERR_BIT; 232 #endif 233 234 if (is_feat_csv2_2_supported()) { 235 /* Enable access to the SCXTNUM_ELx registers. */ 236 scr_el3 |= SCR_EnSCXT_BIT; 237 } 238 239 #ifdef IMAGE_BL31 240 /* 241 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 242 * indicated by the interrupt routing model for BL31. 243 */ 244 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 245 #endif 246 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 247 248 /* Initialize EL1 context registers */ 249 setup_el1_context(ctx, ep); 250 251 /* Initialize EL2 context registers */ 252 #if CTX_INCLUDE_EL2_REGS 253 254 /* 255 * Initialize SCTLR_EL2 context register using Endianness value 256 * taken from the entrypoint attribute. 257 */ 258 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 259 sctlr_el2 |= SCTLR_EL2_RES1; 260 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 261 sctlr_el2); 262 263 if (is_feat_hcx_supported()) { 264 /* 265 * Initialize register HCRX_EL2 with its init value. 266 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 267 * chance that this can lead to unexpected behavior in lower 268 * ELs that have not been updated since the introduction of 269 * this feature if not properly initialized, especially when 270 * it comes to those bits that enable/disable traps. 271 */ 272 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, 273 HCRX_EL2_INIT_VAL); 274 } 275 276 if (is_feat_fgt_supported()) { 277 /* 278 * Initialize HFG*_EL2 registers with a default value so legacy 279 * systems unaware of FEAT_FGT do not get trapped due to their lack 280 * of initialization for this feature. 281 */ 282 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2, 283 HFGITR_EL2_INIT_VAL); 284 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2, 285 HFGRTR_EL2_INIT_VAL); 286 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2, 287 HFGWTR_EL2_INIT_VAL); 288 } 289 #endif /* CTX_INCLUDE_EL2_REGS */ 290 291 manage_extensions_nonsecure(ctx); 292 } 293 294 /******************************************************************************* 295 * The following function performs initialization of the cpu_context 'ctx' 296 * for first use that is common to all security states, and sets the 297 * initial entrypoint state as specified by the entry_point_info structure. 298 * 299 * The EE and ST attributes are used to configure the endianness and secure 300 * timer availability for the new execution context. 301 ******************************************************************************/ 302 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 303 { 304 u_register_t cptr_el3; 305 u_register_t scr_el3; 306 el3_state_t *state; 307 gp_regs_t *gp_regs; 308 309 state = get_el3state_ctx(ctx); 310 311 /* Clear any residual register values from the context */ 312 zeromem(ctx, sizeof(*ctx)); 313 314 /* 315 * The lower-EL context is zeroed so that no stale values leak to a world. 316 * It is assumed that an all-zero lower-EL context is good enough for it 317 * to boot correctly. However, there are very few registers where this 318 * is not true and some values need to be recreated. 319 */ 320 #if CTX_INCLUDE_EL2_REGS 321 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 322 323 /* 324 * These bits are set in the gicv3 driver. Losing them (especially the 325 * SRE bit) is problematic for all worlds. Henceforth recreate them. 326 */ 327 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 328 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 329 write_ctx_reg(el2_ctx, CTX_ICC_SRE_EL2, icc_sre_el2); 330 #endif /* CTX_INCLUDE_EL2_REGS */ 331 332 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 333 scr_el3 = SCR_RESET_VAL; 334 335 /* 336 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 337 * EL2, EL1 and EL0 are not trapped to EL3. 338 * 339 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 340 * EL2, EL1 and EL0 are not trapped to EL3. 341 * 342 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 343 * both Security states and both Execution states. 344 * 345 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 346 * Non-secure memory. 347 */ 348 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 349 350 scr_el3 |= SCR_SIF_BIT; 351 352 /* 353 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 354 * Exception level as specified by SPSR. 355 */ 356 if (GET_RW(ep->spsr) == MODE_RW_64) { 357 scr_el3 |= SCR_RW_BIT; 358 } 359 360 /* 361 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 362 * Secure timer registers to EL3, from AArch64 state only, if specified 363 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 364 * bit always behaves as 1 (i.e. secure physical timer register access 365 * is not trapped) 366 */ 367 if (EP_GET_ST(ep->h.attr) != 0U) { 368 scr_el3 |= SCR_ST_BIT; 369 } 370 371 /* 372 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 373 * SCR_EL3.HXEn. 374 */ 375 if (is_feat_hcx_supported()) { 376 scr_el3 |= SCR_HXEn_BIT; 377 } 378 379 /* 380 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 381 * registers are trapped to EL3. 382 */ 383 #if ENABLE_FEAT_RNG_TRAP 384 scr_el3 |= SCR_TRNDR_BIT; 385 #endif 386 387 #if FAULT_INJECTION_SUPPORT 388 /* Enable fault injection from lower ELs */ 389 scr_el3 |= SCR_FIEN_BIT; 390 #endif 391 392 #if CTX_INCLUDE_PAUTH_REGS 393 /* 394 * Enable Pointer Authentication globally for all the worlds. 395 * 396 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 397 * other than EL3 398 * 399 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 400 * than EL3 401 */ 402 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 403 #endif /* CTX_INCLUDE_PAUTH_REGS */ 404 405 /* 406 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 407 */ 408 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 409 scr_el3 |= SCR_TCR2EN_BIT; 410 } 411 412 /* 413 * SCR_EL3.PIEN: Enable permission indirection and overlay 414 * registers for AArch64 if present. 415 */ 416 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 417 scr_el3 |= SCR_PIEN_BIT; 418 } 419 420 /* 421 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 422 */ 423 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 424 scr_el3 |= SCR_GCSEn_BIT; 425 } 426 427 /* 428 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 429 * All fields are architecturally UNKNOWN on reset. 430 * 431 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 432 * by Advanced SIMD, floating-point or SVE instructions (if 433 * implemented) do not trap to EL3. 434 * 435 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 436 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 437 */ 438 cptr_el3 = CPTR_EL3_RESET_VAL & ~(TFP_BIT | TCPAC_BIT); 439 440 write_ctx_reg(state, CTX_CPTR_EL3, cptr_el3); 441 442 /* 443 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 444 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 445 * next mode is Hyp. 446 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 447 * same conditions as HVC instructions and when the processor supports 448 * ARMv8.6-FGT. 449 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 450 * CNTPOFF_EL2 register under the same conditions as HVC instructions 451 * and when the processor supports ECV. 452 */ 453 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 454 || ((GET_RW(ep->spsr) != MODE_RW_64) 455 && (GET_M32(ep->spsr) == MODE32_hyp))) { 456 scr_el3 |= SCR_HCE_BIT; 457 458 if (is_feat_fgt_supported()) { 459 scr_el3 |= SCR_FGTEN_BIT; 460 } 461 462 if (is_feat_ecv_supported()) { 463 scr_el3 |= SCR_ECVEN_BIT; 464 } 465 } 466 467 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 468 if (is_feat_twed_supported()) { 469 /* Set delay in SCR_EL3 */ 470 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 471 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 472 << SCR_TWEDEL_SHIFT); 473 474 /* Enable WFE delay */ 475 scr_el3 |= SCR_TWEDEn_BIT; 476 } 477 478 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 479 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 480 if (is_feat_sel2_supported()) { 481 scr_el3 |= SCR_EEL2_BIT; 482 } 483 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 484 485 if (is_feat_mpam_supported()) { 486 write_ctx_reg(get_el3state_ctx(ctx), CTX_MPAM3_EL3, \ 487 MPAM3_EL3_RESET_VAL); 488 } 489 490 /* 491 * Populate EL3 state so that we've the right context 492 * before doing ERET 493 */ 494 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 495 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 496 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 497 498 /* 499 * Store the X0-X7 value from the entrypoint into the context 500 * Use memcpy as we are in control of the layout of the structures 501 */ 502 gp_regs = get_gpregs_ctx(ctx); 503 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 504 } 505 506 /******************************************************************************* 507 * Context management library initialization routine. This library is used by 508 * runtime services to share pointers to 'cpu_context' structures for secure 509 * non-secure and realm states. Management of the structures and their associated 510 * memory is not done by the context management library e.g. the PSCI service 511 * manages the cpu context used for entry from and exit to the non-secure state. 512 * The Secure payload dispatcher service manages the context(s) corresponding to 513 * the secure state. It also uses this library to get access to the non-secure 514 * state cpu context pointers. 515 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 516 * which will be used for programming an entry into a lower EL. The same context 517 * will be used to save state upon exception entry from that EL. 518 ******************************************************************************/ 519 void __init cm_init(void) 520 { 521 /* 522 * The context management library has only global data to initialize, but 523 * that will be done when the BSS is zeroed out. 524 */ 525 } 526 527 /******************************************************************************* 528 * This is the high-level function used to initialize the cpu_context 'ctx' for 529 * first use. It performs initializations that are common to all security states 530 * and initializations specific to the security state specified in 'ep' 531 ******************************************************************************/ 532 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 533 { 534 unsigned int security_state; 535 536 assert(ctx != NULL); 537 538 /* 539 * Perform initializations that are common 540 * to all security states 541 */ 542 setup_context_common(ctx, ep); 543 544 security_state = GET_SECURITY_STATE(ep->h.attr); 545 546 /* Perform security state specific initializations */ 547 switch (security_state) { 548 case SECURE: 549 setup_secure_context(ctx, ep); 550 break; 551 #if ENABLE_RME 552 case REALM: 553 setup_realm_context(ctx, ep); 554 break; 555 #endif 556 case NON_SECURE: 557 setup_ns_context(ctx, ep); 558 break; 559 default: 560 ERROR("Invalid security state\n"); 561 panic(); 562 break; 563 } 564 } 565 566 /******************************************************************************* 567 * Enable architecture extensions for EL3 execution. This function only updates 568 * registers in-place which are expected to either never change or be 569 * overwritten by el3_exit. 570 ******************************************************************************/ 571 #if IMAGE_BL31 572 void cm_manage_extensions_el3(void) 573 { 574 if (is_feat_spe_supported()) { 575 spe_init_el3(); 576 } 577 578 if (is_feat_amu_supported()) { 579 amu_init_el3(); 580 } 581 582 if (is_feat_sme_supported()) { 583 sme_init_el3(); 584 } 585 586 if (is_feat_trbe_supported()) { 587 trbe_init_el3(); 588 } 589 590 if (is_feat_brbe_supported()) { 591 brbe_init_el3(); 592 } 593 594 if (is_feat_trf_supported()) { 595 trf_init_el3(); 596 } 597 598 pmuv3_init_el3(); 599 } 600 #endif /* IMAGE_BL31 */ 601 602 /******************************************************************************* 603 * Enable architecture extensions on first entry to Non-secure world. 604 ******************************************************************************/ 605 static void manage_extensions_nonsecure(cpu_context_t *ctx) 606 { 607 #if IMAGE_BL31 608 if (is_feat_amu_supported()) { 609 amu_enable(ctx); 610 } 611 612 /* Enable SVE and FPU/SIMD */ 613 if (is_feat_sve_supported()) { 614 sve_enable(ctx); 615 } 616 617 if (is_feat_sme_supported()) { 618 sme_enable(ctx); 619 } 620 621 if (is_feat_sys_reg_trace_supported()) { 622 sys_reg_trace_enable(ctx); 623 } 624 625 if (is_feat_mpam_supported()) { 626 mpam_enable(ctx); 627 } 628 pmuv3_enable(ctx); 629 #endif /* IMAGE_BL31 */ 630 } 631 632 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 633 static __unused void enable_pauth_el2(void) 634 { 635 u_register_t hcr_el2 = read_hcr_el2(); 636 /* 637 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 638 * accessing key registers or using pointer authentication instructions 639 * from lower ELs. 640 */ 641 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 642 643 write_hcr_el2(hcr_el2); 644 } 645 646 /******************************************************************************* 647 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 648 * world when EL2 is empty and unused. 649 ******************************************************************************/ 650 static void manage_extensions_nonsecure_el2_unused(void) 651 { 652 #if IMAGE_BL31 653 if (is_feat_spe_supported()) { 654 spe_init_el2_unused(); 655 } 656 657 if (is_feat_amu_supported()) { 658 amu_init_el2_unused(); 659 } 660 661 if (is_feat_mpam_supported()) { 662 mpam_init_el2_unused(); 663 } 664 665 if (is_feat_trbe_supported()) { 666 trbe_init_el2_unused(); 667 } 668 669 if (is_feat_sys_reg_trace_supported()) { 670 sys_reg_trace_init_el2_unused(); 671 } 672 673 if (is_feat_trf_supported()) { 674 trf_init_el2_unused(); 675 } 676 677 pmuv3_init_el2_unused(); 678 679 if (is_feat_sve_supported()) { 680 sve_init_el2_unused(); 681 } 682 683 if (is_feat_sme_supported()) { 684 sme_init_el2_unused(); 685 } 686 687 #if ENABLE_PAUTH 688 enable_pauth_el2(); 689 #endif /* ENABLE_PAUTH */ 690 #endif /* IMAGE_BL31 */ 691 } 692 693 /******************************************************************************* 694 * Enable architecture extensions on first entry to Secure world. 695 ******************************************************************************/ 696 static void manage_extensions_secure(cpu_context_t *ctx) 697 { 698 #if IMAGE_BL31 699 if (is_feat_sve_supported()) { 700 if (ENABLE_SVE_FOR_SWD) { 701 /* 702 * Enable SVE and FPU in secure context, secure manager must 703 * ensure that the SVE and FPU register contexts are properly 704 * managed. 705 */ 706 sve_enable(ctx); 707 } else { 708 /* 709 * Disable SVE and FPU in secure context so non-secure world 710 * can safely use them. 711 */ 712 sve_disable(ctx); 713 } 714 } 715 716 if (is_feat_sme_supported()) { 717 if (ENABLE_SME_FOR_SWD) { 718 /* 719 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 720 * must ensure SME, SVE, and FPU/SIMD context properly managed. 721 */ 722 sme_init_el3(); 723 sme_enable(ctx); 724 } else { 725 /* 726 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 727 * world can safely use the associated registers. 728 */ 729 sme_disable(ctx); 730 } 731 } 732 733 /* NS can access this but Secure shouldn't */ 734 if (is_feat_sys_reg_trace_supported()) { 735 sys_reg_trace_disable(ctx); 736 } 737 #endif /* IMAGE_BL31 */ 738 } 739 740 /******************************************************************************* 741 * The following function initializes the cpu_context for a CPU specified by 742 * its `cpu_idx` for first use, and sets the initial entrypoint state as 743 * specified by the entry_point_info structure. 744 ******************************************************************************/ 745 void cm_init_context_by_index(unsigned int cpu_idx, 746 const entry_point_info_t *ep) 747 { 748 cpu_context_t *ctx; 749 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 750 cm_setup_context(ctx, ep); 751 } 752 753 /******************************************************************************* 754 * The following function initializes the cpu_context for the current CPU 755 * for first use, and sets the initial entrypoint state as specified by the 756 * entry_point_info structure. 757 ******************************************************************************/ 758 void cm_init_my_context(const entry_point_info_t *ep) 759 { 760 cpu_context_t *ctx; 761 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 762 cm_setup_context(ctx, ep); 763 } 764 765 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 766 static __unused void init_nonsecure_el2_unused(cpu_context_t *ctx) 767 { 768 u_register_t hcr_el2 = HCR_RESET_VAL; 769 u_register_t mdcr_el2; 770 u_register_t scr_el3; 771 772 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 773 774 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 775 if ((scr_el3 & SCR_RW_BIT) != 0U) { 776 hcr_el2 |= HCR_RW_BIT; 777 } 778 779 write_hcr_el2(hcr_el2); 780 781 /* 782 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 783 * All fields have architecturally UNKNOWN reset values. 784 */ 785 write_cptr_el2(CPTR_EL2_RESET_VAL); 786 787 /* 788 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 789 * reset and are set to zero except for field(s) listed below. 790 * 791 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 792 * Non-secure EL0 and EL1 accesses to the physical timer registers. 793 * 794 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 795 * Non-secure EL0 and EL1 accesses to the physical counter registers. 796 */ 797 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 798 799 /* 800 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 801 * UNKNOWN value. 802 */ 803 write_cntvoff_el2(0); 804 805 /* 806 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 807 * respectively. 808 */ 809 write_vpidr_el2(read_midr_el1()); 810 write_vmpidr_el2(read_mpidr_el1()); 811 812 /* 813 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 814 * 815 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 816 * translation is disabled, cache maintenance operations depend on the 817 * VMID. 818 * 819 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 820 * disabled. 821 */ 822 write_vttbr_el2(VTTBR_RESET_VAL & 823 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 824 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 825 826 /* 827 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 828 * Some fields are architecturally UNKNOWN on reset. 829 * 830 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 831 * register accesses to the Debug ROM registers are not trapped to EL2. 832 * 833 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 834 * accesses to the powerdown debug registers are not trapped to EL2. 835 * 836 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 837 * debug registers do not trap to EL2. 838 * 839 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 840 * EL2. 841 */ 842 mdcr_el2 = MDCR_EL2_RESET_VAL & 843 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 844 MDCR_EL2_TDE_BIT); 845 846 write_mdcr_el2(mdcr_el2); 847 848 /* 849 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 850 * 851 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 852 * EL1 accesses to System registers do not trap to EL2. 853 */ 854 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 855 856 /* 857 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 858 * reset. 859 * 860 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 861 * and prevent timer interrupts. 862 */ 863 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 864 865 manage_extensions_nonsecure_el2_unused(); 866 } 867 868 /******************************************************************************* 869 * Prepare the CPU system registers for first entry into realm, secure, or 870 * normal world. 871 * 872 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 873 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 874 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 875 * For all entries, the EL1 registers are initialized from the cpu_context 876 ******************************************************************************/ 877 void cm_prepare_el3_exit(uint32_t security_state) 878 { 879 u_register_t sctlr_elx, scr_el3; 880 cpu_context_t *ctx = cm_get_context(security_state); 881 882 assert(ctx != NULL); 883 884 if (security_state == NON_SECURE) { 885 uint64_t el2_implemented = el_implemented(2); 886 887 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 888 CTX_SCR_EL3); 889 890 if (((scr_el3 & SCR_HCE_BIT) != 0U) 891 || (el2_implemented != EL_IMPL_NONE)) { 892 /* 893 * If context is not being used for EL2, initialize 894 * HCRX_EL2 with its init value here. 895 */ 896 if (is_feat_hcx_supported()) { 897 write_hcrx_el2(HCRX_EL2_INIT_VAL); 898 } 899 900 /* 901 * Initialize Fine-grained trap registers introduced 902 * by FEAT_FGT so all traps are initially disabled when 903 * switching to EL2 or a lower EL, preventing undesired 904 * behavior. 905 */ 906 if (is_feat_fgt_supported()) { 907 /* 908 * Initialize HFG*_EL2 registers with a default 909 * value so legacy systems unaware of FEAT_FGT 910 * do not get trapped due to their lack of 911 * initialization for this feature. 912 */ 913 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 914 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 915 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 916 } 917 } 918 919 920 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 921 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 922 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 923 CTX_SCTLR_EL1); 924 sctlr_elx &= SCTLR_EE_BIT; 925 sctlr_elx |= SCTLR_EL2_RES1; 926 #if ERRATA_A75_764081 927 /* 928 * If workaround of errata 764081 for Cortex-A75 is used 929 * then set SCTLR_EL2.IESB to enable Implicit Error 930 * Synchronization Barrier. 931 */ 932 sctlr_elx |= SCTLR_IESB_BIT; 933 #endif 934 write_sctlr_el2(sctlr_elx); 935 } else if (el2_implemented != EL_IMPL_NONE) { 936 init_nonsecure_el2_unused(ctx); 937 } 938 } 939 940 cm_el1_sysregs_context_restore(security_state); 941 cm_set_next_eret_context(security_state); 942 } 943 944 #if CTX_INCLUDE_EL2_REGS 945 946 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 947 { 948 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 949 if (is_feat_amu_supported()) { 950 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 951 } 952 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 953 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 954 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 955 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 956 } 957 958 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 959 { 960 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 961 if (is_feat_amu_supported()) { 962 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 963 } 964 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 965 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 966 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 967 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 968 } 969 970 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 971 { 972 u_register_t mpam_idr = read_mpamidr_el1(); 973 974 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 975 976 /* 977 * The context registers that we intend to save would be part of the 978 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 979 */ 980 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 981 return; 982 } 983 984 /* 985 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 986 * MPAMIDR_HAS_HCR_BIT == 1. 987 */ 988 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 989 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 990 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 991 992 /* 993 * The number of MPAMVPM registers is implementation defined, their 994 * number is stored in the MPAMIDR_EL1 register. 995 */ 996 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 997 case 7: 998 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 999 __fallthrough; 1000 case 6: 1001 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 1002 __fallthrough; 1003 case 5: 1004 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 1005 __fallthrough; 1006 case 4: 1007 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 1008 __fallthrough; 1009 case 3: 1010 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 1011 __fallthrough; 1012 case 2: 1013 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 1014 __fallthrough; 1015 case 1: 1016 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 1017 break; 1018 } 1019 } 1020 1021 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1022 { 1023 u_register_t mpam_idr = read_mpamidr_el1(); 1024 1025 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 1026 1027 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1028 return; 1029 } 1030 1031 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 1032 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 1033 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 1034 1035 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1036 case 7: 1037 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 1038 __fallthrough; 1039 case 6: 1040 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 1041 __fallthrough; 1042 case 5: 1043 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 1044 __fallthrough; 1045 case 4: 1046 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 1047 __fallthrough; 1048 case 3: 1049 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 1050 __fallthrough; 1051 case 2: 1052 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 1053 __fallthrough; 1054 case 1: 1055 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 1056 break; 1057 } 1058 } 1059 1060 /* ----------------------------------------------------- 1061 * The following registers are not added: 1062 * AMEVCNTVOFF0<n>_EL2 1063 * AMEVCNTVOFF1<n>_EL2 1064 * ICH_AP0R<n>_EL2 1065 * ICH_AP1R<n>_EL2 1066 * ICH_LR<n>_EL2 1067 * ----------------------------------------------------- 1068 */ 1069 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1070 { 1071 write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2()); 1072 write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2()); 1073 write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2()); 1074 write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2()); 1075 write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2()); 1076 write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2()); 1077 write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2()); 1078 if (CTX_INCLUDE_AARCH32_REGS) { 1079 write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2()); 1080 } 1081 write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2()); 1082 write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2()); 1083 write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2()); 1084 write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2()); 1085 write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2()); 1086 write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2()); 1087 write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2()); 1088 1089 /* 1090 * Set the NS bit to be able to access the ICC_SRE_EL2 register 1091 * TODO: remove with root context 1092 */ 1093 u_register_t scr_el3 = read_scr_el3(); 1094 1095 write_scr_el3(scr_el3 | SCR_NS_BIT); 1096 isb(); 1097 write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2()); 1098 1099 write_scr_el3(scr_el3); 1100 isb(); 1101 1102 write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2()); 1103 write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2()); 1104 write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2()); 1105 write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2()); 1106 write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2()); 1107 write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2()); 1108 write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2()); 1109 write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2()); 1110 write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2()); 1111 write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2()); 1112 write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2()); 1113 write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2()); 1114 write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2()); 1115 write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2()); 1116 write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2()); 1117 } 1118 1119 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1120 { 1121 write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2)); 1122 write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2)); 1123 write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2)); 1124 write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2)); 1125 write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2)); 1126 write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2)); 1127 write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2)); 1128 if (CTX_INCLUDE_AARCH32_REGS) { 1129 write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2)); 1130 } 1131 write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2)); 1132 write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2)); 1133 write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2)); 1134 write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2)); 1135 write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2)); 1136 write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2)); 1137 write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2)); 1138 1139 /* 1140 * Set the NS bit to be able to access the ICC_SRE_EL2 register 1141 * TODO: remove with root context 1142 */ 1143 u_register_t scr_el3 = read_scr_el3(); 1144 1145 write_scr_el3(scr_el3 | SCR_NS_BIT); 1146 isb(); 1147 write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2)); 1148 1149 write_scr_el3(scr_el3); 1150 isb(); 1151 1152 write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2)); 1153 write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2)); 1154 write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2)); 1155 write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2)); 1156 write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2)); 1157 write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2)); 1158 write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2)); 1159 write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2)); 1160 write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2)); 1161 write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2)); 1162 write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2)); 1163 write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2)); 1164 write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2)); 1165 write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2)); 1166 write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2)); 1167 } 1168 1169 /******************************************************************************* 1170 * Save EL2 sysreg context 1171 ******************************************************************************/ 1172 void cm_el2_sysregs_context_save(uint32_t security_state) 1173 { 1174 cpu_context_t *ctx; 1175 el2_sysregs_t *el2_sysregs_ctx; 1176 1177 ctx = cm_get_context(security_state); 1178 assert(ctx != NULL); 1179 1180 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1181 1182 el2_sysregs_context_save_common(el2_sysregs_ctx); 1183 #if CTX_INCLUDE_MTE_REGS 1184 write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2()); 1185 #endif 1186 if (is_feat_mpam_supported()) { 1187 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1188 } 1189 1190 if (is_feat_fgt_supported()) { 1191 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1192 } 1193 1194 if (is_feat_ecv_v2_supported()) { 1195 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, read_cntpoff_el2()); 1196 } 1197 1198 if (is_feat_vhe_supported()) { 1199 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, read_contextidr_el2()); 1200 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, read_ttbr1_el2()); 1201 } 1202 1203 if (is_feat_ras_supported()) { 1204 write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, read_vdisr_el2()); 1205 write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, read_vsesr_el2()); 1206 } 1207 1208 if (is_feat_nv2_supported()) { 1209 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, read_vncr_el2()); 1210 } 1211 1212 if (is_feat_trf_supported()) { 1213 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 1214 } 1215 1216 if (is_feat_csv2_2_supported()) { 1217 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, read_scxtnum_el2()); 1218 } 1219 1220 if (is_feat_hcx_supported()) { 1221 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1222 } 1223 if (is_feat_tcr2_supported()) { 1224 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1225 } 1226 if (is_feat_sxpie_supported()) { 1227 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); 1228 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); 1229 } 1230 if (is_feat_s2pie_supported()) { 1231 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); 1232 } 1233 if (is_feat_sxpoe_supported()) { 1234 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); 1235 } 1236 if (is_feat_gcs_supported()) { 1237 write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); 1238 write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); 1239 } 1240 } 1241 1242 /******************************************************************************* 1243 * Restore EL2 sysreg context 1244 ******************************************************************************/ 1245 void cm_el2_sysregs_context_restore(uint32_t security_state) 1246 { 1247 cpu_context_t *ctx; 1248 el2_sysregs_t *el2_sysregs_ctx; 1249 1250 ctx = cm_get_context(security_state); 1251 assert(ctx != NULL); 1252 1253 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1254 1255 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1256 #if CTX_INCLUDE_MTE_REGS 1257 write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2)); 1258 #endif 1259 if (is_feat_mpam_supported()) { 1260 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1261 } 1262 1263 if (is_feat_fgt_supported()) { 1264 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1265 } 1266 1267 if (is_feat_ecv_v2_supported()) { 1268 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2)); 1269 } 1270 1271 if (is_feat_vhe_supported()) { 1272 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1273 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1274 } 1275 1276 if (is_feat_ras_supported()) { 1277 write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); 1278 write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); 1279 } 1280 1281 if (is_feat_nv2_supported()) { 1282 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1283 } 1284 if (is_feat_trf_supported()) { 1285 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1286 } 1287 1288 if (is_feat_csv2_2_supported()) { 1289 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2)); 1290 } 1291 1292 if (is_feat_hcx_supported()) { 1293 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1294 } 1295 if (is_feat_tcr2_supported()) { 1296 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1297 } 1298 if (is_feat_sxpie_supported()) { 1299 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); 1300 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); 1301 } 1302 if (is_feat_s2pie_supported()) { 1303 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); 1304 } 1305 if (is_feat_sxpoe_supported()) { 1306 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); 1307 } 1308 if (is_feat_gcs_supported()) { 1309 write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); 1310 write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); 1311 } 1312 } 1313 #endif /* CTX_INCLUDE_EL2_REGS */ 1314 1315 /******************************************************************************* 1316 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1317 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1318 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1319 * cm_prepare_el3_exit function. 1320 ******************************************************************************/ 1321 void cm_prepare_el3_exit_ns(void) 1322 { 1323 #if CTX_INCLUDE_EL2_REGS 1324 #if ENABLE_ASSERTIONS 1325 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1326 assert(ctx != NULL); 1327 1328 /* Assert that EL2 is used. */ 1329 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1330 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1331 (el_implemented(2U) != EL_IMPL_NONE)); 1332 #endif /* ENABLE_ASSERTIONS */ 1333 1334 /* Restore EL2 and EL1 sysreg contexts */ 1335 cm_el2_sysregs_context_restore(NON_SECURE); 1336 cm_el1_sysregs_context_restore(NON_SECURE); 1337 cm_set_next_eret_context(NON_SECURE); 1338 #else 1339 cm_prepare_el3_exit(NON_SECURE); 1340 #endif /* CTX_INCLUDE_EL2_REGS */ 1341 } 1342 1343 /******************************************************************************* 1344 * The next four functions are used by runtime services to save and restore 1345 * EL1 context on the 'cpu_context' structure for the specified security 1346 * state. 1347 ******************************************************************************/ 1348 void cm_el1_sysregs_context_save(uint32_t security_state) 1349 { 1350 cpu_context_t *ctx; 1351 1352 ctx = cm_get_context(security_state); 1353 assert(ctx != NULL); 1354 1355 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1356 1357 #if IMAGE_BL31 1358 if (security_state == SECURE) 1359 PUBLISH_EVENT(cm_exited_secure_world); 1360 else 1361 PUBLISH_EVENT(cm_exited_normal_world); 1362 #endif 1363 } 1364 1365 void cm_el1_sysregs_context_restore(uint32_t security_state) 1366 { 1367 cpu_context_t *ctx; 1368 1369 ctx = cm_get_context(security_state); 1370 assert(ctx != NULL); 1371 1372 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1373 1374 #if IMAGE_BL31 1375 if (security_state == SECURE) 1376 PUBLISH_EVENT(cm_entering_secure_world); 1377 else 1378 PUBLISH_EVENT(cm_entering_normal_world); 1379 #endif 1380 } 1381 1382 /******************************************************************************* 1383 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1384 * given security state with the given entrypoint 1385 ******************************************************************************/ 1386 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1387 { 1388 cpu_context_t *ctx; 1389 el3_state_t *state; 1390 1391 ctx = cm_get_context(security_state); 1392 assert(ctx != NULL); 1393 1394 /* Populate EL3 state so that ERET jumps to the correct entry */ 1395 state = get_el3state_ctx(ctx); 1396 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1397 } 1398 1399 /******************************************************************************* 1400 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1401 * pertaining to the given security state 1402 ******************************************************************************/ 1403 void cm_set_elr_spsr_el3(uint32_t security_state, 1404 uintptr_t entrypoint, uint32_t spsr) 1405 { 1406 cpu_context_t *ctx; 1407 el3_state_t *state; 1408 1409 ctx = cm_get_context(security_state); 1410 assert(ctx != NULL); 1411 1412 /* Populate EL3 state so that ERET jumps to the correct entry */ 1413 state = get_el3state_ctx(ctx); 1414 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1415 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1416 } 1417 1418 /******************************************************************************* 1419 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1420 * pertaining to the given security state using the value and bit position 1421 * specified in the parameters. It preserves all other bits. 1422 ******************************************************************************/ 1423 void cm_write_scr_el3_bit(uint32_t security_state, 1424 uint32_t bit_pos, 1425 uint32_t value) 1426 { 1427 cpu_context_t *ctx; 1428 el3_state_t *state; 1429 u_register_t scr_el3; 1430 1431 ctx = cm_get_context(security_state); 1432 assert(ctx != NULL); 1433 1434 /* Ensure that the bit position is a valid one */ 1435 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1436 1437 /* Ensure that the 'value' is only a bit wide */ 1438 assert(value <= 1U); 1439 1440 /* 1441 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1442 * and set it to its new value. 1443 */ 1444 state = get_el3state_ctx(ctx); 1445 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1446 scr_el3 &= ~(1UL << bit_pos); 1447 scr_el3 |= (u_register_t)value << bit_pos; 1448 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1449 } 1450 1451 /******************************************************************************* 1452 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1453 * given security state. 1454 ******************************************************************************/ 1455 u_register_t cm_get_scr_el3(uint32_t security_state) 1456 { 1457 cpu_context_t *ctx; 1458 el3_state_t *state; 1459 1460 ctx = cm_get_context(security_state); 1461 assert(ctx != NULL); 1462 1463 /* Populate EL3 state so that ERET jumps to the correct entry */ 1464 state = get_el3state_ctx(ctx); 1465 return read_ctx_reg(state, CTX_SCR_EL3); 1466 } 1467 1468 /******************************************************************************* 1469 * This function is used to program the context that's used for exception 1470 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1471 * the required security state 1472 ******************************************************************************/ 1473 void cm_set_next_eret_context(uint32_t security_state) 1474 { 1475 cpu_context_t *ctx; 1476 1477 ctx = cm_get_context(security_state); 1478 assert(ctx != NULL); 1479 1480 cm_set_next_context(ctx); 1481 } 1482