1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/sme.h> 28 #include <lib/extensions/spe.h> 29 #include <lib/extensions/sve.h> 30 #include <lib/extensions/sys_reg_trace.h> 31 #include <lib/extensions/trbe.h> 32 #include <lib/extensions/trf.h> 33 #include <lib/utils.h> 34 35 #if ENABLE_FEAT_TWED 36 /* Make sure delay value fits within the range(0-15) */ 37 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 38 #endif /* ENABLE_FEAT_TWED */ 39 40 static void manage_extensions_secure(cpu_context_t *ctx); 41 42 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 43 { 44 u_register_t sctlr_elx, actlr_elx; 45 46 /* 47 * Initialise SCTLR_EL1 to the reset value corresponding to the target 48 * execution state setting all fields rather than relying on the hw. 49 * Some fields have architecturally UNKNOWN reset values and these are 50 * set to zero. 51 * 52 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 53 * 54 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 55 * required by PSCI specification) 56 */ 57 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 58 if (GET_RW(ep->spsr) == MODE_RW_64) { 59 sctlr_elx |= SCTLR_EL1_RES1; 60 } else { 61 /* 62 * If the target execution state is AArch32 then the following 63 * fields need to be set. 64 * 65 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 66 * instructions are not trapped to EL1. 67 * 68 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 69 * instructions are not trapped to EL1. 70 * 71 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 72 * CP15DMB, CP15DSB, and CP15ISB instructions. 73 */ 74 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 75 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 76 } 77 78 #if ERRATA_A75_764081 79 /* 80 * If workaround of errata 764081 for Cortex-A75 is used then set 81 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 82 */ 83 sctlr_elx |= SCTLR_IESB_BIT; 84 #endif 85 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 86 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 87 88 /* 89 * Base the context ACTLR_EL1 on the current value, as it is 90 * implementation defined. The context restore process will write 91 * the value from the context to the actual register and can cause 92 * problems for processor cores that don't expect certain bits to 93 * be zero. 94 */ 95 actlr_elx = read_actlr_el1(); 96 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 97 } 98 99 /****************************************************************************** 100 * This function performs initializations that are specific to SECURE state 101 * and updates the cpu context specified by 'ctx'. 102 *****************************************************************************/ 103 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 104 { 105 u_register_t scr_el3; 106 el3_state_t *state; 107 108 state = get_el3state_ctx(ctx); 109 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 110 111 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 112 /* 113 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 114 * indicated by the interrupt routing model for BL31. 115 */ 116 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 117 #endif 118 119 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 120 /* Get Memory Tagging Extension support level */ 121 unsigned int mte = get_armv8_5_mte_support(); 122 #endif 123 /* 124 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 125 * is set, or when MTE is only implemented at EL0. 126 */ 127 #if CTX_INCLUDE_MTE_REGS 128 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 129 scr_el3 |= SCR_ATA_BIT; 130 #else 131 if (mte == MTE_IMPLEMENTED_EL0) { 132 scr_el3 |= SCR_ATA_BIT; 133 } 134 #endif /* CTX_INCLUDE_MTE_REGS */ 135 136 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 137 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) { 138 if (GET_RW(ep->spsr) != MODE_RW_64) { 139 ERROR("S-EL2 can not be used in AArch32\n."); 140 panic(); 141 } 142 143 scr_el3 |= SCR_EEL2_BIT; 144 } 145 146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 147 148 /* 149 * Initialize EL1 context registers unless SPMC is running 150 * at S-EL2. 151 */ 152 #if !SPMD_SPM_AT_SEL2 153 setup_el1_context(ctx, ep); 154 #endif 155 156 manage_extensions_secure(ctx); 157 } 158 159 #if ENABLE_RME 160 /****************************************************************************** 161 * This function performs initializations that are specific to REALM state 162 * and updates the cpu context specified by 'ctx'. 163 *****************************************************************************/ 164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 165 { 166 u_register_t scr_el3; 167 el3_state_t *state; 168 169 state = get_el3state_ctx(ctx); 170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 173 174 #if ENABLE_FEAT_CSV2_2 175 /* Enable access to the SCXTNUM_ELx registers. */ 176 scr_el3 |= SCR_EnSCXT_BIT; 177 #endif 178 179 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 180 } 181 #endif /* ENABLE_RME */ 182 183 /****************************************************************************** 184 * This function performs initializations that are specific to NON-SECURE state 185 * and updates the cpu context specified by 'ctx'. 186 *****************************************************************************/ 187 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 188 { 189 u_register_t scr_el3; 190 el3_state_t *state; 191 192 state = get_el3state_ctx(ctx); 193 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 194 195 /* SCR_NS: Set the NS bit */ 196 scr_el3 |= SCR_NS_BIT; 197 198 #if !CTX_INCLUDE_PAUTH_REGS 199 /* 200 * If the pointer authentication registers aren't saved during world 201 * switches the value of the registers can be leaked from the Secure to 202 * the Non-secure world. To prevent this, rather than enabling pointer 203 * authentication everywhere, we only enable it in the Non-secure world. 204 * 205 * If the Secure world wants to use pointer authentication, 206 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 207 */ 208 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 209 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 210 211 /* Allow access to Allocation Tags when MTE is implemented. */ 212 scr_el3 |= SCR_ATA_BIT; 213 214 #if HANDLE_EA_EL3_FIRST_NS 215 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 216 scr_el3 |= SCR_EA_BIT; 217 #endif 218 219 #if RAS_TRAP_NS_ERR_REC_ACCESS 220 /* 221 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 222 * and RAS ERX registers from EL1 and EL2(from any security state) 223 * are trapped to EL3. 224 * Set here to trap only for NS EL1/EL2 225 * 226 */ 227 scr_el3 |= SCR_TERR_BIT; 228 #endif 229 230 #if ENABLE_FEAT_CSV2_2 231 /* Enable access to the SCXTNUM_ELx registers. */ 232 scr_el3 |= SCR_EnSCXT_BIT; 233 #endif 234 235 #ifdef IMAGE_BL31 236 /* 237 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 238 * indicated by the interrupt routing model for BL31. 239 */ 240 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 241 #endif 242 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 243 244 /* Initialize EL1 context registers */ 245 setup_el1_context(ctx, ep); 246 247 /* Initialize EL2 context registers */ 248 #if CTX_INCLUDE_EL2_REGS 249 250 /* 251 * Initialize SCTLR_EL2 context register using Endianness value 252 * taken from the entrypoint attribute. 253 */ 254 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 255 sctlr_el2 |= SCTLR_EL2_RES1; 256 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 257 sctlr_el2); 258 259 /* 260 * Program the ICC_SRE_EL2 to make sure the correct bits are set 261 * when restoring NS context. 262 */ 263 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 264 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 265 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 266 icc_sre_el2); 267 268 /* 269 * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't 270 * throw anyone off who expects this to be sensible. 271 * TODO: A similar thing happens in cm_prepare_el3_exit. They should be 272 * unified with the proper PMU implementation 273 */ 274 u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & 275 PMCR_EL0_N_MASK); 276 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2); 277 #endif /* CTX_INCLUDE_EL2_REGS */ 278 } 279 280 /******************************************************************************* 281 * The following function performs initialization of the cpu_context 'ctx' 282 * for first use that is common to all security states, and sets the 283 * initial entrypoint state as specified by the entry_point_info structure. 284 * 285 * The EE and ST attributes are used to configure the endianness and secure 286 * timer availability for the new execution context. 287 ******************************************************************************/ 288 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 289 { 290 u_register_t scr_el3; 291 el3_state_t *state; 292 gp_regs_t *gp_regs; 293 294 /* Clear any residual register values from the context */ 295 zeromem(ctx, sizeof(*ctx)); 296 297 /* 298 * SCR_EL3 was initialised during reset sequence in macro 299 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 300 * affect the next EL. 301 * 302 * The following fields are initially set to zero and then updated to 303 * the required value depending on the state of the SPSR_EL3 and the 304 * Security state and entrypoint attributes of the next EL. 305 */ 306 scr_el3 = read_scr(); 307 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 308 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 309 310 /* 311 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 312 * Exception level as specified by SPSR. 313 */ 314 if (GET_RW(ep->spsr) == MODE_RW_64) { 315 scr_el3 |= SCR_RW_BIT; 316 } 317 318 /* 319 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 320 * Secure timer registers to EL3, from AArch64 state only, if specified 321 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 322 * bit always behaves as 1 (i.e. secure physical timer register access 323 * is not trapped) 324 */ 325 if (EP_GET_ST(ep->h.attr) != 0U) { 326 scr_el3 |= SCR_ST_BIT; 327 } 328 329 /* 330 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 331 * SCR_EL3.HXEn. 332 */ 333 if (is_feat_hcx_supported()) { 334 scr_el3 |= SCR_HXEn_BIT; 335 } 336 337 /* 338 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 339 * registers are trapped to EL3. 340 */ 341 #if ENABLE_FEAT_RNG_TRAP 342 scr_el3 |= SCR_TRNDR_BIT; 343 #endif 344 345 #if FAULT_INJECTION_SUPPORT 346 /* Enable fault injection from lower ELs */ 347 scr_el3 |= SCR_FIEN_BIT; 348 #endif 349 350 /* 351 * CPTR_EL3 was initialized out of reset, copy that value to the 352 * context register. 353 */ 354 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 355 356 /* 357 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 358 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 359 * next mode is Hyp. 360 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 361 * same conditions as HVC instructions and when the processor supports 362 * ARMv8.6-FGT. 363 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 364 * CNTPOFF_EL2 register under the same conditions as HVC instructions 365 * and when the processor supports ECV. 366 */ 367 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 368 || ((GET_RW(ep->spsr) != MODE_RW_64) 369 && (GET_M32(ep->spsr) == MODE32_hyp))) { 370 scr_el3 |= SCR_HCE_BIT; 371 372 if (is_feat_fgt_supported()) { 373 scr_el3 |= SCR_FGTEN_BIT; 374 } 375 376 if (get_armv8_6_ecv_support() 377 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 378 scr_el3 |= SCR_ECVEN_BIT; 379 } 380 } 381 382 #if ENABLE_FEAT_TWED 383 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 384 /* Set delay in SCR_EL3 */ 385 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 386 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 387 << SCR_TWEDEL_SHIFT); 388 389 /* Enable WFE delay */ 390 scr_el3 |= SCR_TWEDEn_BIT; 391 #endif /* ENABLE_FEAT_TWED */ 392 393 /* 394 * Populate EL3 state so that we've the right context 395 * before doing ERET 396 */ 397 state = get_el3state_ctx(ctx); 398 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 399 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 400 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 401 402 /* 403 * Store the X0-X7 value from the entrypoint into the context 404 * Use memcpy as we are in control of the layout of the structures 405 */ 406 gp_regs = get_gpregs_ctx(ctx); 407 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 408 } 409 410 /******************************************************************************* 411 * Context management library initialization routine. This library is used by 412 * runtime services to share pointers to 'cpu_context' structures for secure 413 * non-secure and realm states. Management of the structures and their associated 414 * memory is not done by the context management library e.g. the PSCI service 415 * manages the cpu context used for entry from and exit to the non-secure state. 416 * The Secure payload dispatcher service manages the context(s) corresponding to 417 * the secure state. It also uses this library to get access to the non-secure 418 * state cpu context pointers. 419 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 420 * which will be used for programming an entry into a lower EL. The same context 421 * will be used to save state upon exception entry from that EL. 422 ******************************************************************************/ 423 void __init cm_init(void) 424 { 425 /* 426 * The context management library has only global data to intialize, but 427 * that will be done when the BSS is zeroed out. 428 */ 429 } 430 431 /******************************************************************************* 432 * This is the high-level function used to initialize the cpu_context 'ctx' for 433 * first use. It performs initializations that are common to all security states 434 * and initializations specific to the security state specified in 'ep' 435 ******************************************************************************/ 436 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 437 { 438 unsigned int security_state; 439 440 assert(ctx != NULL); 441 442 /* 443 * Perform initializations that are common 444 * to all security states 445 */ 446 setup_context_common(ctx, ep); 447 448 security_state = GET_SECURITY_STATE(ep->h.attr); 449 450 /* Perform security state specific initializations */ 451 switch (security_state) { 452 case SECURE: 453 setup_secure_context(ctx, ep); 454 break; 455 #if ENABLE_RME 456 case REALM: 457 setup_realm_context(ctx, ep); 458 break; 459 #endif 460 case NON_SECURE: 461 setup_ns_context(ctx, ep); 462 break; 463 default: 464 ERROR("Invalid security state\n"); 465 panic(); 466 break; 467 } 468 } 469 470 /******************************************************************************* 471 * Enable architecture extensions on first entry to Non-secure world. 472 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 473 * it is zero. 474 ******************************************************************************/ 475 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 476 { 477 #if IMAGE_BL31 478 #if ENABLE_SPE_FOR_LOWER_ELS 479 spe_enable(el2_unused); 480 #endif 481 482 #if ENABLE_AMU 483 amu_enable(el2_unused, ctx); 484 #endif 485 486 #if ENABLE_SME_FOR_NS 487 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 488 sme_enable(ctx); 489 #elif ENABLE_SVE_FOR_NS 490 /* Enable SVE and FPU/SIMD for non-secure world. */ 491 sve_enable(ctx); 492 #endif 493 494 #if ENABLE_MPAM_FOR_LOWER_ELS 495 mpam_enable(el2_unused); 496 #endif 497 498 if (is_feat_trbe_supported()) { 499 trbe_enable(); 500 } 501 502 if (is_feat_brbe_supported()) { 503 brbe_enable(); 504 } 505 506 #if ENABLE_SYS_REG_TRACE_FOR_NS 507 sys_reg_trace_enable(ctx); 508 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 509 510 if (is_feat_trf_supported()) { 511 trf_enable(); 512 } 513 #endif 514 } 515 516 /******************************************************************************* 517 * Enable architecture extensions on first entry to Secure world. 518 ******************************************************************************/ 519 static void manage_extensions_secure(cpu_context_t *ctx) 520 { 521 #if IMAGE_BL31 522 #if ENABLE_SME_FOR_NS 523 #if ENABLE_SME_FOR_SWD 524 /* 525 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must 526 * ensure SME, SVE, and FPU/SIMD context properly managed. 527 */ 528 sme_enable(ctx); 529 #else /* ENABLE_SME_FOR_SWD */ 530 /* 531 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can 532 * safely use the associated registers. 533 */ 534 sme_disable(ctx); 535 #endif /* ENABLE_SME_FOR_SWD */ 536 #elif ENABLE_SVE_FOR_NS 537 #if ENABLE_SVE_FOR_SWD 538 /* 539 * Enable SVE and FPU in secure context, secure manager must ensure that 540 * the SVE and FPU register contexts are properly managed. 541 */ 542 sve_enable(ctx); 543 #else /* ENABLE_SVE_FOR_SWD */ 544 /* 545 * Disable SVE and FPU in secure context so non-secure world can safely 546 * use them. 547 */ 548 sve_disable(ctx); 549 #endif /* ENABLE_SVE_FOR_SWD */ 550 #endif /* ENABLE_SVE_FOR_NS */ 551 #endif /* IMAGE_BL31 */ 552 } 553 554 /******************************************************************************* 555 * The following function initializes the cpu_context for a CPU specified by 556 * its `cpu_idx` for first use, and sets the initial entrypoint state as 557 * specified by the entry_point_info structure. 558 ******************************************************************************/ 559 void cm_init_context_by_index(unsigned int cpu_idx, 560 const entry_point_info_t *ep) 561 { 562 cpu_context_t *ctx; 563 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 564 cm_setup_context(ctx, ep); 565 } 566 567 /******************************************************************************* 568 * The following function initializes the cpu_context for the current CPU 569 * for first use, and sets the initial entrypoint state as specified by the 570 * entry_point_info structure. 571 ******************************************************************************/ 572 void cm_init_my_context(const entry_point_info_t *ep) 573 { 574 cpu_context_t *ctx; 575 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 576 cm_setup_context(ctx, ep); 577 } 578 579 /******************************************************************************* 580 * Prepare the CPU system registers for first entry into realm, secure, or 581 * normal world. 582 * 583 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 584 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 585 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 586 * For all entries, the EL1 registers are initialized from the cpu_context 587 ******************************************************************************/ 588 void cm_prepare_el3_exit(uint32_t security_state) 589 { 590 u_register_t sctlr_elx, scr_el3, mdcr_el2; 591 cpu_context_t *ctx = cm_get_context(security_state); 592 bool el2_unused = false; 593 uint64_t hcr_el2 = 0U; 594 595 assert(ctx != NULL); 596 597 if (security_state == NON_SECURE) { 598 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 599 CTX_SCR_EL3); 600 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 601 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 602 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 603 CTX_SCTLR_EL1); 604 sctlr_elx &= SCTLR_EE_BIT; 605 sctlr_elx |= SCTLR_EL2_RES1; 606 #if ERRATA_A75_764081 607 /* 608 * If workaround of errata 764081 for Cortex-A75 is used 609 * then set SCTLR_EL2.IESB to enable Implicit Error 610 * Synchronization Barrier. 611 */ 612 sctlr_elx |= SCTLR_IESB_BIT; 613 #endif 614 write_sctlr_el2(sctlr_elx); 615 } else if (el_implemented(2) != EL_IMPL_NONE) { 616 el2_unused = true; 617 618 /* 619 * EL2 present but unused, need to disable safely. 620 * SCTLR_EL2 can be ignored in this case. 621 * 622 * Set EL2 register width appropriately: Set HCR_EL2 623 * field to match SCR_EL3.RW. 624 */ 625 if ((scr_el3 & SCR_RW_BIT) != 0U) 626 hcr_el2 |= HCR_RW_BIT; 627 628 /* 629 * For Armv8.3 pointer authentication feature, disable 630 * traps to EL2 when accessing key registers or using 631 * pointer authentication instructions from lower ELs. 632 */ 633 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 634 635 write_hcr_el2(hcr_el2); 636 637 /* 638 * Initialise CPTR_EL2 setting all fields rather than 639 * relying on the hw. All fields have architecturally 640 * UNKNOWN reset values. 641 * 642 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 643 * accesses to the CPACR_EL1 or CPACR from both 644 * Execution states do not trap to EL2. 645 * 646 * CPTR_EL2.TTA: Set to zero so that Non-secure System 647 * register accesses to the trace registers from both 648 * Execution states do not trap to EL2. 649 * If PE trace unit System registers are not implemented 650 * then this bit is reserved, and must be set to zero. 651 * 652 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 653 * to SIMD and floating-point functionality from both 654 * Execution states do not trap to EL2. 655 */ 656 write_cptr_el2(CPTR_EL2_RESET_VAL & 657 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 658 | CPTR_EL2_TFP_BIT)); 659 660 /* 661 * Initialise CNTHCTL_EL2. All fields are 662 * architecturally UNKNOWN on reset and are set to zero 663 * except for field(s) listed below. 664 * 665 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 666 * Hyp mode of Non-secure EL0 and EL1 accesses to the 667 * physical timer registers. 668 * 669 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 670 * Hyp mode of Non-secure EL0 and EL1 accesses to the 671 * physical counter registers. 672 */ 673 write_cnthctl_el2(CNTHCTL_RESET_VAL | 674 EL1PCEN_BIT | EL1PCTEN_BIT); 675 676 /* 677 * Initialise CNTVOFF_EL2 to zero as it resets to an 678 * architecturally UNKNOWN value. 679 */ 680 write_cntvoff_el2(0); 681 682 /* 683 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 684 * MPIDR_EL1 respectively. 685 */ 686 write_vpidr_el2(read_midr_el1()); 687 write_vmpidr_el2(read_mpidr_el1()); 688 689 /* 690 * Initialise VTTBR_EL2. All fields are architecturally 691 * UNKNOWN on reset. 692 * 693 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 694 * 2 address translation is disabled, cache maintenance 695 * operations depend on the VMID. 696 * 697 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 698 * translation is disabled. 699 */ 700 write_vttbr_el2(VTTBR_RESET_VAL & 701 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 702 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 703 704 /* 705 * Initialise MDCR_EL2, setting all fields rather than 706 * relying on hw. Some fields are architecturally 707 * UNKNOWN on reset. 708 * 709 * MDCR_EL2.HLP: Set to one so that event counter 710 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 711 * occurs on the increment that changes 712 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 713 * implemented. This bit is RES0 in versions of the 714 * architecture earlier than ARMv8.5, setting it to 1 715 * doesn't have any effect on them. 716 * 717 * MDCR_EL2.TTRF: Set to zero so that access to Trace 718 * Filter Control register TRFCR_EL1 at EL1 is not 719 * trapped to EL2. This bit is RES0 in versions of 720 * the architecture earlier than ARMv8.4. 721 * 722 * MDCR_EL2.HPMD: Set to one so that event counting is 723 * prohibited at EL2. This bit is RES0 in versions of 724 * the architecture earlier than ARMv8.1, setting it 725 * to 1 doesn't have any effect on them. 726 * 727 * MDCR_EL2.TPMS: Set to zero so that accesses to 728 * Statistical Profiling control registers from EL1 729 * do not trap to EL2. This bit is RES0 when SPE is 730 * not implemented. 731 * 732 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 733 * EL1 System register accesses to the Debug ROM 734 * registers are not trapped to EL2. 735 * 736 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 737 * System register accesses to the powerdown debug 738 * registers are not trapped to EL2. 739 * 740 * MDCR_EL2.TDA: Set to zero so that System register 741 * accesses to the debug registers do not trap to EL2. 742 * 743 * MDCR_EL2.TDE: Set to zero so that debug exceptions 744 * are not routed to EL2. 745 * 746 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 747 * Monitors. 748 * 749 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 750 * EL1 accesses to all Performance Monitors registers 751 * are not trapped to EL2. 752 * 753 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 754 * and EL1 accesses to the PMCR_EL0 or PMCR are not 755 * trapped to EL2. 756 * 757 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 758 * architecturally-defined reset value. 759 * 760 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 761 * owning exception level is NS-EL1 and, tracing is 762 * prohibited at NS-EL2. These bits are RES0 when 763 * FEAT_TRBE is not implemented. 764 */ 765 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 766 MDCR_EL2_HPMD) | 767 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 768 >> PMCR_EL0_N_SHIFT)) & 769 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 770 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 771 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 772 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 773 MDCR_EL2_TPMCR_BIT | 774 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 775 776 write_mdcr_el2(mdcr_el2); 777 778 /* 779 * Initialise HSTR_EL2. All fields are architecturally 780 * UNKNOWN on reset. 781 * 782 * HSTR_EL2.T<n>: Set all these fields to zero so that 783 * Non-secure EL0 or EL1 accesses to System registers 784 * do not trap to EL2. 785 */ 786 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 787 /* 788 * Initialise CNTHP_CTL_EL2. All fields are 789 * architecturally UNKNOWN on reset. 790 * 791 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 792 * physical timer and prevent timer interrupts. 793 */ 794 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 795 ~(CNTHP_CTL_ENABLE_BIT)); 796 } 797 manage_extensions_nonsecure(el2_unused, ctx); 798 } 799 800 cm_el1_sysregs_context_restore(security_state); 801 cm_set_next_eret_context(security_state); 802 } 803 804 #if CTX_INCLUDE_EL2_REGS 805 806 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 807 { 808 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 809 if (is_feat_amu_supported()) { 810 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 811 } 812 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 813 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 814 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 815 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 816 } 817 818 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 819 { 820 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 821 if (is_feat_amu_supported()) { 822 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 823 } 824 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 825 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 826 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 827 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 828 } 829 830 /******************************************************************************* 831 * Save EL2 sysreg context 832 ******************************************************************************/ 833 void cm_el2_sysregs_context_save(uint32_t security_state) 834 { 835 u_register_t scr_el3 = read_scr(); 836 837 /* 838 * Always save the non-secure and realm EL2 context, only save the 839 * S-EL2 context if S-EL2 is enabled. 840 */ 841 if ((security_state != SECURE) || 842 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 843 cpu_context_t *ctx; 844 el2_sysregs_t *el2_sysregs_ctx; 845 846 ctx = cm_get_context(security_state); 847 assert(ctx != NULL); 848 849 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 850 851 el2_sysregs_context_save_common(el2_sysregs_ctx); 852 #if ENABLE_SPE_FOR_LOWER_ELS 853 el2_sysregs_context_save_spe(el2_sysregs_ctx); 854 #endif 855 #if CTX_INCLUDE_MTE_REGS 856 el2_sysregs_context_save_mte(el2_sysregs_ctx); 857 #endif 858 #if ENABLE_MPAM_FOR_LOWER_ELS 859 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 860 #endif 861 862 if (is_feat_fgt_supported()) { 863 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 864 } 865 866 #if ENABLE_FEAT_ECV 867 el2_sysregs_context_save_ecv(el2_sysregs_ctx); 868 #endif 869 #if ENABLE_FEAT_VHE 870 el2_sysregs_context_save_vhe(el2_sysregs_ctx); 871 #endif 872 #if RAS_EXTENSION 873 el2_sysregs_context_save_ras(el2_sysregs_ctx); 874 #endif 875 #if CTX_INCLUDE_NEVE_REGS 876 el2_sysregs_context_save_nv2(el2_sysregs_ctx); 877 #endif 878 if (is_feat_trf_supported()) { 879 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 880 } 881 #if ENABLE_FEAT_CSV2_2 882 el2_sysregs_context_save_csv2(el2_sysregs_ctx); 883 #endif 884 if (is_feat_hcx_supported()) { 885 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 886 } 887 } 888 } 889 890 /******************************************************************************* 891 * Restore EL2 sysreg context 892 ******************************************************************************/ 893 void cm_el2_sysregs_context_restore(uint32_t security_state) 894 { 895 u_register_t scr_el3 = read_scr(); 896 897 /* 898 * Always restore the non-secure and realm EL2 context, only restore the 899 * S-EL2 context if S-EL2 is enabled. 900 */ 901 if ((security_state != SECURE) || 902 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 903 cpu_context_t *ctx; 904 el2_sysregs_t *el2_sysregs_ctx; 905 906 ctx = cm_get_context(security_state); 907 assert(ctx != NULL); 908 909 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 910 911 el2_sysregs_context_restore_common(el2_sysregs_ctx); 912 #if ENABLE_SPE_FOR_LOWER_ELS 913 el2_sysregs_context_restore_spe(el2_sysregs_ctx); 914 #endif 915 #if CTX_INCLUDE_MTE_REGS 916 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 917 #endif 918 #if ENABLE_MPAM_FOR_LOWER_ELS 919 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 920 #endif 921 922 if (is_feat_fgt_supported()) { 923 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 924 } 925 926 #if ENABLE_FEAT_ECV 927 el2_sysregs_context_restore_ecv(el2_sysregs_ctx); 928 #endif 929 #if ENABLE_FEAT_VHE 930 el2_sysregs_context_restore_vhe(el2_sysregs_ctx); 931 #endif 932 #if RAS_EXTENSION 933 el2_sysregs_context_restore_ras(el2_sysregs_ctx); 934 #endif 935 #if CTX_INCLUDE_NEVE_REGS 936 el2_sysregs_context_restore_nv2(el2_sysregs_ctx); 937 #endif 938 if (is_feat_trf_supported()) { 939 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 940 } 941 #if ENABLE_FEAT_CSV2_2 942 el2_sysregs_context_restore_csv2(el2_sysregs_ctx); 943 #endif 944 if (is_feat_hcx_supported()) { 945 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 946 } 947 } 948 } 949 #endif /* CTX_INCLUDE_EL2_REGS */ 950 951 /******************************************************************************* 952 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 953 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 954 * updating EL1 and EL2 registers. Otherwise, it calls the generic 955 * cm_prepare_el3_exit function. 956 ******************************************************************************/ 957 void cm_prepare_el3_exit_ns(void) 958 { 959 #if CTX_INCLUDE_EL2_REGS 960 cpu_context_t *ctx = cm_get_context(NON_SECURE); 961 assert(ctx != NULL); 962 963 /* Assert that EL2 is used. */ 964 #if ENABLE_ASSERTIONS 965 el3_state_t *state = get_el3state_ctx(ctx); 966 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 967 #endif 968 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 969 (el_implemented(2U) != EL_IMPL_NONE)); 970 971 /* 972 * Currently some extensions are configured using 973 * direct register updates. Therefore, do this here 974 * instead of when setting up context. 975 */ 976 manage_extensions_nonsecure(0, ctx); 977 978 /* 979 * Set the NS bit to be able to access the ICC_SRE_EL2 980 * register when restoring context. 981 */ 982 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 983 984 /* 985 * Ensure the NS bit change is committed before the EL2/EL1 986 * state restoration. 987 */ 988 isb(); 989 990 /* Restore EL2 and EL1 sysreg contexts */ 991 cm_el2_sysregs_context_restore(NON_SECURE); 992 cm_el1_sysregs_context_restore(NON_SECURE); 993 cm_set_next_eret_context(NON_SECURE); 994 #else 995 cm_prepare_el3_exit(NON_SECURE); 996 #endif /* CTX_INCLUDE_EL2_REGS */ 997 } 998 999 /******************************************************************************* 1000 * The next four functions are used by runtime services to save and restore 1001 * EL1 context on the 'cpu_context' structure for the specified security 1002 * state. 1003 ******************************************************************************/ 1004 void cm_el1_sysregs_context_save(uint32_t security_state) 1005 { 1006 cpu_context_t *ctx; 1007 1008 ctx = cm_get_context(security_state); 1009 assert(ctx != NULL); 1010 1011 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1012 1013 #if IMAGE_BL31 1014 if (security_state == SECURE) 1015 PUBLISH_EVENT(cm_exited_secure_world); 1016 else 1017 PUBLISH_EVENT(cm_exited_normal_world); 1018 #endif 1019 } 1020 1021 void cm_el1_sysregs_context_restore(uint32_t security_state) 1022 { 1023 cpu_context_t *ctx; 1024 1025 ctx = cm_get_context(security_state); 1026 assert(ctx != NULL); 1027 1028 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1029 1030 #if IMAGE_BL31 1031 if (security_state == SECURE) 1032 PUBLISH_EVENT(cm_entering_secure_world); 1033 else 1034 PUBLISH_EVENT(cm_entering_normal_world); 1035 #endif 1036 } 1037 1038 /******************************************************************************* 1039 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1040 * given security state with the given entrypoint 1041 ******************************************************************************/ 1042 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1043 { 1044 cpu_context_t *ctx; 1045 el3_state_t *state; 1046 1047 ctx = cm_get_context(security_state); 1048 assert(ctx != NULL); 1049 1050 /* Populate EL3 state so that ERET jumps to the correct entry */ 1051 state = get_el3state_ctx(ctx); 1052 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1053 } 1054 1055 /******************************************************************************* 1056 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1057 * pertaining to the given security state 1058 ******************************************************************************/ 1059 void cm_set_elr_spsr_el3(uint32_t security_state, 1060 uintptr_t entrypoint, uint32_t spsr) 1061 { 1062 cpu_context_t *ctx; 1063 el3_state_t *state; 1064 1065 ctx = cm_get_context(security_state); 1066 assert(ctx != NULL); 1067 1068 /* Populate EL3 state so that ERET jumps to the correct entry */ 1069 state = get_el3state_ctx(ctx); 1070 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1071 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1072 } 1073 1074 /******************************************************************************* 1075 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1076 * pertaining to the given security state using the value and bit position 1077 * specified in the parameters. It preserves all other bits. 1078 ******************************************************************************/ 1079 void cm_write_scr_el3_bit(uint32_t security_state, 1080 uint32_t bit_pos, 1081 uint32_t value) 1082 { 1083 cpu_context_t *ctx; 1084 el3_state_t *state; 1085 u_register_t scr_el3; 1086 1087 ctx = cm_get_context(security_state); 1088 assert(ctx != NULL); 1089 1090 /* Ensure that the bit position is a valid one */ 1091 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1092 1093 /* Ensure that the 'value' is only a bit wide */ 1094 assert(value <= 1U); 1095 1096 /* 1097 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1098 * and set it to its new value. 1099 */ 1100 state = get_el3state_ctx(ctx); 1101 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1102 scr_el3 &= ~(1UL << bit_pos); 1103 scr_el3 |= (u_register_t)value << bit_pos; 1104 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1105 } 1106 1107 /******************************************************************************* 1108 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1109 * given security state. 1110 ******************************************************************************/ 1111 u_register_t cm_get_scr_el3(uint32_t security_state) 1112 { 1113 cpu_context_t *ctx; 1114 el3_state_t *state; 1115 1116 ctx = cm_get_context(security_state); 1117 assert(ctx != NULL); 1118 1119 /* Populate EL3 state so that ERET jumps to the correct entry */ 1120 state = get_el3state_ctx(ctx); 1121 return read_ctx_reg(state, CTX_SCR_EL3); 1122 } 1123 1124 /******************************************************************************* 1125 * This function is used to program the context that's used for exception 1126 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1127 * the required security state 1128 ******************************************************************************/ 1129 void cm_set_next_eret_context(uint32_t security_state) 1130 { 1131 cpu_context_t *ctx; 1132 1133 ctx = cm_get_context(security_state); 1134 assert(ctx != NULL); 1135 1136 cm_set_next_context(ctx); 1137 } 1138