1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <bl31/interrupt_mgmt.h> 16 #include <common/bl_common.h> 17 #include <context.h> 18 #include <lib/el3_runtime/context_mgmt.h> 19 #include <lib/el3_runtime/pubsub_events.h> 20 #include <lib/extensions/amu.h> 21 #include <lib/extensions/mpam.h> 22 #include <lib/extensions/spe.h> 23 #include <lib/extensions/sve.h> 24 #include <lib/utils.h> 25 #include <plat/common/platform.h> 26 #include <smccc_helpers.h> 27 28 29 /******************************************************************************* 30 * Context management library initialisation routine. This library is used by 31 * runtime services to share pointers to 'cpu_context' structures for the secure 32 * and non-secure states. Management of the structures and their associated 33 * memory is not done by the context management library e.g. the PSCI service 34 * manages the cpu context used for entry from and exit to the non-secure state. 35 * The Secure payload dispatcher service manages the context(s) corresponding to 36 * the secure state. It also uses this library to get access to the non-secure 37 * state cpu context pointers. 38 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 39 * which will used for programming an entry into a lower EL. The same context 40 * will used to save state upon exception entry from that EL. 41 ******************************************************************************/ 42 void __init cm_init(void) 43 { 44 /* 45 * The context management library has only global data to intialize, but 46 * that will be done when the BSS is zeroed out 47 */ 48 } 49 50 /******************************************************************************* 51 * The following function initializes the cpu_context 'ctx' for 52 * first use, and sets the initial entrypoint state as specified by the 53 * entry_point_info structure. 54 * 55 * The security state to initialize is determined by the SECURE attribute 56 * of the entry_point_info. 57 * 58 * The EE and ST attributes are used to configure the endianness and secure 59 * timer availability for the new execution context. 60 * 61 * To prepare the register state for entry call cm_prepare_el3_exit() and 62 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 63 * cm_e1_sysreg_context_restore(). 64 ******************************************************************************/ 65 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 66 { 67 unsigned int security_state; 68 uint32_t scr_el3, pmcr_el0; 69 el3_state_t *state; 70 gp_regs_t *gp_regs; 71 unsigned long sctlr_elx, actlr_elx; 72 73 assert(ctx != NULL); 74 75 security_state = GET_SECURITY_STATE(ep->h.attr); 76 77 /* Clear any residual register values from the context */ 78 zeromem(ctx, sizeof(*ctx)); 79 80 /* 81 * SCR_EL3 was initialised during reset sequence in macro 82 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 83 * affect the next EL. 84 * 85 * The following fields are initially set to zero and then updated to 86 * the required value depending on the state of the SPSR_EL3 and the 87 * Security state and entrypoint attributes of the next EL. 88 */ 89 scr_el3 = (uint32_t)read_scr(); 90 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 91 SCR_ST_BIT | SCR_HCE_BIT); 92 /* 93 * SCR_NS: Set the security state of the next EL. 94 */ 95 if (security_state != SECURE) 96 scr_el3 |= SCR_NS_BIT; 97 /* 98 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 99 * Exception level as specified by SPSR. 100 */ 101 if (GET_RW(ep->spsr) == MODE_RW_64) 102 scr_el3 |= SCR_RW_BIT; 103 /* 104 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 105 * Secure timer registers to EL3, from AArch64 state only, if specified 106 * by the entrypoint attributes. 107 */ 108 if (EP_GET_ST(ep->h.attr) != 0U) 109 scr_el3 |= SCR_ST_BIT; 110 111 #if !HANDLE_EA_EL3_FIRST 112 /* 113 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 114 * to EL3 when executing at a lower EL. When executing at EL3, External 115 * Aborts are taken to EL3. 116 */ 117 scr_el3 &= ~SCR_EA_BIT; 118 #endif 119 120 #if FAULT_INJECTION_SUPPORT 121 /* Enable fault injection from lower ELs */ 122 scr_el3 |= SCR_FIEN_BIT; 123 #endif 124 125 #ifdef IMAGE_BL31 126 /* 127 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 128 * indicated by the interrupt routing model for BL31. 129 */ 130 scr_el3 |= get_scr_el3_from_routing_model(security_state); 131 #endif 132 133 /* 134 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 135 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 136 * next mode is Hyp. 137 */ 138 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 139 || ((GET_RW(ep->spsr) != MODE_RW_64) 140 && (GET_M32(ep->spsr) == MODE32_hyp))) { 141 scr_el3 |= SCR_HCE_BIT; 142 } 143 144 /* 145 * Initialise SCTLR_EL1 to the reset value corresponding to the target 146 * execution state setting all fields rather than relying of the hw. 147 * Some fields have architecturally UNKNOWN reset values and these are 148 * set to zero. 149 * 150 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 151 * 152 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 153 * required by PSCI specification) 154 */ 155 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 156 if (GET_RW(ep->spsr) == MODE_RW_64) 157 sctlr_elx |= SCTLR_EL1_RES1; 158 else { 159 /* 160 * If the target execution state is AArch32 then the following 161 * fields need to be set. 162 * 163 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 164 * instructions are not trapped to EL1. 165 * 166 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 167 * instructions are not trapped to EL1. 168 * 169 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 170 * CP15DMB, CP15DSB, and CP15ISB instructions. 171 */ 172 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 173 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 174 } 175 176 #if ERRATA_A75_764081 177 /* 178 * If workaround of errata 764081 for Cortex-A75 is used then set 179 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 180 */ 181 sctlr_elx |= SCTLR_IESB_BIT; 182 #endif 183 184 /* 185 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 186 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 187 * are not part of the stored cpu_context. 188 */ 189 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 190 191 /* 192 * Base the context ACTLR_EL1 on the current value, as it is 193 * implementation defined. The context restore process will write 194 * the value from the context to the actual register and can cause 195 * problems for processor cores that don't expect certain bits to 196 * be zero. 197 */ 198 actlr_elx = read_actlr_el1(); 199 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 200 201 if (security_state == SECURE) { 202 /* 203 * Initialise PMCR_EL0 for secure context only, setting all 204 * fields rather than relying on hw. Some fields are 205 * architecturally UNKNOWN on reset. 206 * 207 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 208 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 209 * that changes PMCCNTR_EL0[63] from 1 to 0. 210 * 211 * PMCR_EL0.DP: Set to one so that the cycle counter, 212 * PMCCNTR_EL0 does not count when event counting is prohibited. 213 * 214 * PMCR_EL0.X: Set to zero to disable export of events. 215 * 216 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 217 * counts on every clock cycle. 218 */ 219 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT 220 | PMCR_EL0_DP_BIT) 221 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)); 222 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0); 223 } 224 225 /* Populate EL3 state so that we've the right context before doing ERET */ 226 state = get_el3state_ctx(ctx); 227 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 228 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 229 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 230 231 /* 232 * Store the X0-X7 value from the entrypoint into the context 233 * Use memcpy as we are in control of the layout of the structures 234 */ 235 gp_regs = get_gpregs_ctx(ctx); 236 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 237 } 238 239 /******************************************************************************* 240 * Enable architecture extensions on first entry to Non-secure world. 241 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 242 * it is zero. 243 ******************************************************************************/ 244 static void enable_extensions_nonsecure(bool el2_unused) 245 { 246 #if IMAGE_BL31 247 #if ENABLE_SPE_FOR_LOWER_ELS 248 spe_enable(el2_unused); 249 #endif 250 251 #if ENABLE_AMU 252 amu_enable(el2_unused); 253 #endif 254 255 #if ENABLE_SVE_FOR_NS 256 sve_enable(el2_unused); 257 #endif 258 259 #if ENABLE_MPAM_FOR_LOWER_ELS 260 mpam_enable(el2_unused); 261 #endif 262 #endif 263 } 264 265 /******************************************************************************* 266 * The following function initializes the cpu_context for a CPU specified by 267 * its `cpu_idx` for first use, and sets the initial entrypoint state as 268 * specified by the entry_point_info structure. 269 ******************************************************************************/ 270 void cm_init_context_by_index(unsigned int cpu_idx, 271 const entry_point_info_t *ep) 272 { 273 cpu_context_t *ctx; 274 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 275 cm_setup_context(ctx, ep); 276 } 277 278 /******************************************************************************* 279 * The following function initializes the cpu_context for the current CPU 280 * for first use, and sets the initial entrypoint state as specified by the 281 * entry_point_info structure. 282 ******************************************************************************/ 283 void cm_init_my_context(const entry_point_info_t *ep) 284 { 285 cpu_context_t *ctx; 286 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 287 cm_setup_context(ctx, ep); 288 } 289 290 /******************************************************************************* 291 * Prepare the CPU system registers for first entry into secure or normal world 292 * 293 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 294 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 295 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 296 * For all entries, the EL1 registers are initialized from the cpu_context 297 ******************************************************************************/ 298 void cm_prepare_el3_exit(uint32_t security_state) 299 { 300 uint32_t sctlr_elx, scr_el3, mdcr_el2; 301 cpu_context_t *ctx = cm_get_context(security_state); 302 bool el2_unused = false; 303 uint64_t hcr_el2 = 0U; 304 305 assert(ctx != NULL); 306 307 if (security_state == NON_SECURE) { 308 scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx), 309 CTX_SCR_EL3); 310 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 311 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 312 sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx), 313 CTX_SCTLR_EL1); 314 sctlr_elx &= SCTLR_EE_BIT; 315 sctlr_elx |= SCTLR_EL2_RES1; 316 #if ERRATA_A75_764081 317 /* 318 * If workaround of errata 764081 for Cortex-A75 is used 319 * then set SCTLR_EL2.IESB to enable Implicit Error 320 * Synchronization Barrier. 321 */ 322 sctlr_elx |= SCTLR_IESB_BIT; 323 #endif 324 write_sctlr_el2(sctlr_elx); 325 } else if (el_implemented(2) != EL_IMPL_NONE) { 326 el2_unused = true; 327 328 /* 329 * EL2 present but unused, need to disable safely. 330 * SCTLR_EL2 can be ignored in this case. 331 * 332 * Set EL2 register width appropriately: Set HCR_EL2 333 * field to match SCR_EL3.RW. 334 */ 335 if ((scr_el3 & SCR_RW_BIT) != 0U) 336 hcr_el2 |= HCR_RW_BIT; 337 338 /* 339 * For Armv8.3 pointer authentication feature, disable 340 * traps to EL2 when accessing key registers or using 341 * pointer authentication instructions from lower ELs. 342 */ 343 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 344 345 write_hcr_el2(hcr_el2); 346 347 /* 348 * Initialise CPTR_EL2 setting all fields rather than 349 * relying on the hw. All fields have architecturally 350 * UNKNOWN reset values. 351 * 352 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 353 * accesses to the CPACR_EL1 or CPACR from both 354 * Execution states do not trap to EL2. 355 * 356 * CPTR_EL2.TTA: Set to zero so that Non-secure System 357 * register accesses to the trace registers from both 358 * Execution states do not trap to EL2. 359 * 360 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 361 * to SIMD and floating-point functionality from both 362 * Execution states do not trap to EL2. 363 */ 364 write_cptr_el2(CPTR_EL2_RESET_VAL & 365 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 366 | CPTR_EL2_TFP_BIT)); 367 368 /* 369 * Initialise CNTHCTL_EL2. All fields are 370 * architecturally UNKNOWN on reset and are set to zero 371 * except for field(s) listed below. 372 * 373 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 374 * Hyp mode of Non-secure EL0 and EL1 accesses to the 375 * physical timer registers. 376 * 377 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 378 * Hyp mode of Non-secure EL0 and EL1 accesses to the 379 * physical counter registers. 380 */ 381 write_cnthctl_el2(CNTHCTL_RESET_VAL | 382 EL1PCEN_BIT | EL1PCTEN_BIT); 383 384 /* 385 * Initialise CNTVOFF_EL2 to zero as it resets to an 386 * architecturally UNKNOWN value. 387 */ 388 write_cntvoff_el2(0); 389 390 /* 391 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 392 * MPIDR_EL1 respectively. 393 */ 394 write_vpidr_el2(read_midr_el1()); 395 write_vmpidr_el2(read_mpidr_el1()); 396 397 /* 398 * Initialise VTTBR_EL2. All fields are architecturally 399 * UNKNOWN on reset. 400 * 401 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 402 * 2 address translation is disabled, cache maintenance 403 * operations depend on the VMID. 404 * 405 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 406 * translation is disabled. 407 */ 408 write_vttbr_el2(VTTBR_RESET_VAL & 409 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 410 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 411 412 /* 413 * Initialise MDCR_EL2, setting all fields rather than 414 * relying on hw. Some fields are architecturally 415 * UNKNOWN on reset. 416 * 417 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 418 * EL1 System register accesses to the Debug ROM 419 * registers are not trapped to EL2. 420 * 421 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 422 * System register accesses to the powerdown debug 423 * registers are not trapped to EL2. 424 * 425 * MDCR_EL2.TDA: Set to zero so that System register 426 * accesses to the debug registers do not trap to EL2. 427 * 428 * MDCR_EL2.TDE: Set to zero so that debug exceptions 429 * are not routed to EL2. 430 * 431 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 432 * Monitors. 433 * 434 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 435 * EL1 accesses to all Performance Monitors registers 436 * are not trapped to EL2. 437 * 438 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 439 * and EL1 accesses to the PMCR_EL0 or PMCR are not 440 * trapped to EL2. 441 * 442 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 443 * architecturally-defined reset value. 444 */ 445 mdcr_el2 = ((MDCR_EL2_RESET_VAL | 446 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 447 >> PMCR_EL0_N_SHIFT)) & 448 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT 449 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT 450 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT 451 | MDCR_EL2_TPMCR_BIT)); 452 453 write_mdcr_el2(mdcr_el2); 454 455 /* 456 * Initialise HSTR_EL2. All fields are architecturally 457 * UNKNOWN on reset. 458 * 459 * HSTR_EL2.T<n>: Set all these fields to zero so that 460 * Non-secure EL0 or EL1 accesses to System registers 461 * do not trap to EL2. 462 */ 463 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 464 /* 465 * Initialise CNTHP_CTL_EL2. All fields are 466 * architecturally UNKNOWN on reset. 467 * 468 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 469 * physical timer and prevent timer interrupts. 470 */ 471 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 472 ~(CNTHP_CTL_ENABLE_BIT)); 473 } 474 enable_extensions_nonsecure(el2_unused); 475 } 476 477 cm_el1_sysregs_context_restore(security_state); 478 cm_set_next_eret_context(security_state); 479 } 480 481 /******************************************************************************* 482 * The next four functions are used by runtime services to save and restore 483 * EL1 context on the 'cpu_context' structure for the specified security 484 * state. 485 ******************************************************************************/ 486 void cm_el1_sysregs_context_save(uint32_t security_state) 487 { 488 cpu_context_t *ctx; 489 490 ctx = cm_get_context(security_state); 491 assert(ctx != NULL); 492 493 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 494 495 #if IMAGE_BL31 496 if (security_state == SECURE) 497 PUBLISH_EVENT(cm_exited_secure_world); 498 else 499 PUBLISH_EVENT(cm_exited_normal_world); 500 #endif 501 } 502 503 void cm_el1_sysregs_context_restore(uint32_t security_state) 504 { 505 cpu_context_t *ctx; 506 507 ctx = cm_get_context(security_state); 508 assert(ctx != NULL); 509 510 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 511 512 #if IMAGE_BL31 513 if (security_state == SECURE) 514 PUBLISH_EVENT(cm_entering_secure_world); 515 else 516 PUBLISH_EVENT(cm_entering_normal_world); 517 #endif 518 } 519 520 /******************************************************************************* 521 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 522 * given security state with the given entrypoint 523 ******************************************************************************/ 524 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 525 { 526 cpu_context_t *ctx; 527 el3_state_t *state; 528 529 ctx = cm_get_context(security_state); 530 assert(ctx != NULL); 531 532 /* Populate EL3 state so that ERET jumps to the correct entry */ 533 state = get_el3state_ctx(ctx); 534 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 535 } 536 537 /******************************************************************************* 538 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 539 * pertaining to the given security state 540 ******************************************************************************/ 541 void cm_set_elr_spsr_el3(uint32_t security_state, 542 uintptr_t entrypoint, uint32_t spsr) 543 { 544 cpu_context_t *ctx; 545 el3_state_t *state; 546 547 ctx = cm_get_context(security_state); 548 assert(ctx != NULL); 549 550 /* Populate EL3 state so that ERET jumps to the correct entry */ 551 state = get_el3state_ctx(ctx); 552 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 553 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 554 } 555 556 /******************************************************************************* 557 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 558 * pertaining to the given security state using the value and bit position 559 * specified in the parameters. It preserves all other bits. 560 ******************************************************************************/ 561 void cm_write_scr_el3_bit(uint32_t security_state, 562 uint32_t bit_pos, 563 uint32_t value) 564 { 565 cpu_context_t *ctx; 566 el3_state_t *state; 567 uint32_t scr_el3; 568 569 ctx = cm_get_context(security_state); 570 assert(ctx != NULL); 571 572 /* Ensure that the bit position is a valid one */ 573 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 574 575 /* Ensure that the 'value' is only a bit wide */ 576 assert(value <= 1U); 577 578 /* 579 * Get the SCR_EL3 value from the cpu context, clear the desired bit 580 * and set it to its new value. 581 */ 582 state = get_el3state_ctx(ctx); 583 scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 584 scr_el3 &= ~(1U << bit_pos); 585 scr_el3 |= value << bit_pos; 586 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 587 } 588 589 /******************************************************************************* 590 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 591 * given security state. 592 ******************************************************************************/ 593 uint32_t cm_get_scr_el3(uint32_t security_state) 594 { 595 cpu_context_t *ctx; 596 el3_state_t *state; 597 598 ctx = cm_get_context(security_state); 599 assert(ctx != NULL); 600 601 /* Populate EL3 state so that ERET jumps to the correct entry */ 602 state = get_el3state_ctx(ctx); 603 return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 604 } 605 606 /******************************************************************************* 607 * This function is used to program the context that's used for exception 608 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 609 * the required security state 610 ******************************************************************************/ 611 void cm_set_next_eret_context(uint32_t security_state) 612 { 613 cpu_context_t *ctx; 614 615 ctx = cm_get_context(security_state); 616 assert(ctx != NULL); 617 618 cm_set_next_context(ctx); 619 } 620