1 /* 2 * Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/cpa2.h> 30 #include <lib/extensions/debug_v8p9.h> 31 #include <lib/extensions/fgt2.h> 32 #include <lib/extensions/idte3.h> 33 #include <lib/extensions/mpam.h> 34 #include <lib/extensions/pauth.h> 35 #include <lib/extensions/pmuv3.h> 36 #include <lib/extensions/sme.h> 37 #include <lib/extensions/spe.h> 38 #include <lib/extensions/sve.h> 39 #include <lib/extensions/sysreg128.h> 40 #include <lib/extensions/sys_reg_trace.h> 41 #include <lib/extensions/tcr2.h> 42 #include <lib/extensions/trbe.h> 43 #include <lib/extensions/trf.h> 44 #include <lib/utils.h> 45 46 #if ENABLE_FEAT_TWED 47 /* Make sure delay value fits within the range(0-15) */ 48 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 49 #endif /* ENABLE_FEAT_TWED */ 50 51 per_world_context_t per_world_context[CPU_CONTEXT_NUM]; 52 PER_CPU_DEFINE(world_amu_regs_t, world_amu_ctx[CPU_CONTEXT_NUM]); 53 54 static void manage_extensions_nonsecure(cpu_context_t *ctx); 55 static void manage_extensions_secure(cpu_context_t *ctx); 56 57 /* 58 * Set up EL1 context unless there is something running at EL2 and we must 59 * context switch. 60 */ 61 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 62 { 63 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 64 u_register_t sctlr_elx, actlr_elx; 65 66 /* 67 * Initialise SCTLR_EL1 to the reset value corresponding to the target 68 * execution state setting all fields rather than relying on the hw. 69 * Some fields have architecturally UNKNOWN reset values and these are 70 * set to zero. 71 * 72 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 73 * 74 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 75 * required by PSCI specification) 76 */ 77 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 78 if (GET_RW(ep->spsr) == MODE_RW_64) { 79 sctlr_elx |= SCTLR_EL1_RES1; 80 } else { 81 /* 82 * If the target execution state is AArch32 then the following 83 * fields need to be set. 84 * 85 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 86 * instructions are not trapped to EL1. 87 * 88 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 89 * instructions are not trapped to EL1. 90 * 91 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 92 * CP15DMB, CP15DSB, and CP15ISB instructions. 93 */ 94 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 95 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 96 } 97 98 /* 99 * If workaround of errata 764081 for Cortex-A75 is used then set 100 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 101 */ 102 if (errata_a75_764081_applies()) { 103 sctlr_elx |= SCTLR_IESB_BIT; 104 } 105 106 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 107 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 108 109 /* 110 * Base the context ACTLR_EL1 on the current value, as it is 111 * implementation defined. The context restore process will write 112 * the value from the context to the actual register and can cause 113 * problems for processor cores that don't expect certain bits to 114 * be zero. 115 */ 116 actlr_elx = read_actlr_el1(); 117 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 118 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 119 } 120 121 /* 122 * The lower-EL context is zeroed so that no stale values leak to a world. 123 * It is assumed that an all-zero lower-EL context is good enough for it 124 * to boot correctly. However, there are very few registers where this 125 * is not true and some values need to be (re)created. 126 */ 127 static void setup_el2_context(cpu_context_t *ctx) 128 { 129 #if CTX_INCLUDE_EL2_REGS && IMAGE_BL31 130 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 131 132 /* 133 * These bits are set in the gicv3 driver. Losing them (especially the 134 * SRE bit) is problematic for all worlds. Henceforth recreate them. 135 */ 136 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 137 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 138 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 139 140 /* 141 * The actlr_el2 register can be initialized in platform's reset handler 142 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 143 */ 144 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 145 146 write_el2_ctx_common(el2_ctx, sctlr_el2, SCTLR_EL2_RES1); 147 148 /* 149 * Initialize registers with known disabled init values. 150 * 151 * As their value is zeroed at init, there is a chance that this can 152 * lead to unexpected behavior in lower ELs that do not initialise these 153 * registers themselves. 154 * 155 * NOTE: this is duplicate, and mutually exclusive, of the same writes 156 * to setup_el2_regs(). They must be kept in sync. 157 * 158 * Some registers' disabled init value is all zeroes which is carried 159 * forward from init. These are: 160 * * HCRX_EL2 161 */ 162 if (is_feat_fgt_supported()) { 163 write_el2_ctx_fgt(el2_ctx, hfgitr_el2, HFGITR_EL2_INIT_VAL); 164 write_el2_ctx_fgt(el2_ctx, hfgrtr_el2, HFGRTR_EL2_INIT_VAL); 165 write_el2_ctx_fgt(el2_ctx, hfgwtr_el2, HFGWTR_EL2_INIT_VAL); 166 } 167 #endif 168 } 169 170 /* 171 * Write safe values into EL2 registers that reset into an UNKNOWN state. 172 * 173 * As their value is UNKNOWN at init, there is a chance that this can lead to 174 * unexpected behavior in lower ELs that do not initialise these registers 175 * themselves. 176 * 177 * NOTE: this is duplicate, and mutually exclusive, of the same writes to 178 * setup_el2_context(). They must be kept in sync. 179 */ 180 static void setup_el2_regs(void) 181 { 182 #if !(CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 183 if (is_feat_hcx_supported()) { 184 write_hcrx_el2(HCRX_EL2_INIT_VAL); 185 } 186 187 if (is_feat_fgt_supported()) { 188 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 189 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 190 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 191 } 192 #endif 193 } 194 195 /****************************************************************************** 196 * This function performs initializations that are specific to SECURE state 197 * and updates the cpu context specified by 'ctx'. 198 *****************************************************************************/ 199 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 200 { 201 u_register_t scr_el3; 202 el3_state_t *state; 203 204 state = get_el3state_ctx(ctx); 205 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 206 207 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 208 /* 209 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 210 * indicated by the interrupt routing model for BL31. 211 */ 212 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 213 #endif 214 215 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 216 if (is_feat_mte2_supported()) { 217 scr_el3 |= SCR_ATA_BIT; 218 } 219 220 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 221 222 manage_extensions_secure(ctx); 223 } 224 225 #if ENABLE_RME && IMAGE_BL31 226 /****************************************************************************** 227 * This function performs initializations that are specific to REALM state 228 * and updates the cpu context specified by 'ctx'. 229 * 230 * NOTE: any changes to this function must be verified by an RMMD maintainer. 231 *****************************************************************************/ 232 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 233 { 234 u_register_t scr_el3; 235 el3_state_t *state; 236 el2_sysregs_t *el2_ctx; 237 238 state = get_el3state_ctx(ctx); 239 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 240 el2_ctx = get_el2_sysregs_ctx(ctx); 241 242 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 243 244 write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM); 245 246 /* CSV2 version 2 and above */ 247 if (is_feat_csv2_2_supported()) { 248 /* Enable access to the SCXTNUM_ELx registers. */ 249 scr_el3 |= SCR_EnSCXT_BIT; 250 } 251 252 if (is_feat_sctlr2_supported()) { 253 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 254 * SCTLR2_ELx registers. 255 */ 256 scr_el3 |= SCR_SCTLR2En_BIT; 257 } 258 259 if (is_feat_d128_supported()) { 260 /* 261 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 262 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 263 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 264 */ 265 scr_el3 |= SCR_D128En_BIT; 266 } 267 268 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 269 270 if (is_feat_fgt2_supported()) { 271 fgt2_enable(ctx); 272 } 273 274 if (is_feat_debugv8p9_supported()) { 275 debugv8p9_extended_bp_wp_enable(ctx); 276 } 277 278 if (is_feat_brbe_supported()) { 279 brbe_enable(ctx); 280 } 281 282 /* 283 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world. 284 */ 285 if (is_feat_sme_supported()) { 286 sme_enable(ctx); 287 } 288 289 if (is_feat_spe_supported()) { 290 spe_disable_realm(ctx); 291 } 292 293 if (is_feat_trbe_supported()) { 294 trbe_disable_realm(ctx); 295 } 296 } 297 #endif /* ENABLE_RME && IMAGE_BL31 */ 298 299 /****************************************************************************** 300 * This function performs initializations that are specific to NON-SECURE state 301 * and updates the cpu context specified by 'ctx'. 302 *****************************************************************************/ 303 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 304 { 305 u_register_t scr_el3; 306 el3_state_t *state; 307 308 state = get_el3state_ctx(ctx); 309 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 310 311 /* SCR_NS: Set the NS bit */ 312 scr_el3 |= SCR_NS_BIT; 313 314 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 315 if (is_feat_mte2_supported()) { 316 scr_el3 |= SCR_ATA_BIT; 317 } 318 319 /* 320 * Pointer Authentication feature, if present, is always enabled by 321 * default for Non secure lower exception levels. We do not have an 322 * explicit flag to set it. To prevent the leakage between the worlds 323 * during world switch, we enable it only for the non-secure world. 324 * 325 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 326 * exception levels of secure and realm worlds. 327 * 328 * If the Secure/realm world wants to use pointer authentication, 329 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 330 * it will be enabled globally for all the contexts. 331 * 332 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 333 * other than EL3 334 * 335 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 336 * than EL3 337 */ 338 if (!is_ctx_pauth_supported()) { 339 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 340 } 341 342 #if HANDLE_EA_EL3_FIRST_NS 343 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 344 scr_el3 |= SCR_EA_BIT; 345 #endif 346 347 #if RAS_TRAP_NS_ERR_REC_ACCESS 348 /* 349 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 350 * and RAS ERX registers from EL1 and EL2(from any security state) 351 * are trapped to EL3. 352 * Set here to trap only for NS EL1/EL2 353 */ 354 scr_el3 |= SCR_TERR_BIT; 355 #endif 356 357 /* CSV2 version 2 and above */ 358 if (is_feat_csv2_2_supported()) { 359 /* Enable access to the SCXTNUM_ELx registers. */ 360 scr_el3 |= SCR_EnSCXT_BIT; 361 } 362 363 #ifdef IMAGE_BL31 364 /* 365 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 366 * indicated by the interrupt routing model for BL31. 367 */ 368 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 369 #endif 370 371 if (is_feat_the_supported()) { 372 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 373 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 374 */ 375 scr_el3 |= SCR_RCWMASKEn_BIT; 376 } 377 378 if (is_feat_sctlr2_supported()) { 379 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 380 * SCTLR2_ELx registers. 381 */ 382 scr_el3 |= SCR_SCTLR2En_BIT; 383 } 384 385 if (is_feat_d128_supported()) { 386 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 387 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 388 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 389 */ 390 scr_el3 |= SCR_D128En_BIT; 391 } 392 393 if (is_feat_fpmr_supported()) { 394 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 395 * register. 396 */ 397 scr_el3 |= SCR_EnFPM_BIT; 398 } 399 400 if (is_feat_aie_supported()) { 401 /* Set the AIEn bit in SCR_EL3 to enable access to (A)MAIR2 402 * system registers from NS world. 403 */ 404 scr_el3 |= SCR_AIEn_BIT; 405 } 406 407 if (is_feat_pfar_supported()) { 408 /* Set the PFAREn bit in SCR_EL3 to enable access to the PFAR 409 * system registers from NS world. 410 */ 411 scr_el3 |= SCR_PFAREn_BIT; 412 } 413 414 if (is_feat_hdbss_supported()) { 415 /* Set the HDBSSEn bit to enable access to hdbssbr_el2 and 416 * hdbssprod_el2 417 */ 418 scr_el3 |= SCR_HDBSSEn_BIT; 419 } 420 421 if (is_feat_hacdbs_supported()) { 422 /* Set the HACDBSEn bit to enable access to hacdbsbr_el2 and 423 * hacdbscons_el2 424 */ 425 scr_el3 |= SCR_HACDBSEn_BIT; 426 } 427 428 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 429 430 manage_extensions_nonsecure(ctx); 431 } 432 433 static inline ddc_cap_t read_ddc_el0 (void) 434 { 435 ddc_cap_t val = NULL; 436 #if ENABLE_FEAT_MORELLO 437 __asm__ volatile ("msr spsel, #1 \n" 438 "mrs %0, ddc \n" 439 "msr spsel, #0 \n" 440 : "=C"(val) 441 : 442 : "memory" 443 ); 444 #endif 445 return val; 446 } 447 448 /******************************************************************************* 449 * The following function performs initialization of the cpu_context 'ctx' 450 * for first use that is common to all security states, and sets the 451 * initial entrypoint state as specified by the entry_point_info structure. 452 * 453 * The EE and ST attributes are used to configure the endianness and secure 454 * timer availability for the new execution context. 455 ******************************************************************************/ 456 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 457 { 458 u_register_t scr_el3; 459 u_register_t mdcr_el3; 460 el3_state_t *state; 461 gp_regs_t *gp_regs; 462 463 state = get_el3state_ctx(ctx); 464 465 /* Clear any residual register values from the context */ 466 zeromem(ctx, sizeof(*ctx)); 467 468 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 469 scr_el3 = SCR_RESET_VAL; 470 471 /* 472 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 473 * EL2, EL1 and EL0 are not trapped to EL3. 474 * 475 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 476 * EL2, EL1 and EL0 are not trapped to EL3. 477 * 478 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 479 * both Security states and both Execution states. 480 * 481 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 482 * Non-secure memory. 483 */ 484 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 485 486 scr_el3 |= SCR_SIF_BIT; 487 488 /* 489 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 490 * Exception level as specified by SPSR. 491 */ 492 if (GET_RW(ep->spsr) == MODE_RW_64) { 493 scr_el3 |= SCR_RW_BIT; 494 } 495 496 /* 497 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 498 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 499 * next mode is Hyp. 500 */ 501 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 502 || ((GET_RW(ep->spsr) != MODE_RW_64) 503 && (GET_M32(ep->spsr) == MODE32_hyp))) { 504 scr_el3 |= SCR_HCE_BIT; 505 } 506 507 /* 508 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 509 * Secure timer registers to EL3, from AArch64 state only, if specified 510 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 511 * bit always behaves as 1 (i.e. secure physical timer register access 512 * is not trapped) 513 */ 514 if (EP_GET_ST(ep->h.attr) != 0U) { 515 scr_el3 |= SCR_ST_BIT; 516 } 517 518 /* 519 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 520 * SCR_EL3.HXEn. 521 */ 522 if (is_feat_hcx_supported()) { 523 scr_el3 |= SCR_HXEn_BIT; 524 } 525 526 /* 527 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 528 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 529 * SCR_EL3.EnAS0. 530 */ 531 if (is_feat_ls64_accdata_supported()) { 532 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 533 } 534 535 /* 536 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 537 * registers are trapped to EL3. 538 */ 539 if (is_feat_rng_trap_supported()) { 540 scr_el3 |= SCR_TRNDR_BIT; 541 } 542 543 #if FAULT_INJECTION_SUPPORT 544 /* Enable fault injection from lower ELs */ 545 scr_el3 |= SCR_FIEN_BIT; 546 #endif 547 548 /* 549 * Enable Pointer Authentication globally for all the worlds. 550 * 551 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 552 * other than EL3 553 * 554 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 555 * than EL3 556 */ 557 if (is_ctx_pauth_supported()) { 558 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 559 } 560 561 /* 562 * SCR_EL3.PIEN: Enable permission indirection and overlay 563 * registers for AArch64 if present. 564 */ 565 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 566 scr_el3 |= SCR_PIEN_BIT; 567 } 568 569 /* SCR_EL3.GCSEn: Enable GCS registers. */ 570 if (is_feat_gcs_supported()) { 571 scr_el3 |= SCR_GCSEn_BIT; 572 } 573 574 /* SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps */ 575 if (is_feat_fgt_supported()) { 576 scr_el3 |= SCR_FGTEN_BIT; 577 } 578 579 /* SCR_EL3.ECVEn: Do not trap the CNTPOFF_EL2 register */ 580 if (is_feat_ecv_supported()) { 581 scr_el3 |= SCR_ECVEN_BIT; 582 } 583 584 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 585 if (is_feat_twed_supported()) { 586 /* Set delay in SCR_EL3 */ 587 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 588 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 589 << SCR_TWEDEL_SHIFT); 590 591 /* Enable WFE delay */ 592 scr_el3 |= SCR_TWEDEn_BIT; 593 } 594 595 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 596 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 597 if (is_feat_sel2_supported()) { 598 scr_el3 |= SCR_EEL2_BIT; 599 } 600 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 601 602 if (is_feat_mec_supported()) { 603 scr_el3 |= SCR_MECEn_BIT; 604 } 605 606 /* 607 * Populate EL3 state so that we've the right context 608 * before doing ERET 609 */ 610 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 611 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 612 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 613 614 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 615 mdcr_el3 = MDCR_EL3_RESET_VAL; 616 617 /* --------------------------------------------------------------------- 618 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 619 * Some fields are architecturally UNKNOWN on reset. 620 * 621 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 622 * Debug exceptions, other than Breakpoint Instruction exceptions, are 623 * disabled from all ELs in Secure state. 624 * 625 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 626 * privileged debug from S-EL1. 627 * 628 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 629 * access to the powerdown debug registers do not trap to EL3. 630 * 631 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 632 * debug registers, other than those registers that are controlled by 633 * MDCR_EL3.TDOSA. 634 */ 635 mdcr_el3 |= MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE); 636 mdcr_el3 &= ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT); 637 638 /* MDCR_EL3.EnSTEPOP: allow access to MDSTEPOP_EL1 */ 639 if (is_feat_step2_supported()) { 640 mdcr_el3 |= MDCR_EnSTEPOP_BIT; 641 } 642 643 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 644 645 #if IMAGE_BL31 646 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 647 if (is_feat_trf_supported()) { 648 trf_enable(ctx); 649 } 650 651 if (is_feat_tcr2_supported()) { 652 tcr2_enable(ctx); 653 } 654 655 pmuv3_enable(ctx); 656 657 if (is_feat_idte3_supported()) { 658 idte3_enable(ctx); 659 } 660 #endif /* IMAGE_BL31 */ 661 662 setup_el2_context(ctx); 663 664 setup_el1_context(ctx, ep); 665 666 if (is_feat_morello_supported()) { 667 ctx->ddc_el0 = read_ddc_el0(); 668 } 669 670 /* 671 * Store the X0-X7 value from the entrypoint into the context 672 * Use memcpy as we are in control of the layout of the structures 673 */ 674 gp_regs = get_gpregs_ctx(ctx); 675 memcpy((void *)gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 676 } 677 678 /******************************************************************************* 679 * Context management library initialization routine. This library is used by 680 * runtime services to share pointers to 'cpu_context' structures for secure 681 * non-secure and realm states. Management of the structures and their associated 682 * memory is not done by the context management library e.g. the PSCI service 683 * manages the cpu context used for entry from and exit to the non-secure state. 684 * The Secure payload dispatcher service manages the context(s) corresponding to 685 * the secure state. It also uses this library to get access to the non-secure 686 * state cpu context pointers. 687 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 688 * which will be used for programming an entry into a lower EL. The same context 689 * will be used to save state upon exception entry from that EL. 690 ******************************************************************************/ 691 void __init cm_init(void) 692 { 693 /* 694 * The context management library has only global data to initialize, but 695 * that will be done when the BSS is zeroed out. 696 */ 697 } 698 699 /******************************************************************************* 700 * This is the high-level function used to initialize the cpu_context 'ctx' for 701 * first use. It performs initializations that are common to all security states 702 * and initializations specific to the security state specified in 'ep' 703 ******************************************************************************/ 704 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 705 { 706 size_t security_state; 707 708 assert(ctx != NULL); 709 710 /* 711 * Perform initializations that are common 712 * to all security states 713 */ 714 setup_context_common(ctx, ep); 715 716 security_state = GET_SECURITY_STATE(ep->h.attr); 717 718 /* Perform security state specific initializations */ 719 switch (security_state) { 720 case SECURE: 721 setup_secure_context(ctx, ep); 722 break; 723 #if ENABLE_RME && IMAGE_BL31 724 case REALM: 725 setup_realm_context(ctx, ep); 726 break; 727 #endif 728 case NON_SECURE: 729 setup_ns_context(ctx, ep); 730 break; 731 default: 732 ERROR("Invalid security state\n"); 733 panic(); 734 break; 735 } 736 } 737 738 /******************************************************************************* 739 * Enable architecture extensions for EL3 execution. This function only updates 740 * registers in-place which are expected to either never change or be 741 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 742 ******************************************************************************/ 743 void __no_pauth cm_manage_extensions_el3(unsigned int my_idx) 744 { 745 if (is_feat_pauth_supported()) { 746 pauth_init_enable_el3(); 747 } 748 749 #if IMAGE_BL31 750 if (is_feat_sve_supported()) { 751 sve_init_el3(); 752 } 753 754 if (is_feat_amu_supported()) { 755 amu_init_el3(my_idx); 756 } 757 758 if (is_feat_sme_supported()) { 759 sme_init_el3(); 760 } 761 762 if (is_feat_mpam_supported()) { 763 mpam_init_el3(); 764 } 765 766 if (is_feat_cpa2_supported()) { 767 cpa2_enable_el3(); 768 } 769 770 pmuv3_init_el3(); 771 772 /* NOTE: must be done last, makes the configuration immutable */ 773 if (is_feat_fgwte3_supported()) { 774 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL); 775 } 776 #endif /* IMAGE_BL31 */ 777 } 778 779 /****************************************************************************** 780 * Function to initialise the registers with the RESET values in the context 781 * memory, which are maintained per world. 782 ******************************************************************************/ 783 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 784 { 785 per_world_ctx->ctx_cptr_el3 = CPTR_EL3_RESET_VAL; 786 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 787 } 788 789 /******************************************************************************* 790 * Initialise per_world_context for Non-Secure world. 791 * This function enables the architecture extensions, which have same value 792 * across the cores for the non-secure world. 793 ******************************************************************************/ 794 static void manage_extensions_nonsecure_per_world(void) 795 { 796 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 797 798 #if IMAGE_BL31 799 if (is_feat_sme_supported()) { 800 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 801 } 802 803 if (is_feat_sve_supported()) { 804 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 805 } 806 807 if (is_feat_amu_supported()) { 808 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 809 } 810 811 if (is_feat_sys_reg_trace_supported()) { 812 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 813 } 814 815 if (is_feat_mpam_supported()) { 816 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 817 } 818 819 if (is_feat_idte3_supported()) { 820 idte3_init_cached_idregs_per_world(CPU_CONTEXT_NS); 821 } 822 #endif /* IMAGE_BL31 */ 823 } 824 825 /******************************************************************************* 826 * Initialise per_world_context for Secure world. 827 * This function enables the architecture extensions, which have same value 828 * across the cores for the secure world. 829 ******************************************************************************/ 830 static void manage_extensions_secure_per_world(void) 831 { 832 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 833 834 #if IMAGE_BL31 835 if (is_feat_sme_supported()) { 836 837 if (ENABLE_SME_FOR_SWD) { 838 /* 839 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 840 * SME, SVE, and FPU/SIMD context properly managed. 841 */ 842 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 843 } else { 844 /* 845 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 846 * world can safely use the associated registers. 847 */ 848 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 849 } 850 } 851 if (is_feat_sve_supported()) { 852 if (ENABLE_SVE_FOR_SWD) { 853 /* 854 * Enable SVE and FPU in secure context, SPM must ensure 855 * that the SVE and FPU register contexts are properly managed. 856 */ 857 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 858 } else { 859 /* 860 * Disable SVE and FPU in secure context so non-secure world 861 * can safely use them. 862 */ 863 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 864 } 865 } 866 867 /* NS can access this but Secure shouldn't */ 868 if (is_feat_sys_reg_trace_supported()) { 869 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 870 } 871 872 if (is_feat_idte3_supported()) { 873 idte3_init_cached_idregs_per_world(CPU_CONTEXT_SECURE); 874 } 875 #endif /* IMAGE_BL31 */ 876 } 877 878 static void manage_extensions_realm_per_world(void) 879 { 880 #if ENABLE_RME && IMAGE_BL31 881 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 882 883 if (is_feat_sve_supported()) { 884 /* 885 * Enable SVE and FPU in realm context when it is enabled for NS. 886 * Realm manager must ensure that the SVE and FPU register 887 * contexts are properly managed. 888 */ 889 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 890 } 891 892 /* NS can access this but Realm shouldn't */ 893 if (is_feat_sys_reg_trace_supported()) { 894 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 895 } 896 897 /* 898 * If SME/SME2 is supported and enabled for NS world, then disable trapping 899 * of SME instructions for Realm world. RMM will save/restore required 900 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 901 */ 902 if (is_feat_sme_supported()) { 903 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 904 } 905 906 /* 907 * If FEAT_MPAM is supported and enabled, then disable trapping access 908 * to the MPAM registers for Realm world. Instead, RMM will configure 909 * the access to be trapped by itself so it can inject undefined aborts 910 * back to the Realm. 911 */ 912 if (is_feat_mpam_supported()) { 913 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 914 } 915 916 if (is_feat_idte3_supported()) { 917 idte3_init_cached_idregs_per_world(CPU_CONTEXT_REALM); 918 } 919 #endif /* ENABLE_RME && IMAGE_BL31 */ 920 } 921 922 void cm_manage_extensions_per_world(void) 923 { 924 manage_extensions_nonsecure_per_world(); 925 manage_extensions_secure_per_world(); 926 manage_extensions_realm_per_world(); 927 } 928 929 void cm_init_percpu_once_regs(void) 930 { 931 #if IMAGE_BL31 932 if (is_feat_idte3_supported()) { 933 idte3_init_percpu_once_regs(CPU_CONTEXT_NS); 934 idte3_init_percpu_once_regs(CPU_CONTEXT_SECURE); 935 #if ENABLE_RME 936 idte3_init_percpu_once_regs(CPU_CONTEXT_REALM); 937 #endif /* ENABLE_RME */ 938 } 939 #endif /* IMAGE_BL31 */ 940 } 941 942 /******************************************************************************* 943 * Enable architecture extensions on first entry to Non-secure world. 944 ******************************************************************************/ 945 static void manage_extensions_nonsecure(cpu_context_t *ctx) 946 { 947 #if IMAGE_BL31 948 /* NOTE: registers are not context switched */ 949 if (is_feat_amu_supported()) { 950 amu_enable(ctx); 951 } 952 953 if (is_feat_sme_supported()) { 954 sme_enable(ctx); 955 } 956 957 if (is_feat_fgt2_supported()) { 958 fgt2_enable(ctx); 959 } 960 961 if (is_feat_debugv8p9_supported()) { 962 debugv8p9_extended_bp_wp_enable(ctx); 963 } 964 965 if (is_feat_spe_supported()) { 966 spe_enable_ns(ctx); 967 } 968 969 if (is_feat_trbe_supported()) { 970 if (check_if_trbe_disable_affected_core()) { 971 trbe_disable_ns(ctx); 972 } else { 973 trbe_enable_ns(ctx); 974 } 975 } 976 977 if (is_feat_brbe_supported()) { 978 brbe_enable(ctx); 979 } 980 #endif /* IMAGE_BL31 */ 981 } 982 983 #if INIT_UNUSED_NS_EL2 984 /******************************************************************************* 985 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 986 * world when EL2 is empty and unused. 987 ******************************************************************************/ 988 static void manage_extensions_nonsecure_el2_unused(void) 989 { 990 #if IMAGE_BL31 991 if (is_feat_spe_supported()) { 992 spe_init_el2_unused(); 993 } 994 995 if (is_feat_amu_supported()) { 996 amu_init_el2_unused(); 997 } 998 999 if (is_feat_mpam_supported()) { 1000 mpam_init_el2_unused(); 1001 } 1002 1003 if (is_feat_trbe_supported()) { 1004 trbe_init_el2_unused(); 1005 } 1006 1007 if (is_feat_sys_reg_trace_supported()) { 1008 sys_reg_trace_init_el2_unused(); 1009 } 1010 1011 if (is_feat_trf_supported()) { 1012 trf_init_el2_unused(); 1013 } 1014 1015 pmuv3_init_el2_unused(); 1016 1017 if (is_feat_sve_supported()) { 1018 sve_init_el2_unused(); 1019 } 1020 1021 if (is_feat_sme_supported()) { 1022 sme_init_el2_unused(); 1023 } 1024 1025 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 1026 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 1027 } 1028 1029 if (is_feat_pauth_supported()) { 1030 pauth_enable_el2(); 1031 } 1032 #endif /* IMAGE_BL31 */ 1033 } 1034 #endif /* INIT_UNUSED_NS_EL2 */ 1035 1036 /******************************************************************************* 1037 * Enable architecture extensions on first entry to Secure world. 1038 ******************************************************************************/ 1039 static void manage_extensions_secure(cpu_context_t *ctx) 1040 { 1041 #if IMAGE_BL31 1042 if (is_feat_sme_supported()) { 1043 if (ENABLE_SME_FOR_SWD) { 1044 /* 1045 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 1046 * must ensure SME, SVE, and FPU/SIMD context properly managed. 1047 */ 1048 sme_init_el3(); 1049 sme_enable(ctx); 1050 } else { 1051 /* 1052 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 1053 * world can safely use the associated registers. 1054 */ 1055 sme_disable(ctx); 1056 } 1057 } 1058 1059 if (is_feat_spe_supported()) { 1060 spe_disable_secure(ctx); 1061 } 1062 1063 if (is_feat_trbe_supported()) { 1064 trbe_disable_secure(ctx); 1065 } 1066 #endif /* IMAGE_BL31 */ 1067 } 1068 1069 /******************************************************************************* 1070 * The following function initializes the cpu_context for the current CPU 1071 * for first use, and sets the initial entrypoint state as specified by the 1072 * entry_point_info structure. 1073 ******************************************************************************/ 1074 void cm_init_my_context(const entry_point_info_t *ep) 1075 { 1076 cpu_context_t *ctx; 1077 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 1078 cm_setup_context(ctx, ep); 1079 } 1080 1081 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 1082 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 1083 { 1084 #if INIT_UNUSED_NS_EL2 1085 u_register_t hcr_el2 = HCR_RESET_VAL; 1086 u_register_t mdcr_el2; 1087 u_register_t scr_el3; 1088 1089 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1090 1091 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 1092 if ((scr_el3 & SCR_RW_BIT) != 0U) { 1093 hcr_el2 |= HCR_RW_BIT; 1094 } 1095 1096 write_hcr_el2(hcr_el2); 1097 1098 /* 1099 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1100 * All fields have architecturally UNKNOWN reset values. 1101 */ 1102 write_cptr_el2(CPTR_EL2_RESET_VAL); 1103 1104 /* 1105 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1106 * reset and are set to zero except for field(s) listed below. 1107 * 1108 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1109 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1110 * 1111 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1112 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1113 */ 1114 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1115 1116 /* 1117 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1118 * UNKNOWN value. 1119 */ 1120 write_cntvoff_el2(0); 1121 1122 /* 1123 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1124 * respectively. 1125 */ 1126 write_vpidr_el2(read_midr_el1()); 1127 write_vmpidr_el2(read_mpidr_el1()); 1128 1129 /* 1130 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1131 * 1132 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1133 * translation is disabled, cache maintenance operations depend on the 1134 * VMID. 1135 * 1136 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1137 * disabled. 1138 */ 1139 write_vttbr_el2(VTTBR_RESET_VAL & 1140 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1141 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1142 1143 /* 1144 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1145 * Some fields are architecturally UNKNOWN on reset. 1146 * 1147 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1148 * register accesses to the Debug ROM registers are not trapped to EL2. 1149 * 1150 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1151 * accesses to the powerdown debug registers are not trapped to EL2. 1152 * 1153 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1154 * debug registers do not trap to EL2. 1155 * 1156 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1157 * EL2. 1158 */ 1159 mdcr_el2 = MDCR_EL2_RESET_VAL & 1160 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1161 MDCR_EL2_TDE_BIT); 1162 1163 write_mdcr_el2(mdcr_el2); 1164 1165 /* 1166 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1167 * 1168 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1169 * EL1 accesses to System registers do not trap to EL2. 1170 */ 1171 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1172 1173 /* 1174 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1175 * reset. 1176 * 1177 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1178 * and prevent timer interrupts. 1179 */ 1180 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1181 1182 manage_extensions_nonsecure_el2_unused(); 1183 #endif /* INIT_UNUSED_NS_EL2 */ 1184 } 1185 1186 /******************************************************************************* 1187 * Prepare the CPU system registers for first entry into realm, secure, or 1188 * normal world. 1189 * 1190 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1191 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1192 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1193 * For all entries, the EL1 registers are initialized from the cpu_context 1194 ******************************************************************************/ 1195 void cm_prepare_el3_exit(size_t security_state) 1196 { 1197 u_register_t sctlr_el2, scr_el3; 1198 cpu_context_t *ctx = cm_get_context(security_state); 1199 1200 assert(ctx != NULL); 1201 1202 if (security_state == NON_SECURE) { 1203 uint64_t el2_implemented = el_implemented(2); 1204 1205 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1206 CTX_SCR_EL3); 1207 1208 if (el2_implemented != EL_IMPL_NONE) { 1209 setup_el2_regs(); 1210 1211 /* Condition to ensure EL2 is being used. */ 1212 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1213 /* Initialize SCTLR_EL2 register with reset value. */ 1214 sctlr_el2 = SCTLR_EL2_RES1; 1215 1216 /* 1217 * If workaround of errata 764081 for Cortex-A75 1218 * is used then set SCTLR_EL2.IESB to enable 1219 * Implicit Error Synchronization Barrier. 1220 */ 1221 if (errata_a75_764081_applies()) { 1222 sctlr_el2 |= SCTLR_IESB_BIT; 1223 } 1224 1225 write_sctlr_el2(sctlr_el2); 1226 } else { 1227 /* 1228 * (scr_el3 & SCR_HCE_BIT==0) 1229 * EL2 implemented but unused. 1230 */ 1231 init_nonsecure_el2_unused(ctx); 1232 } 1233 } 1234 1235 if (is_feat_fgwte3_supported()) { 1236 /* 1237 * TCR_EL3 and ACTLR_EL3 could be overwritten 1238 * by platforms and hence is locked a bit late. 1239 */ 1240 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL); 1241 } 1242 } 1243 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1 1244 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1245 cm_el1_sysregs_context_restore(security_state); 1246 #endif 1247 cm_set_next_eret_context(security_state); 1248 } 1249 1250 /* Assumes prepare_el3_entry() has disabled counters 2 and 3 */ 1251 void cm_sysregs_context_save_amu(unsigned int security_state) 1252 { 1253 world_amu_regs_t *ctx = PER_CPU_CUR(world_amu_ctx[get_cpu_context_index(security_state)]); 1254 1255 ctx->amevcntr02_el0 = read_amevcntr02_el0(); 1256 ctx->amevcntr03_el0 = read_amevcntr03_el0(); 1257 } 1258 1259 void cm_sysregs_context_restore_amu(unsigned int security_state) 1260 { 1261 world_amu_regs_t *ctx = PER_CPU_CUR(world_amu_ctx[get_cpu_context_index(security_state)]); 1262 1263 write_amevcntr02_el0(ctx->amevcntr02_el0); 1264 write_amevcntr03_el0(ctx->amevcntr03_el0); 1265 } 1266 1267 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1268 1269 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1270 { 1271 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1272 if (is_feat_amu_supported()) { 1273 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1274 } 1275 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1276 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1277 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1278 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1279 } 1280 1281 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1282 { 1283 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1284 if (is_feat_amu_supported()) { 1285 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1286 } 1287 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1288 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1289 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1290 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1291 } 1292 1293 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1294 { 1295 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1296 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1297 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1298 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1299 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1300 } 1301 1302 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1303 { 1304 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1305 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1306 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1307 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1308 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1309 } 1310 1311 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1312 { 1313 u_register_t mpam_idr = read_mpamidr_el1(); 1314 1315 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1316 1317 /* 1318 * The context registers that we intend to save would be part of the 1319 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1320 */ 1321 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1322 return; 1323 } 1324 1325 /* 1326 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1327 * MPAMIDR_HAS_HCR_BIT == 1. 1328 */ 1329 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1330 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1331 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1332 1333 /* 1334 * The number of MPAMVPM registers is implementation defined, their 1335 * number is stored in the MPAMIDR_EL1 register. 1336 */ 1337 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1338 case 7: 1339 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1340 __fallthrough; 1341 case 6: 1342 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1343 __fallthrough; 1344 case 5: 1345 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1346 __fallthrough; 1347 case 4: 1348 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1349 __fallthrough; 1350 case 3: 1351 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1352 __fallthrough; 1353 case 2: 1354 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1355 __fallthrough; 1356 case 1: 1357 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1358 break; 1359 } 1360 } 1361 1362 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1363 { 1364 u_register_t mpam_idr = read_mpamidr_el1(); 1365 1366 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1367 1368 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1369 return; 1370 } 1371 1372 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1373 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1374 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1375 1376 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1377 case 7: 1378 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1379 __fallthrough; 1380 case 6: 1381 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1382 __fallthrough; 1383 case 5: 1384 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1385 __fallthrough; 1386 case 4: 1387 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1388 __fallthrough; 1389 case 3: 1390 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1391 __fallthrough; 1392 case 2: 1393 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1394 __fallthrough; 1395 case 1: 1396 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1397 break; 1398 } 1399 } 1400 1401 /* --------------------------------------------------------------------------- 1402 * The following registers are not added: 1403 * ICH_AP0R<n>_EL2 1404 * ICH_AP1R<n>_EL2 1405 * ICH_LR<n>_EL2 1406 * 1407 * NOTE: For a system with S-EL2 present but not enabled, accessing 1408 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1409 * SCR_EL3.NS = 1 before accessing this register. 1410 * --------------------------------------------------------------------------- 1411 */ 1412 void cm_el2_sysregs_context_save_gic(uint32_t security_state) 1413 { 1414 el2_sysregs_t *ctx = get_el2_sysregs_ctx(cm_get_context(security_state)); 1415 1416 u_register_t scr_el3 = read_scr_el3(); 1417 1418 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1419 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1420 #else 1421 write_scr_el3(scr_el3 | SCR_NS_BIT); 1422 isb(); 1423 1424 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1425 1426 write_scr_el3(scr_el3); 1427 isb(); 1428 #endif 1429 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1430 1431 if (errata_ich_vmcr_el2_applies()) { 1432 if (security_state == SECURE) { 1433 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1434 } else { 1435 write_scr_el3(scr_el3 | SCR_NS_BIT); 1436 } 1437 isb(); 1438 } 1439 1440 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1441 1442 if (errata_ich_vmcr_el2_applies()) { 1443 write_scr_el3(scr_el3); 1444 isb(); 1445 } 1446 } 1447 1448 void cm_el2_sysregs_context_restore_gic(uint32_t security_state) 1449 { 1450 el2_sysregs_t *ctx = get_el2_sysregs_ctx(cm_get_context(security_state)); 1451 1452 u_register_t scr_el3 = read_scr_el3(); 1453 1454 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1455 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1456 #else 1457 write_scr_el3(scr_el3 | SCR_NS_BIT); 1458 isb(); 1459 1460 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1461 1462 write_scr_el3(scr_el3); 1463 isb(); 1464 #endif 1465 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1466 1467 if (errata_ich_vmcr_el2_applies()) { 1468 if (security_state == SECURE) { 1469 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1470 } else { 1471 write_scr_el3(scr_el3 | SCR_NS_BIT); 1472 } 1473 isb(); 1474 } 1475 1476 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1477 1478 if (errata_ich_vmcr_el2_applies()) { 1479 write_scr_el3(scr_el3); 1480 isb(); 1481 } 1482 } 1483 1484 /* ----------------------------------------------------- 1485 * The following registers are not added: 1486 * AMEVCNTVOFF0<n>_EL2 1487 * AMEVCNTVOFF1<n>_EL2 1488 * ----------------------------------------------------- 1489 */ 1490 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1491 { 1492 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1493 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1494 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1495 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1496 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1497 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1498 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1499 if (CTX_INCLUDE_AARCH32_REGS) { 1500 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1501 } 1502 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1503 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1504 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1505 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1506 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1507 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1508 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1509 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1510 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1511 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1512 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1513 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1514 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1515 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1516 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1517 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1518 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1519 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1520 1521 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1522 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1523 } 1524 1525 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1526 { 1527 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1528 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1529 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1530 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1531 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1532 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1533 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1534 if (CTX_INCLUDE_AARCH32_REGS) { 1535 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1536 } 1537 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1538 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1539 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1540 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1541 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1542 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1543 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1544 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1545 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1546 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1547 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1548 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1549 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1550 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1551 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1552 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1553 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1554 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1555 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1556 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1557 } 1558 1559 /******************************************************************************* 1560 * Save EL2 sysreg context 1561 ******************************************************************************/ 1562 void cm_el2_sysregs_context_save(uint32_t security_state) 1563 { 1564 cpu_context_t *ctx; 1565 el2_sysregs_t *el2_sysregs_ctx; 1566 1567 ctx = cm_get_context(security_state); 1568 assert(ctx != NULL); 1569 1570 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1571 1572 el2_sysregs_context_save_common(el2_sysregs_ctx); 1573 1574 if (is_feat_mte2_supported()) { 1575 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1576 } 1577 1578 if (is_feat_mpam_supported()) { 1579 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1580 } 1581 1582 if (is_feat_fgt_supported()) { 1583 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1584 } 1585 1586 if (is_feat_fgt2_supported()) { 1587 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1588 } 1589 1590 if (is_feat_ecv_v2_supported()) { 1591 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1592 } 1593 1594 if (is_feat_vhe_supported()) { 1595 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1596 read_contextidr_el2()); 1597 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1598 } 1599 1600 if (is_feat_ras_supported()) { 1601 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1602 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1603 } 1604 1605 if (is_feat_nv2_supported()) { 1606 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1607 } 1608 1609 if (is_feat_trf_supported()) { 1610 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1611 } 1612 1613 if (is_feat_csv2_2_supported()) { 1614 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1615 read_scxtnum_el2()); 1616 } 1617 1618 if (is_feat_hcx_supported()) { 1619 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1620 } 1621 1622 if (is_feat_tcr2_supported()) { 1623 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1624 } 1625 1626 if (is_feat_s1pie_supported()) { 1627 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1628 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1629 } 1630 1631 if (is_feat_s1poe_supported()) { 1632 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1633 } 1634 1635 if (is_feat_brbe_supported()) { 1636 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1637 } 1638 1639 if (is_feat_s2pie_supported()) { 1640 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1641 } 1642 1643 if (is_feat_gcs_supported()) { 1644 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1645 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1646 } 1647 1648 if (is_feat_sctlr2_supported()) { 1649 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1650 } 1651 1652 if (is_feat_amu_supported()) { 1653 cm_sysregs_context_save_amu(security_state); 1654 } 1655 } 1656 1657 /******************************************************************************* 1658 * Restore EL2 sysreg context 1659 ******************************************************************************/ 1660 void cm_el2_sysregs_context_restore(uint32_t security_state) 1661 { 1662 cpu_context_t *ctx; 1663 el2_sysregs_t *el2_sysregs_ctx; 1664 1665 ctx = cm_get_context(security_state); 1666 assert(ctx != NULL); 1667 1668 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1669 1670 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1671 1672 if (is_feat_mte2_supported()) { 1673 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1674 } 1675 1676 if (is_feat_mpam_supported()) { 1677 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1678 } 1679 1680 if (is_feat_fgt_supported()) { 1681 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1682 } 1683 1684 if (is_feat_fgt2_supported()) { 1685 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1686 } 1687 1688 if (is_feat_ecv_v2_supported()) { 1689 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1690 } 1691 1692 if (is_feat_vhe_supported()) { 1693 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1694 contextidr_el2)); 1695 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1696 } 1697 1698 if (is_feat_ras_supported()) { 1699 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1700 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1701 } 1702 1703 if (is_feat_nv2_supported()) { 1704 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1705 } 1706 1707 if (is_feat_trf_supported()) { 1708 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1709 } 1710 1711 if (is_feat_csv2_2_supported()) { 1712 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1713 scxtnum_el2)); 1714 } 1715 1716 if (is_feat_hcx_supported()) { 1717 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1718 } 1719 1720 if (is_feat_tcr2_supported()) { 1721 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1722 } 1723 1724 if (is_feat_s1pie_supported()) { 1725 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1726 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1727 } 1728 1729 if (is_feat_s1poe_supported()) { 1730 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1731 } 1732 1733 if (is_feat_s2pie_supported()) { 1734 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1735 } 1736 1737 if (is_feat_gcs_supported()) { 1738 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1739 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1740 } 1741 1742 if (is_feat_sctlr2_supported()) { 1743 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1744 } 1745 1746 if (is_feat_brbe_supported()) { 1747 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1748 } 1749 1750 if (is_feat_amu_supported()) { 1751 cm_sysregs_context_restore_amu(security_state); 1752 } 1753 } 1754 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1755 1756 /******************************************************************************* 1757 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1758 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1759 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1760 * cm_prepare_el3_exit function. 1761 ******************************************************************************/ 1762 void cm_prepare_el3_exit_ns(void) 1763 { 1764 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1765 #if ENABLE_ASSERTIONS 1766 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1767 assert(ctx != NULL); 1768 1769 /* Assert that EL2 is used. */ 1770 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1771 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1772 (el_implemented(2U) != EL_IMPL_NONE)); 1773 #endif /* ENABLE_ASSERTIONS */ 1774 1775 /* Restore EL2 sysreg contexts */ 1776 cm_el2_sysregs_context_restore(NON_SECURE); 1777 cm_el2_sysregs_context_restore_gic(NON_SECURE); 1778 cm_set_next_eret_context(NON_SECURE); 1779 #else 1780 cm_prepare_el3_exit(NON_SECURE); 1781 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1782 1783 if (is_feat_amu_supported()) { 1784 cm_sysregs_context_restore_amu(NON_SECURE); 1785 } 1786 } 1787 1788 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1789 /******************************************************************************* 1790 * The next set of six functions are used by runtime services to save and restore 1791 * EL1 context on the 'cpu_context' structure for the specified security state. 1792 ******************************************************************************/ 1793 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1794 { 1795 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1796 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1797 1798 #if (!ERRATA_SPECULATIVE_AT) 1799 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1800 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1801 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1802 1803 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1804 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1805 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1806 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1807 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1808 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1809 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1810 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1811 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1812 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1813 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1814 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1815 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1816 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1817 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1818 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1819 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1820 1821 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1822 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1823 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1824 1825 if (CTX_INCLUDE_AARCH32_REGS) { 1826 /* Save Aarch32 registers */ 1827 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1828 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1829 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1830 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1831 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1832 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1833 } 1834 1835 /* Save counter-timer kernel control register */ 1836 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1837 #if NS_TIMER_SWITCH 1838 /* Save NS Timer registers */ 1839 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1840 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1841 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1842 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1843 #endif 1844 1845 if (is_feat_mte2_supported()) { 1846 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1847 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1848 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1849 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1850 } 1851 1852 if (is_feat_ras_supported()) { 1853 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1854 } 1855 1856 if (is_feat_s1pie_supported()) { 1857 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1858 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1859 } 1860 1861 if (is_feat_s1poe_supported()) { 1862 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1863 } 1864 1865 if (is_feat_s2poe_supported()) { 1866 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1867 } 1868 1869 if (is_feat_tcr2_supported()) { 1870 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1871 } 1872 1873 if (is_feat_trf_supported()) { 1874 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1875 } 1876 1877 if (is_feat_csv2_2_supported()) { 1878 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1879 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1880 } 1881 1882 if (is_feat_gcs_supported()) { 1883 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1884 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1885 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1886 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1887 } 1888 1889 if (is_feat_the_supported()) { 1890 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1891 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1892 } 1893 1894 if (is_feat_sctlr2_supported()) { 1895 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1896 } 1897 1898 if (is_feat_ls64_accdata_supported()) { 1899 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1900 } 1901 1902 if (is_feat_step2_supported()) { 1903 write_el1_ctx_step2(ctx, mdstepop_el1, read_mdstepop_el1()); 1904 } 1905 } 1906 1907 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1908 { 1909 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1910 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1911 1912 #if (!ERRATA_SPECULATIVE_AT) 1913 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1914 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1915 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1916 1917 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1918 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1919 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1920 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1921 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1922 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1923 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1924 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1925 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1926 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1927 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1928 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1929 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1930 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1931 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1932 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1933 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1934 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1935 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1936 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1937 1938 if (CTX_INCLUDE_AARCH32_REGS) { 1939 /* Restore Aarch32 registers */ 1940 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1941 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1942 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1943 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1944 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1945 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1946 } 1947 1948 /* Restore counter-timer kernel control register */ 1949 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1950 #if NS_TIMER_SWITCH 1951 /* Restore NS Timer registers */ 1952 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1953 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1954 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1955 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1956 #endif 1957 1958 if (is_feat_mte2_supported()) { 1959 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1960 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1961 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1962 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1963 } 1964 1965 if (is_feat_ras_supported()) { 1966 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1967 } 1968 1969 if (is_feat_s1pie_supported()) { 1970 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1971 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1972 } 1973 1974 if (is_feat_s1poe_supported()) { 1975 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1976 } 1977 1978 if (is_feat_s2poe_supported()) { 1979 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1980 } 1981 1982 if (is_feat_tcr2_supported()) { 1983 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1984 } 1985 1986 if (is_feat_trf_supported()) { 1987 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1988 } 1989 1990 if (is_feat_csv2_2_supported()) { 1991 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1992 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1993 } 1994 1995 if (is_feat_gcs_supported()) { 1996 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1997 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1998 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1999 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 2000 } 2001 2002 if (is_feat_the_supported()) { 2003 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 2004 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 2005 } 2006 2007 if (is_feat_sctlr2_supported()) { 2008 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 2009 } 2010 2011 if (is_feat_ls64_accdata_supported()) { 2012 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 2013 } 2014 2015 if (is_feat_step2_supported()) { 2016 write_mdstepop_el1(read_el1_ctx_step2(ctx, mdstepop_el1)); 2017 } 2018 } 2019 2020 /******************************************************************************* 2021 * The next couple of functions are used by runtime services to save and restore 2022 * EL1 context on the 'cpu_context' structure for the specified security state. 2023 ******************************************************************************/ 2024 void cm_el1_sysregs_context_save(uint32_t security_state) 2025 { 2026 cpu_context_t *ctx; 2027 2028 ctx = cm_get_context(security_state); 2029 assert(ctx != NULL); 2030 2031 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 2032 2033 #if IMAGE_BL31 2034 if (is_feat_amu_supported()) { 2035 cm_sysregs_context_save_amu(security_state); 2036 } 2037 2038 if (security_state == SECURE) { 2039 PUBLISH_EVENT(cm_exited_secure_world); 2040 } else { 2041 PUBLISH_EVENT(cm_exited_normal_world); 2042 } 2043 #endif 2044 } 2045 2046 void cm_el1_sysregs_context_restore(uint32_t security_state) 2047 { 2048 cpu_context_t *ctx; 2049 2050 ctx = cm_get_context(security_state); 2051 assert(ctx != NULL); 2052 2053 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 2054 2055 #if IMAGE_BL31 2056 if (is_feat_amu_supported()) { 2057 cm_sysregs_context_restore_amu(security_state); 2058 } 2059 2060 if (security_state == SECURE) { 2061 PUBLISH_EVENT(cm_entering_secure_world); 2062 } else { 2063 PUBLISH_EVENT(cm_entering_normal_world); 2064 } 2065 #endif 2066 } 2067 2068 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 2069 2070 /******************************************************************************* 2071 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 2072 * given security state with the given entrypoint 2073 ******************************************************************************/ 2074 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 2075 { 2076 cpu_context_t *ctx; 2077 el3_state_t *state; 2078 2079 ctx = cm_get_context(security_state); 2080 assert(ctx != NULL); 2081 2082 /* Populate EL3 state so that ERET jumps to the correct entry */ 2083 state = get_el3state_ctx(ctx); 2084 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2085 } 2086 2087 /******************************************************************************* 2088 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 2089 * pertaining to the given security state 2090 ******************************************************************************/ 2091 void cm_set_elr_spsr_el3(uint32_t security_state, 2092 uintptr_t entrypoint, uint32_t spsr) 2093 { 2094 cpu_context_t *ctx; 2095 el3_state_t *state; 2096 2097 ctx = cm_get_context(security_state); 2098 assert(ctx != NULL); 2099 2100 /* Populate EL3 state so that ERET jumps to the correct entry */ 2101 state = get_el3state_ctx(ctx); 2102 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2103 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2104 } 2105 2106 /******************************************************************************* 2107 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2108 * pertaining to the given security state using the value and bit position 2109 * specified in the parameters. It preserves all other bits. 2110 ******************************************************************************/ 2111 void cm_write_scr_el3_bit(uint32_t security_state, 2112 uint32_t bit_pos, 2113 uint32_t value) 2114 { 2115 cpu_context_t *ctx; 2116 el3_state_t *state; 2117 u_register_t scr_el3; 2118 2119 ctx = cm_get_context(security_state); 2120 assert(ctx != NULL); 2121 2122 /* Ensure that the bit position is a valid one */ 2123 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2124 2125 /* Ensure that the 'value' is only a bit wide */ 2126 assert(value <= 1U); 2127 2128 /* 2129 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2130 * and set it to its new value. 2131 */ 2132 state = get_el3state_ctx(ctx); 2133 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2134 scr_el3 &= ~(1UL << bit_pos); 2135 scr_el3 |= (u_register_t)value << bit_pos; 2136 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2137 } 2138 2139 /******************************************************************************* 2140 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2141 * given security state. 2142 ******************************************************************************/ 2143 u_register_t cm_get_scr_el3(uint32_t security_state) 2144 { 2145 const cpu_context_t *ctx; 2146 const el3_state_t *state; 2147 2148 ctx = cm_get_context(security_state); 2149 assert(ctx != NULL); 2150 2151 /* Populate EL3 state so that ERET jumps to the correct entry */ 2152 state = get_el3state_ctx(ctx); 2153 return read_ctx_reg(state, CTX_SCR_EL3); 2154 } 2155 2156 /******************************************************************************* 2157 * This function is used to program the context that's used for exception 2158 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2159 * the required security state 2160 ******************************************************************************/ 2161 void cm_set_next_eret_context(uint32_t security_state) 2162 { 2163 cpu_context_t *ctx; 2164 2165 ctx = cm_get_context(security_state); 2166 assert(ctx != NULL); 2167 2168 cm_set_next_context(ctx); 2169 } 2170