1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/utils.h> 26 #include <plat/common/platform.h> 27 #include <smccc_helpers.h> 28 29 30 /******************************************************************************* 31 * Context management library initialisation routine. This library is used by 32 * runtime services to share pointers to 'cpu_context' structures for the secure 33 * and non-secure states. Management of the structures and their associated 34 * memory is not done by the context management library e.g. the PSCI service 35 * manages the cpu context used for entry from and exit to the non-secure state. 36 * The Secure payload dispatcher service manages the context(s) corresponding to 37 * the secure state. It also uses this library to get access to the non-secure 38 * state cpu context pointers. 39 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 40 * which will used for programming an entry into a lower EL. The same context 41 * will used to save state upon exception entry from that EL. 42 ******************************************************************************/ 43 void __init cm_init(void) 44 { 45 /* 46 * The context management library has only global data to intialize, but 47 * that will be done when the BSS is zeroed out 48 */ 49 } 50 51 /******************************************************************************* 52 * The following function initializes the cpu_context 'ctx' for 53 * first use, and sets the initial entrypoint state as specified by the 54 * entry_point_info structure. 55 * 56 * The security state to initialize is determined by the SECURE attribute 57 * of the entry_point_info. 58 * 59 * The EE and ST attributes are used to configure the endianness and secure 60 * timer availability for the new execution context. 61 * 62 * To prepare the register state for entry call cm_prepare_el3_exit() and 63 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 64 * cm_e1_sysreg_context_restore(). 65 ******************************************************************************/ 66 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 67 { 68 unsigned int security_state; 69 uint32_t scr_el3, pmcr_el0; 70 el3_state_t *state; 71 gp_regs_t *gp_regs; 72 unsigned long sctlr_elx, actlr_elx; 73 74 assert(ctx != NULL); 75 76 security_state = GET_SECURITY_STATE(ep->h.attr); 77 78 /* Clear any residual register values from the context */ 79 zeromem(ctx, sizeof(*ctx)); 80 81 /* 82 * SCR_EL3 was initialised during reset sequence in macro 83 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 84 * affect the next EL. 85 * 86 * The following fields are initially set to zero and then updated to 87 * the required value depending on the state of the SPSR_EL3 and the 88 * Security state and entrypoint attributes of the next EL. 89 */ 90 scr_el3 = (uint32_t)read_scr(); 91 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 92 SCR_ST_BIT | SCR_HCE_BIT); 93 /* 94 * SCR_NS: Set the security state of the next EL. 95 */ 96 if (security_state != SECURE) 97 scr_el3 |= SCR_NS_BIT; 98 /* 99 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 100 * Exception level as specified by SPSR. 101 */ 102 if (GET_RW(ep->spsr) == MODE_RW_64) 103 scr_el3 |= SCR_RW_BIT; 104 /* 105 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 106 * Secure timer registers to EL3, from AArch64 state only, if specified 107 * by the entrypoint attributes. 108 */ 109 if (EP_GET_ST(ep->h.attr) != 0U) 110 scr_el3 |= SCR_ST_BIT; 111 112 #if !HANDLE_EA_EL3_FIRST 113 /* 114 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 115 * to EL3 when executing at a lower EL. When executing at EL3, External 116 * Aborts are taken to EL3. 117 */ 118 scr_el3 &= ~SCR_EA_BIT; 119 #endif 120 121 #if FAULT_INJECTION_SUPPORT 122 /* Enable fault injection from lower ELs */ 123 scr_el3 |= SCR_FIEN_BIT; 124 #endif 125 126 #if !CTX_INCLUDE_PAUTH_REGS 127 /* 128 * If the pointer authentication registers aren't saved during world 129 * switches the value of the registers can be leaked from the Secure to 130 * the Non-secure world. To prevent this, rather than enabling pointer 131 * authentication everywhere, we only enable it in the Non-secure world. 132 * 133 * If the Secure world wants to use pointer authentication, 134 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 135 */ 136 if (security_state == NON_SECURE) 137 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 138 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 139 140 unsigned int mte = get_armv8_5_mte_support(); 141 142 /* 143 * Enable MTE support unilaterally for normal world if the CPU supports 144 * it. 145 */ 146 if (mte != MTE_UNIMPLEMENTED) { 147 if (security_state == NON_SECURE) { 148 scr_el3 |= SCR_ATA_BIT; 149 } 150 } 151 152 #ifdef IMAGE_BL31 153 /* 154 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 155 * indicated by the interrupt routing model for BL31. 156 */ 157 scr_el3 |= get_scr_el3_from_routing_model(security_state); 158 #endif 159 160 /* 161 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 162 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 163 * next mode is Hyp. 164 */ 165 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 166 || ((GET_RW(ep->spsr) != MODE_RW_64) 167 && (GET_M32(ep->spsr) == MODE32_hyp))) { 168 scr_el3 |= SCR_HCE_BIT; 169 } 170 171 /* 172 * Initialise SCTLR_EL1 to the reset value corresponding to the target 173 * execution state setting all fields rather than relying of the hw. 174 * Some fields have architecturally UNKNOWN reset values and these are 175 * set to zero. 176 * 177 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 178 * 179 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 180 * required by PSCI specification) 181 */ 182 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 183 if (GET_RW(ep->spsr) == MODE_RW_64) 184 sctlr_elx |= SCTLR_EL1_RES1; 185 else { 186 /* 187 * If the target execution state is AArch32 then the following 188 * fields need to be set. 189 * 190 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 191 * instructions are not trapped to EL1. 192 * 193 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 194 * instructions are not trapped to EL1. 195 * 196 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 197 * CP15DMB, CP15DSB, and CP15ISB instructions. 198 */ 199 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 200 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 201 } 202 203 #if ERRATA_A75_764081 204 /* 205 * If workaround of errata 764081 for Cortex-A75 is used then set 206 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 207 */ 208 sctlr_elx |= SCTLR_IESB_BIT; 209 #endif 210 211 /* 212 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 213 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 214 * are not part of the stored cpu_context. 215 */ 216 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 217 218 /* 219 * Base the context ACTLR_EL1 on the current value, as it is 220 * implementation defined. The context restore process will write 221 * the value from the context to the actual register and can cause 222 * problems for processor cores that don't expect certain bits to 223 * be zero. 224 */ 225 actlr_elx = read_actlr_el1(); 226 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 227 228 if (security_state == SECURE) { 229 /* 230 * Initialise PMCR_EL0 for secure context only, setting all 231 * fields rather than relying on hw. Some fields are 232 * architecturally UNKNOWN on reset. 233 * 234 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 235 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 236 * that changes PMCCNTR_EL0[63] from 1 to 0. 237 * 238 * PMCR_EL0.DP: Set to one so that the cycle counter, 239 * PMCCNTR_EL0 does not count when event counting is prohibited. 240 * 241 * PMCR_EL0.X: Set to zero to disable export of events. 242 * 243 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 244 * counts on every clock cycle. 245 */ 246 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT 247 | PMCR_EL0_DP_BIT) 248 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)); 249 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0); 250 } 251 252 /* Populate EL3 state so that we've the right context before doing ERET */ 253 state = get_el3state_ctx(ctx); 254 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 255 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 256 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 257 258 /* 259 * Store the X0-X7 value from the entrypoint into the context 260 * Use memcpy as we are in control of the layout of the structures 261 */ 262 gp_regs = get_gpregs_ctx(ctx); 263 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 264 } 265 266 /******************************************************************************* 267 * Enable architecture extensions on first entry to Non-secure world. 268 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 269 * it is zero. 270 ******************************************************************************/ 271 static void enable_extensions_nonsecure(bool el2_unused) 272 { 273 #if IMAGE_BL31 274 #if ENABLE_SPE_FOR_LOWER_ELS 275 spe_enable(el2_unused); 276 #endif 277 278 #if ENABLE_AMU 279 amu_enable(el2_unused); 280 #endif 281 282 #if ENABLE_SVE_FOR_NS 283 sve_enable(el2_unused); 284 #endif 285 286 #if ENABLE_MPAM_FOR_LOWER_ELS 287 mpam_enable(el2_unused); 288 #endif 289 #endif 290 } 291 292 /******************************************************************************* 293 * The following function initializes the cpu_context for a CPU specified by 294 * its `cpu_idx` for first use, and sets the initial entrypoint state as 295 * specified by the entry_point_info structure. 296 ******************************************************************************/ 297 void cm_init_context_by_index(unsigned int cpu_idx, 298 const entry_point_info_t *ep) 299 { 300 cpu_context_t *ctx; 301 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 302 cm_setup_context(ctx, ep); 303 } 304 305 /******************************************************************************* 306 * The following function initializes the cpu_context for the current CPU 307 * for first use, and sets the initial entrypoint state as specified by the 308 * entry_point_info structure. 309 ******************************************************************************/ 310 void cm_init_my_context(const entry_point_info_t *ep) 311 { 312 cpu_context_t *ctx; 313 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 314 cm_setup_context(ctx, ep); 315 } 316 317 /******************************************************************************* 318 * Prepare the CPU system registers for first entry into secure or normal world 319 * 320 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 321 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 322 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 323 * For all entries, the EL1 registers are initialized from the cpu_context 324 ******************************************************************************/ 325 void cm_prepare_el3_exit(uint32_t security_state) 326 { 327 uint32_t sctlr_elx, scr_el3, mdcr_el2; 328 cpu_context_t *ctx = cm_get_context(security_state); 329 bool el2_unused = false; 330 uint64_t hcr_el2 = 0U; 331 332 assert(ctx != NULL); 333 334 if (security_state == NON_SECURE) { 335 scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx), 336 CTX_SCR_EL3); 337 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 338 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 339 sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx), 340 CTX_SCTLR_EL1); 341 sctlr_elx &= SCTLR_EE_BIT; 342 sctlr_elx |= SCTLR_EL2_RES1; 343 #if ERRATA_A75_764081 344 /* 345 * If workaround of errata 764081 for Cortex-A75 is used 346 * then set SCTLR_EL2.IESB to enable Implicit Error 347 * Synchronization Barrier. 348 */ 349 sctlr_elx |= SCTLR_IESB_BIT; 350 #endif 351 write_sctlr_el2(sctlr_elx); 352 } else if (el_implemented(2) != EL_IMPL_NONE) { 353 el2_unused = true; 354 355 /* 356 * EL2 present but unused, need to disable safely. 357 * SCTLR_EL2 can be ignored in this case. 358 * 359 * Set EL2 register width appropriately: Set HCR_EL2 360 * field to match SCR_EL3.RW. 361 */ 362 if ((scr_el3 & SCR_RW_BIT) != 0U) 363 hcr_el2 |= HCR_RW_BIT; 364 365 /* 366 * For Armv8.3 pointer authentication feature, disable 367 * traps to EL2 when accessing key registers or using 368 * pointer authentication instructions from lower ELs. 369 */ 370 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 371 372 write_hcr_el2(hcr_el2); 373 374 /* 375 * Initialise CPTR_EL2 setting all fields rather than 376 * relying on the hw. All fields have architecturally 377 * UNKNOWN reset values. 378 * 379 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 380 * accesses to the CPACR_EL1 or CPACR from both 381 * Execution states do not trap to EL2. 382 * 383 * CPTR_EL2.TTA: Set to zero so that Non-secure System 384 * register accesses to the trace registers from both 385 * Execution states do not trap to EL2. 386 * 387 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 388 * to SIMD and floating-point functionality from both 389 * Execution states do not trap to EL2. 390 */ 391 write_cptr_el2(CPTR_EL2_RESET_VAL & 392 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 393 | CPTR_EL2_TFP_BIT)); 394 395 /* 396 * Initialise CNTHCTL_EL2. All fields are 397 * architecturally UNKNOWN on reset and are set to zero 398 * except for field(s) listed below. 399 * 400 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 401 * Hyp mode of Non-secure EL0 and EL1 accesses to the 402 * physical timer registers. 403 * 404 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 405 * Hyp mode of Non-secure EL0 and EL1 accesses to the 406 * physical counter registers. 407 */ 408 write_cnthctl_el2(CNTHCTL_RESET_VAL | 409 EL1PCEN_BIT | EL1PCTEN_BIT); 410 411 /* 412 * Initialise CNTVOFF_EL2 to zero as it resets to an 413 * architecturally UNKNOWN value. 414 */ 415 write_cntvoff_el2(0); 416 417 /* 418 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 419 * MPIDR_EL1 respectively. 420 */ 421 write_vpidr_el2(read_midr_el1()); 422 write_vmpidr_el2(read_mpidr_el1()); 423 424 /* 425 * Initialise VTTBR_EL2. All fields are architecturally 426 * UNKNOWN on reset. 427 * 428 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 429 * 2 address translation is disabled, cache maintenance 430 * operations depend on the VMID. 431 * 432 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 433 * translation is disabled. 434 */ 435 write_vttbr_el2(VTTBR_RESET_VAL & 436 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 437 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 438 439 /* 440 * Initialise MDCR_EL2, setting all fields rather than 441 * relying on hw. Some fields are architecturally 442 * UNKNOWN on reset. 443 * 444 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 445 * EL1 System register accesses to the Debug ROM 446 * registers are not trapped to EL2. 447 * 448 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 449 * System register accesses to the powerdown debug 450 * registers are not trapped to EL2. 451 * 452 * MDCR_EL2.TDA: Set to zero so that System register 453 * accesses to the debug registers do not trap to EL2. 454 * 455 * MDCR_EL2.TDE: Set to zero so that debug exceptions 456 * are not routed to EL2. 457 * 458 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 459 * Monitors. 460 * 461 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 462 * EL1 accesses to all Performance Monitors registers 463 * are not trapped to EL2. 464 * 465 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 466 * and EL1 accesses to the PMCR_EL0 or PMCR are not 467 * trapped to EL2. 468 * 469 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 470 * architecturally-defined reset value. 471 */ 472 mdcr_el2 = ((MDCR_EL2_RESET_VAL | 473 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 474 >> PMCR_EL0_N_SHIFT)) & 475 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT 476 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT 477 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT 478 | MDCR_EL2_TPMCR_BIT)); 479 480 write_mdcr_el2(mdcr_el2); 481 482 /* 483 * Initialise HSTR_EL2. All fields are architecturally 484 * UNKNOWN on reset. 485 * 486 * HSTR_EL2.T<n>: Set all these fields to zero so that 487 * Non-secure EL0 or EL1 accesses to System registers 488 * do not trap to EL2. 489 */ 490 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 491 /* 492 * Initialise CNTHP_CTL_EL2. All fields are 493 * architecturally UNKNOWN on reset. 494 * 495 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 496 * physical timer and prevent timer interrupts. 497 */ 498 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 499 ~(CNTHP_CTL_ENABLE_BIT)); 500 } 501 enable_extensions_nonsecure(el2_unused); 502 } 503 504 cm_el1_sysregs_context_restore(security_state); 505 cm_set_next_eret_context(security_state); 506 } 507 508 /******************************************************************************* 509 * The next four functions are used by runtime services to save and restore 510 * EL1 context on the 'cpu_context' structure for the specified security 511 * state. 512 ******************************************************************************/ 513 void cm_el1_sysregs_context_save(uint32_t security_state) 514 { 515 cpu_context_t *ctx; 516 517 ctx = cm_get_context(security_state); 518 assert(ctx != NULL); 519 520 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 521 522 #if IMAGE_BL31 523 if (security_state == SECURE) 524 PUBLISH_EVENT(cm_exited_secure_world); 525 else 526 PUBLISH_EVENT(cm_exited_normal_world); 527 #endif 528 } 529 530 void cm_el1_sysregs_context_restore(uint32_t security_state) 531 { 532 cpu_context_t *ctx; 533 534 ctx = cm_get_context(security_state); 535 assert(ctx != NULL); 536 537 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 538 539 #if IMAGE_BL31 540 if (security_state == SECURE) 541 PUBLISH_EVENT(cm_entering_secure_world); 542 else 543 PUBLISH_EVENT(cm_entering_normal_world); 544 #endif 545 } 546 547 /******************************************************************************* 548 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 549 * given security state with the given entrypoint 550 ******************************************************************************/ 551 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 552 { 553 cpu_context_t *ctx; 554 el3_state_t *state; 555 556 ctx = cm_get_context(security_state); 557 assert(ctx != NULL); 558 559 /* Populate EL3 state so that ERET jumps to the correct entry */ 560 state = get_el3state_ctx(ctx); 561 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 562 } 563 564 /******************************************************************************* 565 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 566 * pertaining to the given security state 567 ******************************************************************************/ 568 void cm_set_elr_spsr_el3(uint32_t security_state, 569 uintptr_t entrypoint, uint32_t spsr) 570 { 571 cpu_context_t *ctx; 572 el3_state_t *state; 573 574 ctx = cm_get_context(security_state); 575 assert(ctx != NULL); 576 577 /* Populate EL3 state so that ERET jumps to the correct entry */ 578 state = get_el3state_ctx(ctx); 579 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 580 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 581 } 582 583 /******************************************************************************* 584 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 585 * pertaining to the given security state using the value and bit position 586 * specified in the parameters. It preserves all other bits. 587 ******************************************************************************/ 588 void cm_write_scr_el3_bit(uint32_t security_state, 589 uint32_t bit_pos, 590 uint32_t value) 591 { 592 cpu_context_t *ctx; 593 el3_state_t *state; 594 uint32_t scr_el3; 595 596 ctx = cm_get_context(security_state); 597 assert(ctx != NULL); 598 599 /* Ensure that the bit position is a valid one */ 600 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 601 602 /* Ensure that the 'value' is only a bit wide */ 603 assert(value <= 1U); 604 605 /* 606 * Get the SCR_EL3 value from the cpu context, clear the desired bit 607 * and set it to its new value. 608 */ 609 state = get_el3state_ctx(ctx); 610 scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 611 scr_el3 &= ~(1U << bit_pos); 612 scr_el3 |= value << bit_pos; 613 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 614 } 615 616 /******************************************************************************* 617 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 618 * given security state. 619 ******************************************************************************/ 620 uint32_t cm_get_scr_el3(uint32_t security_state) 621 { 622 cpu_context_t *ctx; 623 el3_state_t *state; 624 625 ctx = cm_get_context(security_state); 626 assert(ctx != NULL); 627 628 /* Populate EL3 state so that ERET jumps to the correct entry */ 629 state = get_el3state_ctx(ctx); 630 return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 631 } 632 633 /******************************************************************************* 634 * This function is used to program the context that's used for exception 635 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 636 * the required security state 637 ******************************************************************************/ 638 void cm_set_next_eret_context(uint32_t security_state) 639 { 640 cpu_context_t *ctx; 641 642 ctx = cm_get_context(security_state); 643 assert(ctx != NULL); 644 645 cm_set_next_context(ctx); 646 } 647