1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/cpu_data.h> 24 #include <lib/el3_runtime/pubsub_events.h> 25 #include <lib/extensions/amu.h> 26 #include <lib/extensions/brbe.h> 27 #include <lib/extensions/mpam.h> 28 #include <lib/extensions/pmuv3.h> 29 #include <lib/extensions/sme.h> 30 #include <lib/extensions/spe.h> 31 #include <lib/extensions/sve.h> 32 #include <lib/extensions/sys_reg_trace.h> 33 #include <lib/extensions/trbe.h> 34 #include <lib/extensions/trf.h> 35 #include <lib/utils.h> 36 37 #if ENABLE_FEAT_TWED 38 /* Make sure delay value fits within the range(0-15) */ 39 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 40 #endif /* ENABLE_FEAT_TWED */ 41 42 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 43 static bool has_secure_perworld_init; 44 45 static void manage_extensions_common(cpu_context_t *ctx); 46 static void manage_extensions_nonsecure(cpu_context_t *ctx); 47 static void manage_extensions_secure(cpu_context_t *ctx); 48 static void manage_extensions_secure_per_world(void); 49 50 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 51 { 52 u_register_t sctlr_elx, actlr_elx; 53 54 /* 55 * Initialise SCTLR_EL1 to the reset value corresponding to the target 56 * execution state setting all fields rather than relying on the hw. 57 * Some fields have architecturally UNKNOWN reset values and these are 58 * set to zero. 59 * 60 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 61 * 62 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 63 * required by PSCI specification) 64 */ 65 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 66 if (GET_RW(ep->spsr) == MODE_RW_64) { 67 sctlr_elx |= SCTLR_EL1_RES1; 68 } else { 69 /* 70 * If the target execution state is AArch32 then the following 71 * fields need to be set. 72 * 73 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 74 * instructions are not trapped to EL1. 75 * 76 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 77 * instructions are not trapped to EL1. 78 * 79 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 80 * CP15DMB, CP15DSB, and CP15ISB instructions. 81 */ 82 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 83 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 84 } 85 86 #if ERRATA_A75_764081 87 /* 88 * If workaround of errata 764081 for Cortex-A75 is used then set 89 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 90 */ 91 sctlr_elx |= SCTLR_IESB_BIT; 92 #endif 93 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 94 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 95 96 /* 97 * Base the context ACTLR_EL1 on the current value, as it is 98 * implementation defined. The context restore process will write 99 * the value from the context to the actual register and can cause 100 * problems for processor cores that don't expect certain bits to 101 * be zero. 102 */ 103 actlr_elx = read_actlr_el1(); 104 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 105 } 106 107 /****************************************************************************** 108 * This function performs initializations that are specific to SECURE state 109 * and updates the cpu context specified by 'ctx'. 110 *****************************************************************************/ 111 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 112 { 113 u_register_t scr_el3; 114 el3_state_t *state; 115 116 state = get_el3state_ctx(ctx); 117 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 118 119 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 120 /* 121 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 122 * indicated by the interrupt routing model for BL31. 123 */ 124 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 125 #endif 126 127 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 128 if (is_feat_mte2_supported()) { 129 scr_el3 |= SCR_ATA_BIT; 130 } 131 132 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 133 134 /* 135 * Initialize EL1 context registers unless SPMC is running 136 * at S-EL2. 137 */ 138 #if !SPMD_SPM_AT_SEL2 139 setup_el1_context(ctx, ep); 140 #endif 141 142 manage_extensions_secure(ctx); 143 144 /** 145 * manage_extensions_secure_per_world api has to be executed once, 146 * as the registers getting initialised, maintain constant value across 147 * all the cpus for the secure world. 148 * Henceforth, this check ensures that the registers are initialised once 149 * and avoids re-initialization from multiple cores. 150 */ 151 if (!has_secure_perworld_init) { 152 manage_extensions_secure_per_world(); 153 } 154 155 } 156 157 #if ENABLE_RME 158 /****************************************************************************** 159 * This function performs initializations that are specific to REALM state 160 * and updates the cpu context specified by 'ctx'. 161 *****************************************************************************/ 162 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 163 { 164 u_register_t scr_el3; 165 el3_state_t *state; 166 167 state = get_el3state_ctx(ctx); 168 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 169 170 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 171 172 /* CSV2 version 2 and above */ 173 if (is_feat_csv2_2_supported()) { 174 /* Enable access to the SCXTNUM_ELx registers. */ 175 scr_el3 |= SCR_EnSCXT_BIT; 176 } 177 178 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 179 } 180 #endif /* ENABLE_RME */ 181 182 /****************************************************************************** 183 * This function performs initializations that are specific to NON-SECURE state 184 * and updates the cpu context specified by 'ctx'. 185 *****************************************************************************/ 186 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 187 { 188 u_register_t scr_el3; 189 el3_state_t *state; 190 191 state = get_el3state_ctx(ctx); 192 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 193 194 /* SCR_NS: Set the NS bit */ 195 scr_el3 |= SCR_NS_BIT; 196 197 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 198 if (is_feat_mte2_supported()) { 199 scr_el3 |= SCR_ATA_BIT; 200 } 201 202 #if !CTX_INCLUDE_PAUTH_REGS 203 /* 204 * Pointer Authentication feature, if present, is always enabled by default 205 * for Non secure lower exception levels. We do not have an explicit 206 * flag to set it. 207 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 208 * exception levels of secure and realm worlds. 209 * 210 * To prevent the leakage between the worlds during world switch, 211 * we enable it only for the non-secure world. 212 * 213 * If the Secure/realm world wants to use pointer authentication, 214 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 215 * it will be enabled globally for all the contexts. 216 * 217 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 218 * other than EL3 219 * 220 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 221 * than EL3 222 */ 223 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 224 225 #endif /* CTX_INCLUDE_PAUTH_REGS */ 226 227 #if HANDLE_EA_EL3_FIRST_NS 228 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 229 scr_el3 |= SCR_EA_BIT; 230 #endif 231 232 #if RAS_TRAP_NS_ERR_REC_ACCESS 233 /* 234 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 235 * and RAS ERX registers from EL1 and EL2(from any security state) 236 * are trapped to EL3. 237 * Set here to trap only for NS EL1/EL2 238 * 239 */ 240 scr_el3 |= SCR_TERR_BIT; 241 #endif 242 243 /* CSV2 version 2 and above */ 244 if (is_feat_csv2_2_supported()) { 245 /* Enable access to the SCXTNUM_ELx registers. */ 246 scr_el3 |= SCR_EnSCXT_BIT; 247 } 248 249 #ifdef IMAGE_BL31 250 /* 251 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 252 * indicated by the interrupt routing model for BL31. 253 */ 254 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 255 #endif 256 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 257 258 /* Initialize EL1 context registers */ 259 setup_el1_context(ctx, ep); 260 261 /* Initialize EL2 context registers */ 262 #if CTX_INCLUDE_EL2_REGS 263 264 /* 265 * Initialize SCTLR_EL2 context register with reset value. 266 */ 267 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 268 269 if (is_feat_hcx_supported()) { 270 /* 271 * Initialize register HCRX_EL2 with its init value. 272 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 273 * chance that this can lead to unexpected behavior in lower 274 * ELs that have not been updated since the introduction of 275 * this feature if not properly initialized, especially when 276 * it comes to those bits that enable/disable traps. 277 */ 278 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 279 HCRX_EL2_INIT_VAL); 280 } 281 282 if (is_feat_fgt_supported()) { 283 /* 284 * Initialize HFG*_EL2 registers with a default value so legacy 285 * systems unaware of FEAT_FGT do not get trapped due to their lack 286 * of initialization for this feature. 287 */ 288 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 289 HFGITR_EL2_INIT_VAL); 290 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 291 HFGRTR_EL2_INIT_VAL); 292 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 293 HFGWTR_EL2_INIT_VAL); 294 } 295 296 #endif /* CTX_INCLUDE_EL2_REGS */ 297 298 manage_extensions_nonsecure(ctx); 299 } 300 301 /******************************************************************************* 302 * The following function performs initialization of the cpu_context 'ctx' 303 * for first use that is common to all security states, and sets the 304 * initial entrypoint state as specified by the entry_point_info structure. 305 * 306 * The EE and ST attributes are used to configure the endianness and secure 307 * timer availability for the new execution context. 308 ******************************************************************************/ 309 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 310 { 311 u_register_t scr_el3; 312 u_register_t mdcr_el3; 313 el3_state_t *state; 314 gp_regs_t *gp_regs; 315 316 state = get_el3state_ctx(ctx); 317 318 /* Clear any residual register values from the context */ 319 zeromem(ctx, sizeof(*ctx)); 320 321 /* 322 * The lower-EL context is zeroed so that no stale values leak to a world. 323 * It is assumed that an all-zero lower-EL context is good enough for it 324 * to boot correctly. However, there are very few registers where this 325 * is not true and some values need to be recreated. 326 */ 327 #if CTX_INCLUDE_EL2_REGS 328 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 329 330 /* 331 * These bits are set in the gicv3 driver. Losing them (especially the 332 * SRE bit) is problematic for all worlds. Henceforth recreate them. 333 */ 334 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 335 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 336 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 337 #endif /* CTX_INCLUDE_EL2_REGS */ 338 339 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 340 scr_el3 = SCR_RESET_VAL; 341 342 /* 343 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 344 * EL2, EL1 and EL0 are not trapped to EL3. 345 * 346 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 347 * EL2, EL1 and EL0 are not trapped to EL3. 348 * 349 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 350 * both Security states and both Execution states. 351 * 352 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 353 * Non-secure memory. 354 */ 355 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 356 357 scr_el3 |= SCR_SIF_BIT; 358 359 /* 360 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 361 * Exception level as specified by SPSR. 362 */ 363 if (GET_RW(ep->spsr) == MODE_RW_64) { 364 scr_el3 |= SCR_RW_BIT; 365 } 366 367 /* 368 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 369 * Secure timer registers to EL3, from AArch64 state only, if specified 370 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 371 * bit always behaves as 1 (i.e. secure physical timer register access 372 * is not trapped) 373 */ 374 if (EP_GET_ST(ep->h.attr) != 0U) { 375 scr_el3 |= SCR_ST_BIT; 376 } 377 378 /* 379 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 380 * SCR_EL3.HXEn. 381 */ 382 if (is_feat_hcx_supported()) { 383 scr_el3 |= SCR_HXEn_BIT; 384 } 385 386 /* 387 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 388 * registers are trapped to EL3. 389 */ 390 #if ENABLE_FEAT_RNG_TRAP 391 scr_el3 |= SCR_TRNDR_BIT; 392 #endif 393 394 #if FAULT_INJECTION_SUPPORT 395 /* Enable fault injection from lower ELs */ 396 scr_el3 |= SCR_FIEN_BIT; 397 #endif 398 399 #if CTX_INCLUDE_PAUTH_REGS 400 /* 401 * Enable Pointer Authentication globally for all the worlds. 402 * 403 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 404 * other than EL3 405 * 406 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 407 * than EL3 408 */ 409 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 410 #endif /* CTX_INCLUDE_PAUTH_REGS */ 411 412 /* 413 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 414 */ 415 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 416 scr_el3 |= SCR_TCR2EN_BIT; 417 } 418 419 /* 420 * SCR_EL3.PIEN: Enable permission indirection and overlay 421 * registers for AArch64 if present. 422 */ 423 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 424 scr_el3 |= SCR_PIEN_BIT; 425 } 426 427 /* 428 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 429 */ 430 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 431 scr_el3 |= SCR_GCSEn_BIT; 432 } 433 434 /* 435 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 436 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 437 * next mode is Hyp. 438 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 439 * same conditions as HVC instructions and when the processor supports 440 * ARMv8.6-FGT. 441 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 442 * CNTPOFF_EL2 register under the same conditions as HVC instructions 443 * and when the processor supports ECV. 444 */ 445 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 446 || ((GET_RW(ep->spsr) != MODE_RW_64) 447 && (GET_M32(ep->spsr) == MODE32_hyp))) { 448 scr_el3 |= SCR_HCE_BIT; 449 450 if (is_feat_fgt_supported()) { 451 scr_el3 |= SCR_FGTEN_BIT; 452 } 453 454 if (is_feat_ecv_supported()) { 455 scr_el3 |= SCR_ECVEN_BIT; 456 } 457 } 458 459 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 460 if (is_feat_twed_supported()) { 461 /* Set delay in SCR_EL3 */ 462 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 463 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 464 << SCR_TWEDEL_SHIFT); 465 466 /* Enable WFE delay */ 467 scr_el3 |= SCR_TWEDEn_BIT; 468 } 469 470 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 471 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 472 if (is_feat_sel2_supported()) { 473 scr_el3 |= SCR_EEL2_BIT; 474 } 475 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 476 477 /* 478 * Populate EL3 state so that we've the right context 479 * before doing ERET 480 */ 481 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 482 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 483 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 484 485 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 486 mdcr_el3 = MDCR_EL3_RESET_VAL; 487 488 /* --------------------------------------------------------------------- 489 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 490 * Some fields are architecturally UNKNOWN on reset. 491 * 492 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 493 * Debug exceptions, other than Breakpoint Instruction exceptions, are 494 * disabled from all ELs in Secure state. 495 * 496 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 497 * privileged debug from S-EL1. 498 * 499 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 500 * access to the powerdown debug registers do not trap to EL3. 501 * 502 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 503 * debug registers, other than those registers that are controlled by 504 * MDCR_EL3.TDOSA. 505 */ 506 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 507 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 508 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 509 510 /* 511 * Configure MDCR_EL3 register as applicable for each world 512 * (NS/Secure/Realm) context. 513 */ 514 manage_extensions_common(ctx); 515 516 /* 517 * Store the X0-X7 value from the entrypoint into the context 518 * Use memcpy as we are in control of the layout of the structures 519 */ 520 gp_regs = get_gpregs_ctx(ctx); 521 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 522 } 523 524 /******************************************************************************* 525 * Context management library initialization routine. This library is used by 526 * runtime services to share pointers to 'cpu_context' structures for secure 527 * non-secure and realm states. Management of the structures and their associated 528 * memory is not done by the context management library e.g. the PSCI service 529 * manages the cpu context used for entry from and exit to the non-secure state. 530 * The Secure payload dispatcher service manages the context(s) corresponding to 531 * the secure state. It also uses this library to get access to the non-secure 532 * state cpu context pointers. 533 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 534 * which will be used for programming an entry into a lower EL. The same context 535 * will be used to save state upon exception entry from that EL. 536 ******************************************************************************/ 537 void __init cm_init(void) 538 { 539 /* 540 * The context management library has only global data to initialize, but 541 * that will be done when the BSS is zeroed out. 542 */ 543 } 544 545 /******************************************************************************* 546 * This is the high-level function used to initialize the cpu_context 'ctx' for 547 * first use. It performs initializations that are common to all security states 548 * and initializations specific to the security state specified in 'ep' 549 ******************************************************************************/ 550 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 551 { 552 unsigned int security_state; 553 554 assert(ctx != NULL); 555 556 /* 557 * Perform initializations that are common 558 * to all security states 559 */ 560 setup_context_common(ctx, ep); 561 562 security_state = GET_SECURITY_STATE(ep->h.attr); 563 564 /* Perform security state specific initializations */ 565 switch (security_state) { 566 case SECURE: 567 setup_secure_context(ctx, ep); 568 break; 569 #if ENABLE_RME 570 case REALM: 571 setup_realm_context(ctx, ep); 572 break; 573 #endif 574 case NON_SECURE: 575 setup_ns_context(ctx, ep); 576 break; 577 default: 578 ERROR("Invalid security state\n"); 579 panic(); 580 break; 581 } 582 } 583 584 /******************************************************************************* 585 * Enable architecture extensions for EL3 execution. This function only updates 586 * registers in-place which are expected to either never change or be 587 * overwritten by el3_exit. 588 ******************************************************************************/ 589 #if IMAGE_BL31 590 void cm_manage_extensions_el3(void) 591 { 592 if (is_feat_amu_supported()) { 593 amu_init_el3(); 594 } 595 596 if (is_feat_sme_supported()) { 597 sme_init_el3(); 598 } 599 600 pmuv3_init_el3(); 601 } 602 #endif /* IMAGE_BL31 */ 603 604 /****************************************************************************** 605 * Function to initialise the registers with the RESET values in the context 606 * memory, which are maintained per world. 607 ******************************************************************************/ 608 #if IMAGE_BL31 609 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 610 { 611 /* 612 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 613 * 614 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 615 * by Advanced SIMD, floating-point or SVE instructions (if 616 * implemented) do not trap to EL3. 617 * 618 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 619 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 620 */ 621 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 622 623 per_world_ctx->ctx_cptr_el3 = cptr_el3; 624 625 /* 626 * Initialize MPAM3_EL3 to its default reset value 627 * 628 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 629 * all lower ELn MPAM3_EL3 register access to, trap to EL3 630 */ 631 632 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 633 } 634 #endif /* IMAGE_BL31 */ 635 636 /******************************************************************************* 637 * Initialise per_world_context for Non-Secure world. 638 * This function enables the architecture extensions, which have same value 639 * across the cores for the non-secure world. 640 ******************************************************************************/ 641 #if IMAGE_BL31 642 void manage_extensions_nonsecure_per_world(void) 643 { 644 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 645 646 if (is_feat_sme_supported()) { 647 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 648 } 649 650 if (is_feat_sve_supported()) { 651 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 652 } 653 654 if (is_feat_amu_supported()) { 655 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 656 } 657 658 if (is_feat_sys_reg_trace_supported()) { 659 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 660 } 661 662 if (is_feat_mpam_supported()) { 663 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 664 } 665 } 666 #endif /* IMAGE_BL31 */ 667 668 /******************************************************************************* 669 * Initialise per_world_context for Secure world. 670 * This function enables the architecture extensions, which have same value 671 * across the cores for the secure world. 672 ******************************************************************************/ 673 static void manage_extensions_secure_per_world(void) 674 { 675 #if IMAGE_BL31 676 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 677 678 if (is_feat_sme_supported()) { 679 680 if (ENABLE_SME_FOR_SWD) { 681 /* 682 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 683 * SME, SVE, and FPU/SIMD context properly managed. 684 */ 685 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 686 } else { 687 /* 688 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 689 * world can safely use the associated registers. 690 */ 691 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 692 } 693 } 694 if (is_feat_sve_supported()) { 695 if (ENABLE_SVE_FOR_SWD) { 696 /* 697 * Enable SVE and FPU in secure context, SPM must ensure 698 * that the SVE and FPU register contexts are properly managed. 699 */ 700 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 701 } else { 702 /* 703 * Disable SVE and FPU in secure context so non-secure world 704 * can safely use them. 705 */ 706 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 707 } 708 } 709 710 /* NS can access this but Secure shouldn't */ 711 if (is_feat_sys_reg_trace_supported()) { 712 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 713 } 714 715 has_secure_perworld_init = true; 716 #endif /* IMAGE_BL31 */ 717 } 718 719 /******************************************************************************* 720 * Enable architecture extensions on first entry to Non-secure world only 721 * and disable for secure world. 722 * 723 * NOTE: Arch features which have been provided with the capability of getting 724 * enabled only for non-secure world and being disabled for secure world are 725 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 726 ******************************************************************************/ 727 static void manage_extensions_common(cpu_context_t *ctx) 728 { 729 #if IMAGE_BL31 730 if (is_feat_spe_supported()) { 731 /* 732 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 733 */ 734 spe_enable(ctx); 735 } 736 737 if (is_feat_trbe_supported()) { 738 /* 739 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 740 * Realm state. 741 */ 742 trbe_enable(ctx); 743 } 744 745 if (is_feat_trf_supported()) { 746 /* 747 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 748 */ 749 trf_enable(ctx); 750 } 751 752 if (is_feat_brbe_supported()) { 753 /* 754 * Enable FEAT_BRBE for Non-Secure and prohibit for Secure state. 755 */ 756 brbe_enable(ctx); 757 } 758 #endif /* IMAGE_BL31 */ 759 } 760 761 /******************************************************************************* 762 * Enable architecture extensions on first entry to Non-secure world. 763 ******************************************************************************/ 764 static void manage_extensions_nonsecure(cpu_context_t *ctx) 765 { 766 #if IMAGE_BL31 767 if (is_feat_amu_supported()) { 768 amu_enable(ctx); 769 } 770 771 if (is_feat_sme_supported()) { 772 sme_enable(ctx); 773 } 774 775 pmuv3_enable(ctx); 776 #endif /* IMAGE_BL31 */ 777 } 778 779 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 780 static __unused void enable_pauth_el2(void) 781 { 782 u_register_t hcr_el2 = read_hcr_el2(); 783 /* 784 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 785 * accessing key registers or using pointer authentication instructions 786 * from lower ELs. 787 */ 788 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 789 790 write_hcr_el2(hcr_el2); 791 } 792 793 #if INIT_UNUSED_NS_EL2 794 /******************************************************************************* 795 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 796 * world when EL2 is empty and unused. 797 ******************************************************************************/ 798 static void manage_extensions_nonsecure_el2_unused(void) 799 { 800 #if IMAGE_BL31 801 if (is_feat_spe_supported()) { 802 spe_init_el2_unused(); 803 } 804 805 if (is_feat_amu_supported()) { 806 amu_init_el2_unused(); 807 } 808 809 if (is_feat_mpam_supported()) { 810 mpam_init_el2_unused(); 811 } 812 813 if (is_feat_trbe_supported()) { 814 trbe_init_el2_unused(); 815 } 816 817 if (is_feat_sys_reg_trace_supported()) { 818 sys_reg_trace_init_el2_unused(); 819 } 820 821 if (is_feat_trf_supported()) { 822 trf_init_el2_unused(); 823 } 824 825 pmuv3_init_el2_unused(); 826 827 if (is_feat_sve_supported()) { 828 sve_init_el2_unused(); 829 } 830 831 if (is_feat_sme_supported()) { 832 sme_init_el2_unused(); 833 } 834 835 #if ENABLE_PAUTH 836 enable_pauth_el2(); 837 #endif /* ENABLE_PAUTH */ 838 #endif /* IMAGE_BL31 */ 839 } 840 #endif /* INIT_UNUSED_NS_EL2 */ 841 842 /******************************************************************************* 843 * Enable architecture extensions on first entry to Secure world. 844 ******************************************************************************/ 845 static void manage_extensions_secure(cpu_context_t *ctx) 846 { 847 #if IMAGE_BL31 848 if (is_feat_sme_supported()) { 849 if (ENABLE_SME_FOR_SWD) { 850 /* 851 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 852 * must ensure SME, SVE, and FPU/SIMD context properly managed. 853 */ 854 sme_init_el3(); 855 sme_enable(ctx); 856 } else { 857 /* 858 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 859 * world can safely use the associated registers. 860 */ 861 sme_disable(ctx); 862 } 863 } 864 #endif /* IMAGE_BL31 */ 865 } 866 867 #if !IMAGE_BL1 868 /******************************************************************************* 869 * The following function initializes the cpu_context for a CPU specified by 870 * its `cpu_idx` for first use, and sets the initial entrypoint state as 871 * specified by the entry_point_info structure. 872 ******************************************************************************/ 873 void cm_init_context_by_index(unsigned int cpu_idx, 874 const entry_point_info_t *ep) 875 { 876 cpu_context_t *ctx; 877 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 878 cm_setup_context(ctx, ep); 879 } 880 #endif /* !IMAGE_BL1 */ 881 882 /******************************************************************************* 883 * The following function initializes the cpu_context for the current CPU 884 * for first use, and sets the initial entrypoint state as specified by the 885 * entry_point_info structure. 886 ******************************************************************************/ 887 void cm_init_my_context(const entry_point_info_t *ep) 888 { 889 cpu_context_t *ctx; 890 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 891 cm_setup_context(ctx, ep); 892 } 893 894 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 895 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 896 { 897 #if INIT_UNUSED_NS_EL2 898 u_register_t hcr_el2 = HCR_RESET_VAL; 899 u_register_t mdcr_el2; 900 u_register_t scr_el3; 901 902 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 903 904 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 905 if ((scr_el3 & SCR_RW_BIT) != 0U) { 906 hcr_el2 |= HCR_RW_BIT; 907 } 908 909 write_hcr_el2(hcr_el2); 910 911 /* 912 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 913 * All fields have architecturally UNKNOWN reset values. 914 */ 915 write_cptr_el2(CPTR_EL2_RESET_VAL); 916 917 /* 918 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 919 * reset and are set to zero except for field(s) listed below. 920 * 921 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 922 * Non-secure EL0 and EL1 accesses to the physical timer registers. 923 * 924 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 925 * Non-secure EL0 and EL1 accesses to the physical counter registers. 926 */ 927 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 928 929 /* 930 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 931 * UNKNOWN value. 932 */ 933 write_cntvoff_el2(0); 934 935 /* 936 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 937 * respectively. 938 */ 939 write_vpidr_el2(read_midr_el1()); 940 write_vmpidr_el2(read_mpidr_el1()); 941 942 /* 943 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 944 * 945 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 946 * translation is disabled, cache maintenance operations depend on the 947 * VMID. 948 * 949 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 950 * disabled. 951 */ 952 write_vttbr_el2(VTTBR_RESET_VAL & 953 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 954 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 955 956 /* 957 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 958 * Some fields are architecturally UNKNOWN on reset. 959 * 960 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 961 * register accesses to the Debug ROM registers are not trapped to EL2. 962 * 963 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 964 * accesses to the powerdown debug registers are not trapped to EL2. 965 * 966 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 967 * debug registers do not trap to EL2. 968 * 969 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 970 * EL2. 971 */ 972 mdcr_el2 = MDCR_EL2_RESET_VAL & 973 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 974 MDCR_EL2_TDE_BIT); 975 976 write_mdcr_el2(mdcr_el2); 977 978 /* 979 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 980 * 981 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 982 * EL1 accesses to System registers do not trap to EL2. 983 */ 984 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 985 986 /* 987 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 988 * reset. 989 * 990 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 991 * and prevent timer interrupts. 992 */ 993 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 994 995 manage_extensions_nonsecure_el2_unused(); 996 #endif /* INIT_UNUSED_NS_EL2 */ 997 } 998 999 /******************************************************************************* 1000 * Prepare the CPU system registers for first entry into realm, secure, or 1001 * normal world. 1002 * 1003 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1004 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1005 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1006 * For all entries, the EL1 registers are initialized from the cpu_context 1007 ******************************************************************************/ 1008 void cm_prepare_el3_exit(uint32_t security_state) 1009 { 1010 u_register_t sctlr_el2, scr_el3; 1011 cpu_context_t *ctx = cm_get_context(security_state); 1012 1013 assert(ctx != NULL); 1014 1015 if (security_state == NON_SECURE) { 1016 uint64_t el2_implemented = el_implemented(2); 1017 1018 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1019 CTX_SCR_EL3); 1020 1021 if (el2_implemented != EL_IMPL_NONE) { 1022 1023 /* 1024 * If context is not being used for EL2, initialize 1025 * HCRX_EL2 with its init value here. 1026 */ 1027 if (is_feat_hcx_supported()) { 1028 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1029 } 1030 1031 /* 1032 * Initialize Fine-grained trap registers introduced 1033 * by FEAT_FGT so all traps are initially disabled when 1034 * switching to EL2 or a lower EL, preventing undesired 1035 * behavior. 1036 */ 1037 if (is_feat_fgt_supported()) { 1038 /* 1039 * Initialize HFG*_EL2 registers with a default 1040 * value so legacy systems unaware of FEAT_FGT 1041 * do not get trapped due to their lack of 1042 * initialization for this feature. 1043 */ 1044 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1045 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1046 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1047 } 1048 1049 /* Condition to ensure EL2 is being used. */ 1050 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1051 /* Initialize SCTLR_EL2 register with reset value. */ 1052 sctlr_el2 = SCTLR_EL2_RES1; 1053 #if ERRATA_A75_764081 1054 /* 1055 * If workaround of errata 764081 for Cortex-A75 1056 * is used then set SCTLR_EL2.IESB to enable 1057 * Implicit Error Synchronization Barrier. 1058 */ 1059 sctlr_el2 |= SCTLR_IESB_BIT; 1060 #endif 1061 write_sctlr_el2(sctlr_el2); 1062 } else { 1063 /* 1064 * (scr_el3 & SCR_HCE_BIT==0) 1065 * EL2 implemented but unused. 1066 */ 1067 init_nonsecure_el2_unused(ctx); 1068 } 1069 } 1070 } 1071 cm_el1_sysregs_context_restore(security_state); 1072 cm_set_next_eret_context(security_state); 1073 } 1074 1075 #if CTX_INCLUDE_EL2_REGS 1076 1077 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1078 { 1079 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1080 if (is_feat_amu_supported()) { 1081 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1082 } 1083 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1084 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1085 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1086 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1087 } 1088 1089 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1090 { 1091 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1092 if (is_feat_amu_supported()) { 1093 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1094 } 1095 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1096 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1097 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1098 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1099 } 1100 1101 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1102 { 1103 u_register_t mpam_idr = read_mpamidr_el1(); 1104 1105 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1106 1107 /* 1108 * The context registers that we intend to save would be part of the 1109 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1110 */ 1111 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1112 return; 1113 } 1114 1115 /* 1116 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1117 * MPAMIDR_HAS_HCR_BIT == 1. 1118 */ 1119 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1120 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1121 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1122 1123 /* 1124 * The number of MPAMVPM registers is implementation defined, their 1125 * number is stored in the MPAMIDR_EL1 register. 1126 */ 1127 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1128 case 7: 1129 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1130 __fallthrough; 1131 case 6: 1132 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1133 __fallthrough; 1134 case 5: 1135 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1136 __fallthrough; 1137 case 4: 1138 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1139 __fallthrough; 1140 case 3: 1141 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1142 __fallthrough; 1143 case 2: 1144 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1145 __fallthrough; 1146 case 1: 1147 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1148 break; 1149 } 1150 } 1151 1152 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1153 { 1154 u_register_t mpam_idr = read_mpamidr_el1(); 1155 1156 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1157 1158 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1159 return; 1160 } 1161 1162 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1163 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1164 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1165 1166 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1167 case 7: 1168 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1169 __fallthrough; 1170 case 6: 1171 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1172 __fallthrough; 1173 case 5: 1174 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1175 __fallthrough; 1176 case 4: 1177 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1178 __fallthrough; 1179 case 3: 1180 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1181 __fallthrough; 1182 case 2: 1183 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1184 __fallthrough; 1185 case 1: 1186 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1187 break; 1188 } 1189 } 1190 1191 /* --------------------------------------------------------------------------- 1192 * The following registers are not added: 1193 * ICH_AP0R<n>_EL2 1194 * ICH_AP1R<n>_EL2 1195 * ICH_LR<n>_EL2 1196 * 1197 * NOTE: For a system with S-EL2 present but not enabled, accessing 1198 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1199 * SCR_EL3.NS = 1 before accessing this register. 1200 * --------------------------------------------------------------------------- 1201 */ 1202 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1203 { 1204 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1205 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1206 #else 1207 u_register_t scr_el3 = read_scr_el3(); 1208 write_scr_el3(scr_el3 | SCR_NS_BIT); 1209 isb(); 1210 1211 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1212 1213 write_scr_el3(scr_el3); 1214 isb(); 1215 #endif 1216 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1217 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1218 } 1219 1220 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1221 { 1222 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1223 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1224 #else 1225 u_register_t scr_el3 = read_scr_el3(); 1226 write_scr_el3(scr_el3 | SCR_NS_BIT); 1227 isb(); 1228 1229 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1230 1231 write_scr_el3(scr_el3); 1232 isb(); 1233 #endif 1234 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1235 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1236 } 1237 1238 /* ----------------------------------------------------- 1239 * The following registers are not added: 1240 * AMEVCNTVOFF0<n>_EL2 1241 * AMEVCNTVOFF1<n>_EL2 1242 * ----------------------------------------------------- 1243 */ 1244 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1245 { 1246 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1247 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1248 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1249 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1250 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1251 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1252 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1253 if (CTX_INCLUDE_AARCH32_REGS) { 1254 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1255 } 1256 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1257 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1258 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1259 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1260 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1261 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1262 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1263 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1264 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1265 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1266 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1267 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1268 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1269 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1270 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2()); 1271 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1272 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1273 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1274 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1275 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2()); 1276 } 1277 1278 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1279 { 1280 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1281 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1282 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1283 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1284 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1285 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1286 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1287 if (CTX_INCLUDE_AARCH32_REGS) { 1288 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1289 } 1290 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1291 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1292 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1293 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1294 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1295 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1296 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1297 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1298 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1299 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1300 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1301 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1302 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1303 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1304 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1305 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1306 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1307 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1308 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1309 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1310 } 1311 1312 /******************************************************************************* 1313 * Save EL2 sysreg context 1314 ******************************************************************************/ 1315 void cm_el2_sysregs_context_save(uint32_t security_state) 1316 { 1317 cpu_context_t *ctx; 1318 el2_sysregs_t *el2_sysregs_ctx; 1319 1320 ctx = cm_get_context(security_state); 1321 assert(ctx != NULL); 1322 1323 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1324 1325 el2_sysregs_context_save_common(el2_sysregs_ctx); 1326 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1327 1328 if (is_feat_mte2_supported()) { 1329 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1330 } 1331 1332 if (is_feat_mpam_supported()) { 1333 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1334 } 1335 1336 if (is_feat_fgt_supported()) { 1337 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1338 } 1339 1340 if (is_feat_ecv_v2_supported()) { 1341 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1342 } 1343 1344 if (is_feat_vhe_supported()) { 1345 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1346 read_contextidr_el2()); 1347 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1348 } 1349 1350 if (is_feat_ras_supported()) { 1351 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1352 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1353 } 1354 1355 if (is_feat_nv2_supported()) { 1356 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1357 } 1358 1359 if (is_feat_trf_supported()) { 1360 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1361 } 1362 1363 if (is_feat_csv2_2_supported()) { 1364 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1365 read_scxtnum_el2()); 1366 } 1367 1368 if (is_feat_hcx_supported()) { 1369 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1370 } 1371 1372 if (is_feat_tcr2_supported()) { 1373 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1374 } 1375 1376 if (is_feat_sxpie_supported()) { 1377 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1378 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1379 } 1380 1381 if (is_feat_sxpoe_supported()) { 1382 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1383 } 1384 1385 if (is_feat_s2pie_supported()) { 1386 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1387 } 1388 1389 if (is_feat_gcs_supported()) { 1390 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1391 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1392 } 1393 } 1394 1395 /******************************************************************************* 1396 * Restore EL2 sysreg context 1397 ******************************************************************************/ 1398 void cm_el2_sysregs_context_restore(uint32_t security_state) 1399 { 1400 cpu_context_t *ctx; 1401 el2_sysregs_t *el2_sysregs_ctx; 1402 1403 ctx = cm_get_context(security_state); 1404 assert(ctx != NULL); 1405 1406 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1407 1408 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1409 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1410 1411 if (is_feat_mte2_supported()) { 1412 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1413 } 1414 1415 if (is_feat_mpam_supported()) { 1416 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1417 } 1418 1419 if (is_feat_fgt_supported()) { 1420 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1421 } 1422 1423 if (is_feat_ecv_v2_supported()) { 1424 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1425 } 1426 1427 if (is_feat_vhe_supported()) { 1428 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1429 contextidr_el2)); 1430 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1431 } 1432 1433 if (is_feat_ras_supported()) { 1434 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1435 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1436 } 1437 1438 if (is_feat_nv2_supported()) { 1439 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1440 } 1441 1442 if (is_feat_trf_supported()) { 1443 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1444 } 1445 1446 if (is_feat_csv2_2_supported()) { 1447 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1448 scxtnum_el2)); 1449 } 1450 1451 if (is_feat_hcx_supported()) { 1452 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1453 } 1454 1455 if (is_feat_tcr2_supported()) { 1456 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1457 } 1458 1459 if (is_feat_sxpie_supported()) { 1460 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1461 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1462 } 1463 1464 if (is_feat_sxpoe_supported()) { 1465 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1466 } 1467 1468 if (is_feat_s2pie_supported()) { 1469 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1470 } 1471 1472 if (is_feat_gcs_supported()) { 1473 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1474 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1475 } 1476 } 1477 #endif /* CTX_INCLUDE_EL2_REGS */ 1478 1479 /******************************************************************************* 1480 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1481 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1482 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1483 * cm_prepare_el3_exit function. 1484 ******************************************************************************/ 1485 void cm_prepare_el3_exit_ns(void) 1486 { 1487 #if CTX_INCLUDE_EL2_REGS 1488 #if ENABLE_ASSERTIONS 1489 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1490 assert(ctx != NULL); 1491 1492 /* Assert that EL2 is used. */ 1493 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1494 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1495 (el_implemented(2U) != EL_IMPL_NONE)); 1496 #endif /* ENABLE_ASSERTIONS */ 1497 1498 /* Restore EL2 and EL1 sysreg contexts */ 1499 cm_el2_sysregs_context_restore(NON_SECURE); 1500 cm_el1_sysregs_context_restore(NON_SECURE); 1501 cm_set_next_eret_context(NON_SECURE); 1502 #else 1503 cm_prepare_el3_exit(NON_SECURE); 1504 #endif /* CTX_INCLUDE_EL2_REGS */ 1505 } 1506 1507 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1508 { 1509 write_ctx_reg(ctx, CTX_SPSR_EL1, read_spsr_el1()); 1510 write_ctx_reg(ctx, CTX_ELR_EL1, read_elr_el1()); 1511 1512 #if !ERRATA_SPECULATIVE_AT 1513 write_ctx_reg(ctx, CTX_SCTLR_EL1, read_sctlr_el1()); 1514 write_ctx_reg(ctx, CTX_TCR_EL1, read_tcr_el1()); 1515 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1516 1517 write_ctx_reg(ctx, CTX_CPACR_EL1, read_cpacr_el1()); 1518 write_ctx_reg(ctx, CTX_CSSELR_EL1, read_csselr_el1()); 1519 write_ctx_reg(ctx, CTX_SP_EL1, read_sp_el1()); 1520 write_ctx_reg(ctx, CTX_ESR_EL1, read_esr_el1()); 1521 write_ctx_reg(ctx, CTX_TTBR0_EL1, read_ttbr0_el1()); 1522 write_ctx_reg(ctx, CTX_TTBR1_EL1, read_ttbr1_el1()); 1523 write_ctx_reg(ctx, CTX_MAIR_EL1, read_mair_el1()); 1524 write_ctx_reg(ctx, CTX_AMAIR_EL1, read_amair_el1()); 1525 write_ctx_reg(ctx, CTX_ACTLR_EL1, read_actlr_el1()); 1526 write_ctx_reg(ctx, CTX_TPIDR_EL1, read_tpidr_el1()); 1527 write_ctx_reg(ctx, CTX_TPIDR_EL0, read_tpidr_el0()); 1528 write_ctx_reg(ctx, CTX_TPIDRRO_EL0, read_tpidrro_el0()); 1529 write_ctx_reg(ctx, CTX_PAR_EL1, read_par_el1()); 1530 write_ctx_reg(ctx, CTX_FAR_EL1, read_far_el1()); 1531 write_ctx_reg(ctx, CTX_AFSR0_EL1, read_afsr0_el1()); 1532 write_ctx_reg(ctx, CTX_AFSR1_EL1, read_afsr1_el1()); 1533 write_ctx_reg(ctx, CTX_CONTEXTIDR_EL1, read_contextidr_el1()); 1534 write_ctx_reg(ctx, CTX_VBAR_EL1, read_vbar_el1()); 1535 write_ctx_reg(ctx, CTX_MDCCINT_EL1, read_mdccint_el1()); 1536 write_ctx_reg(ctx, CTX_MDSCR_EL1, read_mdscr_el1()); 1537 1538 #if CTX_INCLUDE_AARCH32_REGS 1539 write_ctx_reg(ctx, CTX_SPSR_ABT, read_spsr_abt()); 1540 write_ctx_reg(ctx, CTX_SPSR_UND, read_spsr_und()); 1541 write_ctx_reg(ctx, CTX_SPSR_IRQ, read_spsr_irq()); 1542 write_ctx_reg(ctx, CTX_SPSR_FIQ, read_spsr_fiq()); 1543 write_ctx_reg(ctx, CTX_DACR32_EL2, read_dacr32_el2()); 1544 write_ctx_reg(ctx, CTX_IFSR32_EL2, read_ifsr32_el2()); 1545 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1546 1547 #if NS_TIMER_SWITCH 1548 write_ctx_reg(ctx, CTX_CNTP_CTL_EL0, read_cntp_ctl_el0()); 1549 write_ctx_reg(ctx, CTX_CNTP_CVAL_EL0, read_cntp_cval_el0()); 1550 write_ctx_reg(ctx, CTX_CNTV_CTL_EL0, read_cntv_ctl_el0()); 1551 write_ctx_reg(ctx, CTX_CNTV_CVAL_EL0, read_cntv_cval_el0()); 1552 write_ctx_reg(ctx, CTX_CNTKCTL_EL1, read_cntkctl_el1()); 1553 #endif /* NS_TIMER_SWITCH */ 1554 1555 #if ENABLE_FEAT_MTE2 1556 write_ctx_reg(ctx, CTX_TFSRE0_EL1, read_tfsre0_el1()); 1557 write_ctx_reg(ctx, CTX_TFSR_EL1, read_tfsr_el1()); 1558 write_ctx_reg(ctx, CTX_RGSR_EL1, read_rgsr_el1()); 1559 write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1()); 1560 #endif /* ENABLE_FEAT_MTE2 */ 1561 1562 #if ENABLE_FEAT_RAS 1563 if (is_feat_ras_supported()) { 1564 write_ctx_reg(ctx, CTX_DISR_EL1, read_disr_el1()); 1565 } 1566 #endif 1567 1568 #if ENABLE_FEAT_S1PIE 1569 if (is_feat_s1pie_supported()) { 1570 write_ctx_reg(ctx, CTX_PIRE0_EL1, read_pire0_el1()); 1571 write_ctx_reg(ctx, CTX_PIR_EL1, read_pir_el1()); 1572 } 1573 #endif 1574 1575 #if ENABLE_FEAT_S1POE 1576 if (is_feat_s1poe_supported()) { 1577 write_ctx_reg(ctx, CTX_POR_EL1, read_por_el1()); 1578 } 1579 #endif 1580 1581 #if ENABLE_FEAT_S2POE 1582 if (is_feat_s2poe_supported()) { 1583 write_ctx_reg(ctx, CTX_S2POR_EL1, read_s2por_el1()); 1584 } 1585 #endif 1586 1587 #if ENABLE_FEAT_TCR2 1588 if (is_feat_tcr2_supported()) { 1589 write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1()); 1590 } 1591 #endif 1592 1593 #if ENABLE_TRF_FOR_NS 1594 if (is_feat_trf_supported()) { 1595 write_ctx_reg(ctx, CTX_TRFCR_EL1, read_trfcr_el1()); 1596 } 1597 #endif 1598 1599 #if ENABLE_FEAT_CSV2_2 1600 if (is_feat_csv2_2_supported()) { 1601 write_ctx_reg(ctx, CTX_SCXTNUM_EL0, read_scxtnum_el0()); 1602 write_ctx_reg(ctx, CTX_SCXTNUM_EL1, read_scxtnum_el1()); 1603 } 1604 #endif 1605 1606 #if ENABLE_FEAT_GCS 1607 if (is_feat_gcs_supported()) { 1608 write_ctx_reg(ctx, CTX_GCSCR_EL1, read_gcscr_el1()); 1609 write_ctx_reg(ctx, CTX_GCSCRE0_EL1, read_gcscre0_el1()); 1610 write_ctx_reg(ctx, CTX_GCSPR_EL1, read_gcspr_el1()); 1611 write_ctx_reg(ctx, CTX_GCSPR_EL0, read_gcspr_el0()); 1612 } 1613 #endif 1614 } 1615 1616 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1617 { 1618 write_spsr_el1(read_ctx_reg(ctx, CTX_SPSR_EL1)); 1619 write_elr_el1(read_ctx_reg(ctx, CTX_ELR_EL1)); 1620 1621 #if !ERRATA_SPECULATIVE_AT 1622 write_sctlr_el1(read_ctx_reg(ctx, CTX_SCTLR_EL1)); 1623 write_tcr_el1(read_ctx_reg(ctx, CTX_TCR_EL1)); 1624 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1625 1626 write_cpacr_el1(read_ctx_reg(ctx, CTX_CPACR_EL1)); 1627 write_csselr_el1(read_ctx_reg(ctx, CTX_CSSELR_EL1)); 1628 write_sp_el1(read_ctx_reg(ctx, CTX_SP_EL1)); 1629 write_esr_el1(read_ctx_reg(ctx, CTX_ESR_EL1)); 1630 write_ttbr0_el1(read_ctx_reg(ctx, CTX_TTBR0_EL1)); 1631 write_ttbr1_el1(read_ctx_reg(ctx, CTX_TTBR1_EL1)); 1632 write_mair_el1(read_ctx_reg(ctx, CTX_MAIR_EL1)); 1633 write_amair_el1(read_ctx_reg(ctx, CTX_AMAIR_EL1)); 1634 write_actlr_el1(read_ctx_reg(ctx, CTX_ACTLR_EL1)); 1635 write_tpidr_el1(read_ctx_reg(ctx, CTX_TPIDR_EL1)); 1636 write_tpidr_el0(read_ctx_reg(ctx, CTX_TPIDR_EL0)); 1637 write_tpidrro_el0(read_ctx_reg(ctx, CTX_TPIDRRO_EL0)); 1638 write_par_el1(read_ctx_reg(ctx, CTX_PAR_EL1)); 1639 write_far_el1(read_ctx_reg(ctx, CTX_FAR_EL1)); 1640 write_afsr0_el1(read_ctx_reg(ctx, CTX_AFSR0_EL1)); 1641 write_afsr1_el1(read_ctx_reg(ctx, CTX_AFSR1_EL1)); 1642 write_contextidr_el1(read_ctx_reg(ctx, CTX_CONTEXTIDR_EL1)); 1643 write_vbar_el1(read_ctx_reg(ctx, CTX_VBAR_EL1)); 1644 write_mdccint_el1(read_ctx_reg(ctx, CTX_MDCCINT_EL1)); 1645 write_mdscr_el1(read_ctx_reg(ctx, CTX_MDSCR_EL1)); 1646 1647 #if CTX_INCLUDE_AARCH32_REGS 1648 write_spsr_abt(read_ctx_reg(ctx, CTX_SPSR_ABT)); 1649 write_spsr_und(read_ctx_reg(ctx, CTX_SPSR_UND)); 1650 write_spsr_irq(read_ctx_reg(ctx, CTX_SPSR_IRQ)); 1651 write_spsr_fiq(read_ctx_reg(ctx, CTX_SPSR_FIQ)); 1652 write_dacr32_el2(read_ctx_reg(ctx, CTX_DACR32_EL2)); 1653 write_ifsr32_el2(read_ctx_reg(ctx, CTX_IFSR32_EL2)); 1654 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1655 1656 #if NS_TIMER_SWITCH 1657 write_cntp_ctl_el0(read_ctx_reg(ctx, CTX_CNTP_CTL_EL0)); 1658 write_cntp_cval_el0(read_ctx_reg(ctx, CTX_CNTP_CVAL_EL0)); 1659 write_cntv_ctl_el0(read_ctx_reg(ctx, CTX_CNTV_CTL_EL0)); 1660 write_cntv_cval_el0(read_ctx_reg(ctx, CTX_CNTV_CVAL_EL0)); 1661 write_cntkctl_el1(read_ctx_reg(ctx, CTX_CNTKCTL_EL1)); 1662 #endif /* NS_TIMER_SWITCH */ 1663 1664 #if ENABLE_FEAT_MTE2 1665 write_tfsre0_el1(read_ctx_reg(ctx, CTX_TFSRE0_EL1)); 1666 write_tfsr_el1(read_ctx_reg(ctx, CTX_TFSR_EL1)); 1667 write_rgsr_el1(read_ctx_reg(ctx, CTX_RGSR_EL1)); 1668 write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1)); 1669 #endif /* ENABLE_FEAT_MTE2 */ 1670 1671 #if ENABLE_FEAT_RAS 1672 if (is_feat_ras_supported()) { 1673 write_disr_el1(read_ctx_reg(ctx, CTX_DISR_EL1)); 1674 } 1675 #endif 1676 1677 #if ENABLE_FEAT_S1PIE 1678 if (is_feat_s1pie_supported()) { 1679 write_pire0_el1(read_ctx_reg(ctx, CTX_PIRE0_EL1)); 1680 write_pir_el1(read_ctx_reg(ctx, CTX_PIR_EL1)); 1681 } 1682 #endif 1683 1684 #if ENABLE_FEAT_S1POE 1685 if (is_feat_s1poe_supported()) { 1686 write_por_el1(read_ctx_reg(ctx, CTX_POR_EL1)); 1687 } 1688 #endif 1689 1690 #if ENABLE_FEAT_S2POE 1691 if (is_feat_s2poe_supported()) { 1692 write_s2por_el1(read_ctx_reg(ctx, CTX_S2POR_EL1)); 1693 } 1694 #endif 1695 1696 #if ENABLE_FEAT_TCR2 1697 if (is_feat_tcr2_supported()) { 1698 write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1)); 1699 } 1700 #endif 1701 1702 #if ENABLE_TRF_FOR_NS 1703 if (is_feat_trf_supported()) { 1704 write_trfcr_el1(read_ctx_reg(ctx, CTX_TRFCR_EL1)); 1705 } 1706 #endif 1707 1708 #if ENABLE_FEAT_CSV2_2 1709 if (is_feat_csv2_2_supported()) { 1710 write_scxtnum_el0(read_ctx_reg(ctx, CTX_SCXTNUM_EL0)); 1711 write_scxtnum_el1(read_ctx_reg(ctx, CTX_SCXTNUM_EL1)); 1712 } 1713 #endif 1714 1715 #if ENABLE_FEAT_GCS 1716 if (is_feat_gcs_supported()) { 1717 write_gcscr_el1(read_ctx_reg(ctx, CTX_GCSCR_EL1)); 1718 write_gcscre0_el1(read_ctx_reg(ctx, CTX_GCSCRE0_EL1)); 1719 write_gcspr_el1(read_ctx_reg(ctx, CTX_GCSPR_EL1)); 1720 write_gcspr_el0(read_ctx_reg(ctx, CTX_GCSPR_EL0)); 1721 } 1722 #endif 1723 } 1724 1725 /******************************************************************************* 1726 * The next four functions are used by runtime services to save and restore 1727 * EL1 context on the 'cpu_context' structure for the specified security 1728 * state. 1729 ******************************************************************************/ 1730 void cm_el1_sysregs_context_save(uint32_t security_state) 1731 { 1732 cpu_context_t *ctx; 1733 1734 ctx = cm_get_context(security_state); 1735 assert(ctx != NULL); 1736 1737 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1738 1739 #if IMAGE_BL31 1740 if (security_state == SECURE) 1741 PUBLISH_EVENT(cm_exited_secure_world); 1742 else 1743 PUBLISH_EVENT(cm_exited_normal_world); 1744 #endif 1745 } 1746 1747 void cm_el1_sysregs_context_restore(uint32_t security_state) 1748 { 1749 cpu_context_t *ctx; 1750 1751 ctx = cm_get_context(security_state); 1752 assert(ctx != NULL); 1753 1754 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1755 1756 #if IMAGE_BL31 1757 if (security_state == SECURE) 1758 PUBLISH_EVENT(cm_entering_secure_world); 1759 else 1760 PUBLISH_EVENT(cm_entering_normal_world); 1761 #endif 1762 } 1763 1764 /******************************************************************************* 1765 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1766 * given security state with the given entrypoint 1767 ******************************************************************************/ 1768 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1769 { 1770 cpu_context_t *ctx; 1771 el3_state_t *state; 1772 1773 ctx = cm_get_context(security_state); 1774 assert(ctx != NULL); 1775 1776 /* Populate EL3 state so that ERET jumps to the correct entry */ 1777 state = get_el3state_ctx(ctx); 1778 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1779 } 1780 1781 /******************************************************************************* 1782 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1783 * pertaining to the given security state 1784 ******************************************************************************/ 1785 void cm_set_elr_spsr_el3(uint32_t security_state, 1786 uintptr_t entrypoint, uint32_t spsr) 1787 { 1788 cpu_context_t *ctx; 1789 el3_state_t *state; 1790 1791 ctx = cm_get_context(security_state); 1792 assert(ctx != NULL); 1793 1794 /* Populate EL3 state so that ERET jumps to the correct entry */ 1795 state = get_el3state_ctx(ctx); 1796 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1797 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1798 } 1799 1800 /******************************************************************************* 1801 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1802 * pertaining to the given security state using the value and bit position 1803 * specified in the parameters. It preserves all other bits. 1804 ******************************************************************************/ 1805 void cm_write_scr_el3_bit(uint32_t security_state, 1806 uint32_t bit_pos, 1807 uint32_t value) 1808 { 1809 cpu_context_t *ctx; 1810 el3_state_t *state; 1811 u_register_t scr_el3; 1812 1813 ctx = cm_get_context(security_state); 1814 assert(ctx != NULL); 1815 1816 /* Ensure that the bit position is a valid one */ 1817 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1818 1819 /* Ensure that the 'value' is only a bit wide */ 1820 assert(value <= 1U); 1821 1822 /* 1823 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1824 * and set it to its new value. 1825 */ 1826 state = get_el3state_ctx(ctx); 1827 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1828 scr_el3 &= ~(1UL << bit_pos); 1829 scr_el3 |= (u_register_t)value << bit_pos; 1830 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1831 } 1832 1833 /******************************************************************************* 1834 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1835 * given security state. 1836 ******************************************************************************/ 1837 u_register_t cm_get_scr_el3(uint32_t security_state) 1838 { 1839 cpu_context_t *ctx; 1840 el3_state_t *state; 1841 1842 ctx = cm_get_context(security_state); 1843 assert(ctx != NULL); 1844 1845 /* Populate EL3 state so that ERET jumps to the correct entry */ 1846 state = get_el3state_ctx(ctx); 1847 return read_ctx_reg(state, CTX_SCR_EL3); 1848 } 1849 1850 /******************************************************************************* 1851 * This function is used to program the context that's used for exception 1852 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1853 * the required security state 1854 ******************************************************************************/ 1855 void cm_set_next_eret_context(uint32_t security_state) 1856 { 1857 cpu_context_t *ctx; 1858 1859 ctx = cm_get_context(security_state); 1860 assert(ctx != NULL); 1861 1862 cm_set_next_context(ctx); 1863 } 1864