1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <drivers/arm/gicv3.h> 20 #include <lib/el3_runtime/context_mgmt.h> 21 #include <lib/el3_runtime/pubsub_events.h> 22 #include <lib/extensions/amu.h> 23 #include <lib/extensions/brbe.h> 24 #include <lib/extensions/mpam.h> 25 #include <lib/extensions/sme.h> 26 #include <lib/extensions/spe.h> 27 #include <lib/extensions/sve.h> 28 #include <lib/extensions/sys_reg_trace.h> 29 #include <lib/extensions/trbe.h> 30 #include <lib/extensions/trf.h> 31 #include <lib/utils.h> 32 33 #if ENABLE_FEAT_TWED 34 /* Make sure delay value fits within the range(0-15) */ 35 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 36 #endif /* ENABLE_FEAT_TWED */ 37 38 static void manage_extensions_secure(cpu_context_t *ctx); 39 40 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 41 { 42 u_register_t sctlr_elx, actlr_elx; 43 44 /* 45 * Initialise SCTLR_EL1 to the reset value corresponding to the target 46 * execution state setting all fields rather than relying on the hw. 47 * Some fields have architecturally UNKNOWN reset values and these are 48 * set to zero. 49 * 50 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 51 * 52 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 53 * required by PSCI specification) 54 */ 55 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 56 if (GET_RW(ep->spsr) == MODE_RW_64) { 57 sctlr_elx |= SCTLR_EL1_RES1; 58 } else { 59 /* 60 * If the target execution state is AArch32 then the following 61 * fields need to be set. 62 * 63 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 64 * instructions are not trapped to EL1. 65 * 66 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 67 * instructions are not trapped to EL1. 68 * 69 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 70 * CP15DMB, CP15DSB, and CP15ISB instructions. 71 */ 72 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 73 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 74 } 75 76 #if ERRATA_A75_764081 77 /* 78 * If workaround of errata 764081 for Cortex-A75 is used then set 79 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 80 */ 81 sctlr_elx |= SCTLR_IESB_BIT; 82 #endif 83 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 84 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 85 86 /* 87 * Base the context ACTLR_EL1 on the current value, as it is 88 * implementation defined. The context restore process will write 89 * the value from the context to the actual register and can cause 90 * problems for processor cores that don't expect certain bits to 91 * be zero. 92 */ 93 actlr_elx = read_actlr_el1(); 94 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 95 } 96 97 /****************************************************************************** 98 * This function performs initializations that are specific to SECURE state 99 * and updates the cpu context specified by 'ctx'. 100 *****************************************************************************/ 101 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 102 { 103 u_register_t scr_el3; 104 el3_state_t *state; 105 106 state = get_el3state_ctx(ctx); 107 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 108 109 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 110 /* 111 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 112 * indicated by the interrupt routing model for BL31. 113 */ 114 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 115 #endif 116 117 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 118 /* Get Memory Tagging Extension support level */ 119 unsigned int mte = get_armv8_5_mte_support(); 120 #endif 121 /* 122 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 123 * is set, or when MTE is only implemented at EL0. 124 */ 125 #if CTX_INCLUDE_MTE_REGS 126 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 127 scr_el3 |= SCR_ATA_BIT; 128 #else 129 if (mte == MTE_IMPLEMENTED_EL0) { 130 scr_el3 |= SCR_ATA_BIT; 131 } 132 #endif /* CTX_INCLUDE_MTE_REGS */ 133 134 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 135 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) { 136 if (GET_RW(ep->spsr) != MODE_RW_64) { 137 ERROR("S-EL2 can not be used in AArch32\n."); 138 panic(); 139 } 140 141 scr_el3 |= SCR_EEL2_BIT; 142 } 143 144 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 145 146 /* 147 * Initialize EL1 context registers unless SPMC is running 148 * at S-EL2. 149 */ 150 #if !SPMD_SPM_AT_SEL2 151 setup_el1_context(ctx, ep); 152 #endif 153 154 manage_extensions_secure(ctx); 155 } 156 157 #if ENABLE_RME 158 /****************************************************************************** 159 * This function performs initializations that are specific to REALM state 160 * and updates the cpu context specified by 'ctx'. 161 *****************************************************************************/ 162 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 163 { 164 u_register_t scr_el3; 165 el3_state_t *state; 166 167 state = get_el3state_ctx(ctx); 168 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 169 170 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT; 171 172 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 173 } 174 #endif /* ENABLE_RME */ 175 176 /****************************************************************************** 177 * This function performs initializations that are specific to NON-SECURE state 178 * and updates the cpu context specified by 'ctx'. 179 *****************************************************************************/ 180 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 181 { 182 u_register_t scr_el3; 183 el3_state_t *state; 184 185 state = get_el3state_ctx(ctx); 186 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 187 188 /* SCR_NS: Set the NS bit */ 189 scr_el3 |= SCR_NS_BIT; 190 191 #if !CTX_INCLUDE_PAUTH_REGS 192 /* 193 * If the pointer authentication registers aren't saved during world 194 * switches the value of the registers can be leaked from the Secure to 195 * the Non-secure world. To prevent this, rather than enabling pointer 196 * authentication everywhere, we only enable it in the Non-secure world. 197 * 198 * If the Secure world wants to use pointer authentication, 199 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 200 */ 201 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 202 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 203 204 /* Allow access to Allocation Tags when MTE is implemented. */ 205 scr_el3 |= SCR_ATA_BIT; 206 207 #ifdef IMAGE_BL31 208 /* 209 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 210 * indicated by the interrupt routing model for BL31. 211 */ 212 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 213 #endif 214 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 215 216 /* Initialize EL1 context registers */ 217 setup_el1_context(ctx, ep); 218 219 /* Initialize EL2 context registers */ 220 #if CTX_INCLUDE_EL2_REGS 221 222 /* 223 * Initialize SCTLR_EL2 context register using Endianness value 224 * taken from the entrypoint attribute. 225 */ 226 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 227 sctlr_el2 |= SCTLR_EL2_RES1; 228 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 229 sctlr_el2); 230 231 /* 232 * The GICv3 driver initializes the ICC_SRE_EL2 register during 233 * platform setup. Use the same setting for the corresponding 234 * context register to make sure the correct bits are set when 235 * restoring NS context. 236 */ 237 u_register_t icc_sre_el2 = read_icc_sre_el2(); 238 icc_sre_el2 |= (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT); 239 icc_sre_el2 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 240 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 241 icc_sre_el2); 242 #endif /* CTX_INCLUDE_EL2_REGS */ 243 } 244 245 /******************************************************************************* 246 * The following function performs initialization of the cpu_context 'ctx' 247 * for first use that is common to all security states, and sets the 248 * initial entrypoint state as specified by the entry_point_info structure. 249 * 250 * The EE and ST attributes are used to configure the endianness and secure 251 * timer availability for the new execution context. 252 ******************************************************************************/ 253 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 254 { 255 u_register_t scr_el3; 256 el3_state_t *state; 257 gp_regs_t *gp_regs; 258 259 /* Clear any residual register values from the context */ 260 zeromem(ctx, sizeof(*ctx)); 261 262 /* 263 * SCR_EL3 was initialised during reset sequence in macro 264 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 265 * affect the next EL. 266 * 267 * The following fields are initially set to zero and then updated to 268 * the required value depending on the state of the SPSR_EL3 and the 269 * Security state and entrypoint attributes of the next EL. 270 */ 271 scr_el3 = read_scr(); 272 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 273 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 274 275 /* 276 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 277 * Exception level as specified by SPSR. 278 */ 279 if (GET_RW(ep->spsr) == MODE_RW_64) { 280 scr_el3 |= SCR_RW_BIT; 281 } 282 283 /* 284 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 285 * Secure timer registers to EL3, from AArch64 state only, if specified 286 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 287 * bit always behaves as 1 (i.e. secure physical timer register access 288 * is not trapped) 289 */ 290 if (EP_GET_ST(ep->h.attr) != 0U) { 291 scr_el3 |= SCR_ST_BIT; 292 } 293 294 /* 295 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 296 * SCR_EL3.HXEn. 297 */ 298 #if ENABLE_FEAT_HCX 299 scr_el3 |= SCR_HXEn_BIT; 300 #endif 301 302 /* 303 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 304 * registers are trapped to EL3. 305 */ 306 #if ENABLE_FEAT_RNG_TRAP 307 scr_el3 |= SCR_TRNDR_BIT; 308 #endif 309 310 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 311 /* 312 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 313 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 314 */ 315 scr_el3 |= SCR_TERR_BIT; 316 #endif 317 318 #if !HANDLE_EA_EL3_FIRST 319 /* 320 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 321 * to EL3 when executing at a lower EL. When executing at EL3, External 322 * Aborts are taken to EL3. 323 */ 324 scr_el3 &= ~SCR_EA_BIT; 325 #endif 326 327 #if FAULT_INJECTION_SUPPORT 328 /* Enable fault injection from lower ELs */ 329 scr_el3 |= SCR_FIEN_BIT; 330 #endif 331 332 /* 333 * CPTR_EL3 was initialized out of reset, copy that value to the 334 * context register. 335 */ 336 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 337 338 /* 339 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 340 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 341 * next mode is Hyp. 342 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 343 * same conditions as HVC instructions and when the processor supports 344 * ARMv8.6-FGT. 345 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 346 * CNTPOFF_EL2 register under the same conditions as HVC instructions 347 * and when the processor supports ECV. 348 */ 349 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 350 || ((GET_RW(ep->spsr) != MODE_RW_64) 351 && (GET_M32(ep->spsr) == MODE32_hyp))) { 352 scr_el3 |= SCR_HCE_BIT; 353 354 if (is_armv8_6_fgt_present()) { 355 scr_el3 |= SCR_FGTEN_BIT; 356 } 357 358 if (get_armv8_6_ecv_support() 359 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 360 scr_el3 |= SCR_ECVEN_BIT; 361 } 362 } 363 364 #if ENABLE_FEAT_TWED 365 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 366 /* Set delay in SCR_EL3 */ 367 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 368 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 369 << SCR_TWEDEL_SHIFT); 370 371 /* Enable WFE delay */ 372 scr_el3 |= SCR_TWEDEn_BIT; 373 #endif /* ENABLE_FEAT_TWED */ 374 375 /* 376 * Populate EL3 state so that we've the right context 377 * before doing ERET 378 */ 379 state = get_el3state_ctx(ctx); 380 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 381 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 382 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 383 384 /* 385 * Store the X0-X7 value from the entrypoint into the context 386 * Use memcpy as we are in control of the layout of the structures 387 */ 388 gp_regs = get_gpregs_ctx(ctx); 389 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 390 } 391 392 /******************************************************************************* 393 * Context management library initialization routine. This library is used by 394 * runtime services to share pointers to 'cpu_context' structures for secure 395 * non-secure and realm states. Management of the structures and their associated 396 * memory is not done by the context management library e.g. the PSCI service 397 * manages the cpu context used for entry from and exit to the non-secure state. 398 * The Secure payload dispatcher service manages the context(s) corresponding to 399 * the secure state. It also uses this library to get access to the non-secure 400 * state cpu context pointers. 401 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 402 * which will be used for programming an entry into a lower EL. The same context 403 * will be used to save state upon exception entry from that EL. 404 ******************************************************************************/ 405 void __init cm_init(void) 406 { 407 /* 408 * The context management library has only global data to intialize, but 409 * that will be done when the BSS is zeroed out. 410 */ 411 } 412 413 /******************************************************************************* 414 * This is the high-level function used to initialize the cpu_context 'ctx' for 415 * first use. It performs initializations that are common to all security states 416 * and initializations specific to the security state specified in 'ep' 417 ******************************************************************************/ 418 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 419 { 420 unsigned int security_state; 421 422 assert(ctx != NULL); 423 424 /* 425 * Perform initializations that are common 426 * to all security states 427 */ 428 setup_context_common(ctx, ep); 429 430 security_state = GET_SECURITY_STATE(ep->h.attr); 431 432 /* Perform security state specific initializations */ 433 switch (security_state) { 434 case SECURE: 435 setup_secure_context(ctx, ep); 436 break; 437 #if ENABLE_RME 438 case REALM: 439 setup_realm_context(ctx, ep); 440 break; 441 #endif 442 case NON_SECURE: 443 setup_ns_context(ctx, ep); 444 break; 445 default: 446 ERROR("Invalid security state\n"); 447 panic(); 448 break; 449 } 450 } 451 452 /******************************************************************************* 453 * Enable architecture extensions on first entry to Non-secure world. 454 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 455 * it is zero. 456 ******************************************************************************/ 457 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 458 { 459 #if IMAGE_BL31 460 #if ENABLE_SPE_FOR_LOWER_ELS 461 spe_enable(el2_unused); 462 #endif 463 464 #if ENABLE_AMU 465 amu_enable(el2_unused, ctx); 466 #endif 467 468 #if ENABLE_SME_FOR_NS 469 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 470 sme_enable(ctx); 471 #elif ENABLE_SVE_FOR_NS 472 /* Enable SVE and FPU/SIMD for non-secure world. */ 473 sve_enable(ctx); 474 #endif 475 476 #if ENABLE_MPAM_FOR_LOWER_ELS 477 mpam_enable(el2_unused); 478 #endif 479 480 #if ENABLE_TRBE_FOR_NS 481 trbe_enable(); 482 #endif /* ENABLE_TRBE_FOR_NS */ 483 484 #if ENABLE_BRBE_FOR_NS 485 brbe_enable(); 486 #endif /* ENABLE_BRBE_FOR_NS */ 487 488 #if ENABLE_SYS_REG_TRACE_FOR_NS 489 sys_reg_trace_enable(ctx); 490 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 491 492 #if ENABLE_TRF_FOR_NS 493 trf_enable(); 494 #endif /* ENABLE_TRF_FOR_NS */ 495 #endif 496 } 497 498 /******************************************************************************* 499 * Enable architecture extensions on first entry to Secure world. 500 ******************************************************************************/ 501 static void manage_extensions_secure(cpu_context_t *ctx) 502 { 503 #if IMAGE_BL31 504 #if ENABLE_SME_FOR_NS 505 #if ENABLE_SME_FOR_SWD 506 /* 507 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must 508 * ensure SME, SVE, and FPU/SIMD context properly managed. 509 */ 510 sme_enable(ctx); 511 #else /* ENABLE_SME_FOR_SWD */ 512 /* 513 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can 514 * safely use the associated registers. 515 */ 516 sme_disable(ctx); 517 #endif /* ENABLE_SME_FOR_SWD */ 518 #elif ENABLE_SVE_FOR_NS 519 #if ENABLE_SVE_FOR_SWD 520 /* 521 * Enable SVE and FPU in secure context, secure manager must ensure that 522 * the SVE and FPU register contexts are properly managed. 523 */ 524 sve_enable(ctx); 525 #else /* ENABLE_SVE_FOR_SWD */ 526 /* 527 * Disable SVE and FPU in secure context so non-secure world can safely 528 * use them. 529 */ 530 sve_disable(ctx); 531 #endif /* ENABLE_SVE_FOR_SWD */ 532 #endif /* ENABLE_SVE_FOR_NS */ 533 #endif /* IMAGE_BL31 */ 534 } 535 536 /******************************************************************************* 537 * The following function initializes the cpu_context for a CPU specified by 538 * its `cpu_idx` for first use, and sets the initial entrypoint state as 539 * specified by the entry_point_info structure. 540 ******************************************************************************/ 541 void cm_init_context_by_index(unsigned int cpu_idx, 542 const entry_point_info_t *ep) 543 { 544 cpu_context_t *ctx; 545 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 546 cm_setup_context(ctx, ep); 547 } 548 549 /******************************************************************************* 550 * The following function initializes the cpu_context for the current CPU 551 * for first use, and sets the initial entrypoint state as specified by the 552 * entry_point_info structure. 553 ******************************************************************************/ 554 void cm_init_my_context(const entry_point_info_t *ep) 555 { 556 cpu_context_t *ctx; 557 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 558 cm_setup_context(ctx, ep); 559 } 560 561 /******************************************************************************* 562 * Prepare the CPU system registers for first entry into realm, secure, or 563 * normal world. 564 * 565 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 566 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 567 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 568 * For all entries, the EL1 registers are initialized from the cpu_context 569 ******************************************************************************/ 570 void cm_prepare_el3_exit(uint32_t security_state) 571 { 572 u_register_t sctlr_elx, scr_el3, mdcr_el2; 573 cpu_context_t *ctx = cm_get_context(security_state); 574 bool el2_unused = false; 575 uint64_t hcr_el2 = 0U; 576 577 assert(ctx != NULL); 578 579 if (security_state == NON_SECURE) { 580 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 581 CTX_SCR_EL3); 582 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 583 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 584 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 585 CTX_SCTLR_EL1); 586 sctlr_elx &= SCTLR_EE_BIT; 587 sctlr_elx |= SCTLR_EL2_RES1; 588 #if ERRATA_A75_764081 589 /* 590 * If workaround of errata 764081 for Cortex-A75 is used 591 * then set SCTLR_EL2.IESB to enable Implicit Error 592 * Synchronization Barrier. 593 */ 594 sctlr_elx |= SCTLR_IESB_BIT; 595 #endif 596 write_sctlr_el2(sctlr_elx); 597 } else if (el_implemented(2) != EL_IMPL_NONE) { 598 el2_unused = true; 599 600 /* 601 * EL2 present but unused, need to disable safely. 602 * SCTLR_EL2 can be ignored in this case. 603 * 604 * Set EL2 register width appropriately: Set HCR_EL2 605 * field to match SCR_EL3.RW. 606 */ 607 if ((scr_el3 & SCR_RW_BIT) != 0U) 608 hcr_el2 |= HCR_RW_BIT; 609 610 /* 611 * For Armv8.3 pointer authentication feature, disable 612 * traps to EL2 when accessing key registers or using 613 * pointer authentication instructions from lower ELs. 614 */ 615 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 616 617 write_hcr_el2(hcr_el2); 618 619 /* 620 * Initialise CPTR_EL2 setting all fields rather than 621 * relying on the hw. All fields have architecturally 622 * UNKNOWN reset values. 623 * 624 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 625 * accesses to the CPACR_EL1 or CPACR from both 626 * Execution states do not trap to EL2. 627 * 628 * CPTR_EL2.TTA: Set to zero so that Non-secure System 629 * register accesses to the trace registers from both 630 * Execution states do not trap to EL2. 631 * If PE trace unit System registers are not implemented 632 * then this bit is reserved, and must be set to zero. 633 * 634 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 635 * to SIMD and floating-point functionality from both 636 * Execution states do not trap to EL2. 637 */ 638 write_cptr_el2(CPTR_EL2_RESET_VAL & 639 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 640 | CPTR_EL2_TFP_BIT)); 641 642 /* 643 * Initialise CNTHCTL_EL2. All fields are 644 * architecturally UNKNOWN on reset and are set to zero 645 * except for field(s) listed below. 646 * 647 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 648 * Hyp mode of Non-secure EL0 and EL1 accesses to the 649 * physical timer registers. 650 * 651 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 652 * Hyp mode of Non-secure EL0 and EL1 accesses to the 653 * physical counter registers. 654 */ 655 write_cnthctl_el2(CNTHCTL_RESET_VAL | 656 EL1PCEN_BIT | EL1PCTEN_BIT); 657 658 /* 659 * Initialise CNTVOFF_EL2 to zero as it resets to an 660 * architecturally UNKNOWN value. 661 */ 662 write_cntvoff_el2(0); 663 664 /* 665 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 666 * MPIDR_EL1 respectively. 667 */ 668 write_vpidr_el2(read_midr_el1()); 669 write_vmpidr_el2(read_mpidr_el1()); 670 671 /* 672 * Initialise VTTBR_EL2. All fields are architecturally 673 * UNKNOWN on reset. 674 * 675 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 676 * 2 address translation is disabled, cache maintenance 677 * operations depend on the VMID. 678 * 679 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 680 * translation is disabled. 681 */ 682 write_vttbr_el2(VTTBR_RESET_VAL & 683 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 684 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 685 686 /* 687 * Initialise MDCR_EL2, setting all fields rather than 688 * relying on hw. Some fields are architecturally 689 * UNKNOWN on reset. 690 * 691 * MDCR_EL2.HLP: Set to one so that event counter 692 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 693 * occurs on the increment that changes 694 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 695 * implemented. This bit is RES0 in versions of the 696 * architecture earlier than ARMv8.5, setting it to 1 697 * doesn't have any effect on them. 698 * 699 * MDCR_EL2.TTRF: Set to zero so that access to Trace 700 * Filter Control register TRFCR_EL1 at EL1 is not 701 * trapped to EL2. This bit is RES0 in versions of 702 * the architecture earlier than ARMv8.4. 703 * 704 * MDCR_EL2.HPMD: Set to one so that event counting is 705 * prohibited at EL2. This bit is RES0 in versions of 706 * the architecture earlier than ARMv8.1, setting it 707 * to 1 doesn't have any effect on them. 708 * 709 * MDCR_EL2.TPMS: Set to zero so that accesses to 710 * Statistical Profiling control registers from EL1 711 * do not trap to EL2. This bit is RES0 when SPE is 712 * not implemented. 713 * 714 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 715 * EL1 System register accesses to the Debug ROM 716 * registers are not trapped to EL2. 717 * 718 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 719 * System register accesses to the powerdown debug 720 * registers are not trapped to EL2. 721 * 722 * MDCR_EL2.TDA: Set to zero so that System register 723 * accesses to the debug registers do not trap to EL2. 724 * 725 * MDCR_EL2.TDE: Set to zero so that debug exceptions 726 * are not routed to EL2. 727 * 728 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 729 * Monitors. 730 * 731 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 732 * EL1 accesses to all Performance Monitors registers 733 * are not trapped to EL2. 734 * 735 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 736 * and EL1 accesses to the PMCR_EL0 or PMCR are not 737 * trapped to EL2. 738 * 739 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 740 * architecturally-defined reset value. 741 * 742 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 743 * owning exception level is NS-EL1 and, tracing is 744 * prohibited at NS-EL2. These bits are RES0 when 745 * FEAT_TRBE is not implemented. 746 */ 747 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 748 MDCR_EL2_HPMD) | 749 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 750 >> PMCR_EL0_N_SHIFT)) & 751 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 752 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 753 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 754 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 755 MDCR_EL2_TPMCR_BIT | 756 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 757 758 write_mdcr_el2(mdcr_el2); 759 760 /* 761 * Initialise HSTR_EL2. All fields are architecturally 762 * UNKNOWN on reset. 763 * 764 * HSTR_EL2.T<n>: Set all these fields to zero so that 765 * Non-secure EL0 or EL1 accesses to System registers 766 * do not trap to EL2. 767 */ 768 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 769 /* 770 * Initialise CNTHP_CTL_EL2. All fields are 771 * architecturally UNKNOWN on reset. 772 * 773 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 774 * physical timer and prevent timer interrupts. 775 */ 776 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 777 ~(CNTHP_CTL_ENABLE_BIT)); 778 } 779 manage_extensions_nonsecure(el2_unused, ctx); 780 } 781 782 cm_el1_sysregs_context_restore(security_state); 783 cm_set_next_eret_context(security_state); 784 } 785 786 #if CTX_INCLUDE_EL2_REGS 787 /******************************************************************************* 788 * Save EL2 sysreg context 789 ******************************************************************************/ 790 void cm_el2_sysregs_context_save(uint32_t security_state) 791 { 792 u_register_t scr_el3 = read_scr(); 793 794 /* 795 * Always save the non-secure and realm EL2 context, only save the 796 * S-EL2 context if S-EL2 is enabled. 797 */ 798 if ((security_state != SECURE) || 799 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 800 cpu_context_t *ctx; 801 el2_sysregs_t *el2_sysregs_ctx; 802 803 ctx = cm_get_context(security_state); 804 assert(ctx != NULL); 805 806 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 807 808 el2_sysregs_context_save_common(el2_sysregs_ctx); 809 #if ENABLE_SPE_FOR_LOWER_ELS 810 el2_sysregs_context_save_spe(el2_sysregs_ctx); 811 #endif 812 #if CTX_INCLUDE_MTE_REGS 813 el2_sysregs_context_save_mte(el2_sysregs_ctx); 814 #endif 815 #if ENABLE_MPAM_FOR_LOWER_ELS 816 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 817 #endif 818 #if ENABLE_FEAT_FGT 819 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 820 #endif 821 #if ENABLE_FEAT_ECV 822 el2_sysregs_context_save_ecv(el2_sysregs_ctx); 823 #endif 824 #if ENABLE_FEAT_VHE 825 el2_sysregs_context_save_vhe(el2_sysregs_ctx); 826 #endif 827 #if RAS_EXTENSION 828 el2_sysregs_context_save_ras(el2_sysregs_ctx); 829 #endif 830 #if CTX_INCLUDE_NEVE_REGS 831 el2_sysregs_context_save_nv2(el2_sysregs_ctx); 832 #endif 833 #if ENABLE_TRF_FOR_NS 834 el2_sysregs_context_save_trf(el2_sysregs_ctx); 835 #endif 836 #if ENABLE_FEAT_CSV2_2 837 el2_sysregs_context_save_csv2(el2_sysregs_ctx); 838 #endif 839 #if ENABLE_FEAT_HCX 840 el2_sysregs_context_save_hcx(el2_sysregs_ctx); 841 #endif 842 } 843 } 844 845 /******************************************************************************* 846 * Restore EL2 sysreg context 847 ******************************************************************************/ 848 void cm_el2_sysregs_context_restore(uint32_t security_state) 849 { 850 u_register_t scr_el3 = read_scr(); 851 852 /* 853 * Always restore the non-secure and realm EL2 context, only restore the 854 * S-EL2 context if S-EL2 is enabled. 855 */ 856 if ((security_state != SECURE) || 857 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 858 cpu_context_t *ctx; 859 el2_sysregs_t *el2_sysregs_ctx; 860 861 ctx = cm_get_context(security_state); 862 assert(ctx != NULL); 863 864 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 865 866 el2_sysregs_context_restore_common(el2_sysregs_ctx); 867 #if ENABLE_SPE_FOR_LOWER_ELS 868 el2_sysregs_context_restore_spe(el2_sysregs_ctx); 869 #endif 870 #if CTX_INCLUDE_MTE_REGS 871 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 872 #endif 873 #if ENABLE_MPAM_FOR_LOWER_ELS 874 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 875 #endif 876 #if ENABLE_FEAT_FGT 877 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 878 #endif 879 #if ENABLE_FEAT_ECV 880 el2_sysregs_context_restore_ecv(el2_sysregs_ctx); 881 #endif 882 #if ENABLE_FEAT_VHE 883 el2_sysregs_context_restore_vhe(el2_sysregs_ctx); 884 #endif 885 #if RAS_EXTENSION 886 el2_sysregs_context_restore_ras(el2_sysregs_ctx); 887 #endif 888 #if CTX_INCLUDE_NEVE_REGS 889 el2_sysregs_context_restore_nv2(el2_sysregs_ctx); 890 #endif 891 #if ENABLE_TRF_FOR_NS 892 el2_sysregs_context_restore_trf(el2_sysregs_ctx); 893 #endif 894 #if ENABLE_FEAT_CSV2_2 895 el2_sysregs_context_restore_csv2(el2_sysregs_ctx); 896 #endif 897 #if ENABLE_FEAT_HCX 898 el2_sysregs_context_restore_hcx(el2_sysregs_ctx); 899 #endif 900 } 901 } 902 #endif /* CTX_INCLUDE_EL2_REGS */ 903 904 /******************************************************************************* 905 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 906 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 907 * updating EL1 and EL2 registers. Otherwise, it calls the generic 908 * cm_prepare_el3_exit function. 909 ******************************************************************************/ 910 void cm_prepare_el3_exit_ns(void) 911 { 912 #if CTX_INCLUDE_EL2_REGS 913 cpu_context_t *ctx = cm_get_context(NON_SECURE); 914 assert(ctx != NULL); 915 916 /* Assert that EL2 is used. */ 917 #if ENABLE_ASSERTIONS 918 el3_state_t *state = get_el3state_ctx(ctx); 919 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 920 #endif 921 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 922 (el_implemented(2U) != EL_IMPL_NONE)); 923 924 /* 925 * Currently some extensions are configured using 926 * direct register updates. Therefore, do this here 927 * instead of when setting up context. 928 */ 929 manage_extensions_nonsecure(0, ctx); 930 931 /* 932 * Set the NS bit to be able to access the ICC_SRE_EL2 933 * register when restoring context. 934 */ 935 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 936 937 /* 938 * Ensure the NS bit change is committed before the EL2/EL1 939 * state restoration. 940 */ 941 isb(); 942 943 /* Restore EL2 and EL1 sysreg contexts */ 944 cm_el2_sysregs_context_restore(NON_SECURE); 945 cm_el1_sysregs_context_restore(NON_SECURE); 946 cm_set_next_eret_context(NON_SECURE); 947 #else 948 cm_prepare_el3_exit(NON_SECURE); 949 #endif /* CTX_INCLUDE_EL2_REGS */ 950 } 951 952 /******************************************************************************* 953 * The next four functions are used by runtime services to save and restore 954 * EL1 context on the 'cpu_context' structure for the specified security 955 * state. 956 ******************************************************************************/ 957 void cm_el1_sysregs_context_save(uint32_t security_state) 958 { 959 cpu_context_t *ctx; 960 961 ctx = cm_get_context(security_state); 962 assert(ctx != NULL); 963 964 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 965 966 #if IMAGE_BL31 967 if (security_state == SECURE) 968 PUBLISH_EVENT(cm_exited_secure_world); 969 else 970 PUBLISH_EVENT(cm_exited_normal_world); 971 #endif 972 } 973 974 void cm_el1_sysregs_context_restore(uint32_t security_state) 975 { 976 cpu_context_t *ctx; 977 978 ctx = cm_get_context(security_state); 979 assert(ctx != NULL); 980 981 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 982 983 #if IMAGE_BL31 984 if (security_state == SECURE) 985 PUBLISH_EVENT(cm_entering_secure_world); 986 else 987 PUBLISH_EVENT(cm_entering_normal_world); 988 #endif 989 } 990 991 /******************************************************************************* 992 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 993 * given security state with the given entrypoint 994 ******************************************************************************/ 995 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 996 { 997 cpu_context_t *ctx; 998 el3_state_t *state; 999 1000 ctx = cm_get_context(security_state); 1001 assert(ctx != NULL); 1002 1003 /* Populate EL3 state so that ERET jumps to the correct entry */ 1004 state = get_el3state_ctx(ctx); 1005 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1006 } 1007 1008 /******************************************************************************* 1009 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1010 * pertaining to the given security state 1011 ******************************************************************************/ 1012 void cm_set_elr_spsr_el3(uint32_t security_state, 1013 uintptr_t entrypoint, uint32_t spsr) 1014 { 1015 cpu_context_t *ctx; 1016 el3_state_t *state; 1017 1018 ctx = cm_get_context(security_state); 1019 assert(ctx != NULL); 1020 1021 /* Populate EL3 state so that ERET jumps to the correct entry */ 1022 state = get_el3state_ctx(ctx); 1023 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1024 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1025 } 1026 1027 /******************************************************************************* 1028 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1029 * pertaining to the given security state using the value and bit position 1030 * specified in the parameters. It preserves all other bits. 1031 ******************************************************************************/ 1032 void cm_write_scr_el3_bit(uint32_t security_state, 1033 uint32_t bit_pos, 1034 uint32_t value) 1035 { 1036 cpu_context_t *ctx; 1037 el3_state_t *state; 1038 u_register_t scr_el3; 1039 1040 ctx = cm_get_context(security_state); 1041 assert(ctx != NULL); 1042 1043 /* Ensure that the bit position is a valid one */ 1044 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1045 1046 /* Ensure that the 'value' is only a bit wide */ 1047 assert(value <= 1U); 1048 1049 /* 1050 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1051 * and set it to its new value. 1052 */ 1053 state = get_el3state_ctx(ctx); 1054 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1055 scr_el3 &= ~(1UL << bit_pos); 1056 scr_el3 |= (u_register_t)value << bit_pos; 1057 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1058 } 1059 1060 /******************************************************************************* 1061 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1062 * given security state. 1063 ******************************************************************************/ 1064 u_register_t cm_get_scr_el3(uint32_t security_state) 1065 { 1066 cpu_context_t *ctx; 1067 el3_state_t *state; 1068 1069 ctx = cm_get_context(security_state); 1070 assert(ctx != NULL); 1071 1072 /* Populate EL3 state so that ERET jumps to the correct entry */ 1073 state = get_el3state_ctx(ctx); 1074 return read_ctx_reg(state, CTX_SCR_EL3); 1075 } 1076 1077 /******************************************************************************* 1078 * This function is used to program the context that's used for exception 1079 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1080 * the required security state 1081 ******************************************************************************/ 1082 void cm_set_next_eret_context(uint32_t security_state) 1083 { 1084 cpu_context_t *ctx; 1085 1086 ctx = cm_get_context(security_state); 1087 assert(ctx != NULL); 1088 1089 cm_set_next_context(ctx); 1090 } 1091