1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <amu.h> 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <bl_common.h> 12 #include <context.h> 13 #include <context_mgmt.h> 14 #include <interrupt_mgmt.h> 15 #include <platform.h> 16 #include <platform_def.h> 17 #include <pubsub_events.h> 18 #include <smccc_helpers.h> 19 #include <spe.h> 20 #include <string.h> 21 #include <sve.h> 22 #include <utils.h> 23 24 25 /******************************************************************************* 26 * Context management library initialisation routine. This library is used by 27 * runtime services to share pointers to 'cpu_context' structures for the secure 28 * and non-secure states. Management of the structures and their associated 29 * memory is not done by the context management library e.g. the PSCI service 30 * manages the cpu context used for entry from and exit to the non-secure state. 31 * The Secure payload dispatcher service manages the context(s) corresponding to 32 * the secure state. It also uses this library to get access to the non-secure 33 * state cpu context pointers. 34 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 35 * which will used for programming an entry into a lower EL. The same context 36 * will used to save state upon exception entry from that EL. 37 ******************************************************************************/ 38 void cm_init(void) 39 { 40 /* 41 * The context management library has only global data to intialize, but 42 * that will be done when the BSS is zeroed out 43 */ 44 } 45 46 /******************************************************************************* 47 * The following function initializes the cpu_context 'ctx' for 48 * first use, and sets the initial entrypoint state as specified by the 49 * entry_point_info structure. 50 * 51 * The security state to initialize is determined by the SECURE attribute 52 * of the entry_point_info. The function returns a pointer to the initialized 53 * context and sets this as the next context to return to. 54 * 55 * The EE and ST attributes are used to configure the endianess and secure 56 * timer availability for the new execution context. 57 * 58 * To prepare the register state for entry call cm_prepare_el3_exit() and 59 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 60 * cm_e1_sysreg_context_restore(). 61 ******************************************************************************/ 62 static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 63 { 64 unsigned int security_state; 65 uint32_t scr_el3, pmcr_el0; 66 el3_state_t *state; 67 gp_regs_t *gp_regs; 68 unsigned long sctlr_elx, actlr_elx; 69 70 assert(ctx); 71 72 security_state = GET_SECURITY_STATE(ep->h.attr); 73 74 /* Clear any residual register values from the context */ 75 zeromem(ctx, sizeof(*ctx)); 76 77 /* 78 * SCR_EL3 was initialised during reset sequence in macro 79 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 80 * affect the next EL. 81 * 82 * The following fields are initially set to zero and then updated to 83 * the required value depending on the state of the SPSR_EL3 and the 84 * Security state and entrypoint attributes of the next EL. 85 */ 86 scr_el3 = read_scr(); 87 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 88 SCR_ST_BIT | SCR_HCE_BIT); 89 /* 90 * SCR_NS: Set the security state of the next EL. 91 */ 92 if (security_state != SECURE) 93 scr_el3 |= SCR_NS_BIT; 94 /* 95 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 96 * Exception level as specified by SPSR. 97 */ 98 if (GET_RW(ep->spsr) == MODE_RW_64) 99 scr_el3 |= SCR_RW_BIT; 100 /* 101 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 102 * Secure timer registers to EL3, from AArch64 state only, if specified 103 * by the entrypoint attributes. 104 */ 105 if (EP_GET_ST(ep->h.attr)) 106 scr_el3 |= SCR_ST_BIT; 107 108 #ifndef HANDLE_EA_EL3_FIRST 109 /* 110 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 111 * to EL3 when executing at a lower EL. When executing at EL3, External 112 * Aborts are taken to EL3. 113 */ 114 scr_el3 &= ~SCR_EA_BIT; 115 #endif 116 117 #ifdef IMAGE_BL31 118 /* 119 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ rounting as 120 * indicated by the interrupt routing model for BL31. 121 */ 122 scr_el3 |= get_scr_el3_from_routing_model(security_state); 123 #endif 124 125 /* 126 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 127 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 128 * next mode is Hyp. 129 */ 130 if ((GET_RW(ep->spsr) == MODE_RW_64 131 && GET_EL(ep->spsr) == MODE_EL2) 132 || (GET_RW(ep->spsr) != MODE_RW_64 133 && GET_M32(ep->spsr) == MODE32_hyp)) { 134 scr_el3 |= SCR_HCE_BIT; 135 } 136 137 /* 138 * Initialise SCTLR_EL1 to the reset value corresponding to the target 139 * execution state setting all fields rather than relying of the hw. 140 * Some fields have architecturally UNKNOWN reset values and these are 141 * set to zero. 142 * 143 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 144 * 145 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 146 * required by PSCI specification) 147 */ 148 sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; 149 if (GET_RW(ep->spsr) == MODE_RW_64) 150 sctlr_elx |= SCTLR_EL1_RES1; 151 else { 152 /* 153 * If the target execution state is AArch32 then the following 154 * fields need to be set. 155 * 156 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 157 * instructions are not trapped to EL1. 158 * 159 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 160 * instructions are not trapped to EL1. 161 * 162 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 163 * CP15DMB, CP15DSB, and CP15ISB instructions. 164 */ 165 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 166 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 167 } 168 169 /* 170 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 171 * and other EL2 registers are set up by cm_preapre_ns_entry() as they 172 * are not part of the stored cpu_context. 173 */ 174 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 175 176 /* 177 * Base the context ACTLR_EL1 on the current value, as it is 178 * implementation defined. The context restore process will write 179 * the value from the context to the actual register and can cause 180 * problems for processor cores that don't expect certain bits to 181 * be zero. 182 */ 183 actlr_elx = read_actlr_el1(); 184 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 185 186 if (security_state == SECURE) { 187 /* 188 * Initialise PMCR_EL0 for secure context only, setting all 189 * fields rather than relying on hw. Some fields are 190 * architecturally UNKNOWN on reset. 191 * 192 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 193 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 194 * that changes PMCCNTR_EL0[63] from 1 to 0. 195 * 196 * PMCR_EL0.DP: Set to one so that the cycle counter, 197 * PMCCNTR_EL0 does not count when event counting is prohibited. 198 * 199 * PMCR_EL0.X: Set to zero to disable export of events. 200 * 201 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 202 * counts on every clock cycle. 203 */ 204 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT 205 | PMCR_EL0_DP_BIT) 206 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)); 207 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0); 208 } 209 210 /* Populate EL3 state so that we've the right context before doing ERET */ 211 state = get_el3state_ctx(ctx); 212 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 213 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 214 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 215 216 /* 217 * Store the X0-X7 value from the entrypoint into the context 218 * Use memcpy as we are in control of the layout of the structures 219 */ 220 gp_regs = get_gpregs_ctx(ctx); 221 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 222 } 223 224 /******************************************************************************* 225 * Enable architecture extensions on first entry to Non-secure world. 226 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 227 * it is zero. 228 ******************************************************************************/ 229 static void enable_extensions_nonsecure(int el2_unused) 230 { 231 #if IMAGE_BL31 232 #if ENABLE_SPE_FOR_LOWER_ELS 233 spe_enable(el2_unused); 234 #endif 235 236 #if ENABLE_AMU 237 amu_enable(el2_unused); 238 #endif 239 240 #if ENABLE_SVE_FOR_NS 241 sve_enable(el2_unused); 242 #endif 243 #endif 244 } 245 246 /******************************************************************************* 247 * The following function initializes the cpu_context for a CPU specified by 248 * its `cpu_idx` for first use, and sets the initial entrypoint state as 249 * specified by the entry_point_info structure. 250 ******************************************************************************/ 251 void cm_init_context_by_index(unsigned int cpu_idx, 252 const entry_point_info_t *ep) 253 { 254 cpu_context_t *ctx; 255 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 256 cm_init_context_common(ctx, ep); 257 } 258 259 /******************************************************************************* 260 * The following function initializes the cpu_context for the current CPU 261 * for first use, and sets the initial entrypoint state as specified by the 262 * entry_point_info structure. 263 ******************************************************************************/ 264 void cm_init_my_context(const entry_point_info_t *ep) 265 { 266 cpu_context_t *ctx; 267 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 268 cm_init_context_common(ctx, ep); 269 } 270 271 /******************************************************************************* 272 * Prepare the CPU system registers for first entry into secure or normal world 273 * 274 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 275 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 276 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 277 * For all entries, the EL1 registers are initialized from the cpu_context 278 ******************************************************************************/ 279 void cm_prepare_el3_exit(uint32_t security_state) 280 { 281 uint32_t sctlr_elx, scr_el3, mdcr_el2; 282 cpu_context_t *ctx = cm_get_context(security_state); 283 int el2_unused = 0; 284 285 assert(ctx); 286 287 if (security_state == NON_SECURE) { 288 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 289 if (scr_el3 & SCR_HCE_BIT) { 290 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 291 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), 292 CTX_SCTLR_EL1); 293 sctlr_elx &= SCTLR_EE_BIT; 294 sctlr_elx |= SCTLR_EL2_RES1; 295 write_sctlr_el2(sctlr_elx); 296 } else if (EL_IMPLEMENTED(2)) { 297 el2_unused = 1; 298 299 /* 300 * EL2 present but unused, need to disable safely. 301 * SCTLR_EL2 can be ignored in this case. 302 * 303 * Initialise all fields in HCR_EL2, except HCR_EL2.RW, 304 * to zero so that Non-secure operations do not trap to 305 * EL2. 306 * 307 * HCR_EL2.RW: Set this field to match SCR_EL3.RW 308 */ 309 write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0); 310 311 /* 312 * Initialise CPTR_EL2 setting all fields rather than 313 * relying on the hw. All fields have architecturally 314 * UNKNOWN reset values. 315 * 316 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 317 * accesses to the CPACR_EL1 or CPACR from both 318 * Execution states do not trap to EL2. 319 * 320 * CPTR_EL2.TTA: Set to zero so that Non-secure System 321 * register accesses to the trace registers from both 322 * Execution states do not trap to EL2. 323 * 324 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 325 * to SIMD and floating-point functionality from both 326 * Execution states do not trap to EL2. 327 */ 328 write_cptr_el2(CPTR_EL2_RESET_VAL & 329 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 330 | CPTR_EL2_TFP_BIT)); 331 332 /* 333 * Initiliase CNTHCTL_EL2. All fields are 334 * architecturally UNKNOWN on reset and are set to zero 335 * except for field(s) listed below. 336 * 337 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 338 * Hyp mode of Non-secure EL0 and EL1 accesses to the 339 * physical timer registers. 340 * 341 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 342 * Hyp mode of Non-secure EL0 and EL1 accesses to the 343 * physical counter registers. 344 */ 345 write_cnthctl_el2(CNTHCTL_RESET_VAL | 346 EL1PCEN_BIT | EL1PCTEN_BIT); 347 348 /* 349 * Initialise CNTVOFF_EL2 to zero as it resets to an 350 * architecturally UNKNOWN value. 351 */ 352 write_cntvoff_el2(0); 353 354 /* 355 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 356 * MPIDR_EL1 respectively. 357 */ 358 write_vpidr_el2(read_midr_el1()); 359 write_vmpidr_el2(read_mpidr_el1()); 360 361 /* 362 * Initialise VTTBR_EL2. All fields are architecturally 363 * UNKNOWN on reset. 364 * 365 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 366 * 2 address translation is disabled, cache maintenance 367 * operations depend on the VMID. 368 * 369 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 370 * translation is disabled. 371 */ 372 write_vttbr_el2(VTTBR_RESET_VAL & 373 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 374 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 375 376 /* 377 * Initialise MDCR_EL2, setting all fields rather than 378 * relying on hw. Some fields are architecturally 379 * UNKNOWN on reset. 380 * 381 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 382 * EL1 System register accesses to the Debug ROM 383 * registers are not trapped to EL2. 384 * 385 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 386 * System register accesses to the powerdown debug 387 * registers are not trapped to EL2. 388 * 389 * MDCR_EL2.TDA: Set to zero so that System register 390 * accesses to the debug registers do not trap to EL2. 391 * 392 * MDCR_EL2.TDE: Set to zero so that debug exceptions 393 * are not routed to EL2. 394 * 395 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 396 * Monitors. 397 * 398 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 399 * EL1 accesses to all Performance Monitors registers 400 * are not trapped to EL2. 401 * 402 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 403 * and EL1 accesses to the PMCR_EL0 or PMCR are not 404 * trapped to EL2. 405 * 406 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 407 * architecturally-defined reset value. 408 */ 409 mdcr_el2 = ((MDCR_EL2_RESET_VAL | 410 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 411 >> PMCR_EL0_N_SHIFT)) & 412 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT 413 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT 414 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT 415 | MDCR_EL2_TPMCR_BIT)); 416 417 write_mdcr_el2(mdcr_el2); 418 419 /* 420 * Initialise HSTR_EL2. All fields are architecturally 421 * UNKNOWN on reset. 422 * 423 * HSTR_EL2.T<n>: Set all these fields to zero so that 424 * Non-secure EL0 or EL1 accesses to System registers 425 * do not trap to EL2. 426 */ 427 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 428 /* 429 * Initialise CNTHP_CTL_EL2. All fields are 430 * architecturally UNKNOWN on reset. 431 * 432 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 433 * physical timer and prevent timer interrupts. 434 */ 435 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 436 ~(CNTHP_CTL_ENABLE_BIT)); 437 } 438 enable_extensions_nonsecure(el2_unused); 439 } 440 441 cm_el1_sysregs_context_restore(security_state); 442 cm_set_next_eret_context(security_state); 443 } 444 445 /******************************************************************************* 446 * The next four functions are used by runtime services to save and restore 447 * EL1 context on the 'cpu_context' structure for the specified security 448 * state. 449 ******************************************************************************/ 450 void cm_el1_sysregs_context_save(uint32_t security_state) 451 { 452 cpu_context_t *ctx; 453 454 ctx = cm_get_context(security_state); 455 assert(ctx); 456 457 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 458 459 #if IMAGE_BL31 460 if (security_state == SECURE) 461 PUBLISH_EVENT(cm_exited_secure_world); 462 else 463 PUBLISH_EVENT(cm_exited_normal_world); 464 #endif 465 } 466 467 void cm_el1_sysregs_context_restore(uint32_t security_state) 468 { 469 cpu_context_t *ctx; 470 471 ctx = cm_get_context(security_state); 472 assert(ctx); 473 474 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 475 476 #if IMAGE_BL31 477 if (security_state == SECURE) 478 PUBLISH_EVENT(cm_entering_secure_world); 479 else 480 PUBLISH_EVENT(cm_entering_normal_world); 481 #endif 482 } 483 484 /******************************************************************************* 485 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 486 * given security state with the given entrypoint 487 ******************************************************************************/ 488 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 489 { 490 cpu_context_t *ctx; 491 el3_state_t *state; 492 493 ctx = cm_get_context(security_state); 494 assert(ctx); 495 496 /* Populate EL3 state so that ERET jumps to the correct entry */ 497 state = get_el3state_ctx(ctx); 498 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 499 } 500 501 /******************************************************************************* 502 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 503 * pertaining to the given security state 504 ******************************************************************************/ 505 void cm_set_elr_spsr_el3(uint32_t security_state, 506 uintptr_t entrypoint, uint32_t spsr) 507 { 508 cpu_context_t *ctx; 509 el3_state_t *state; 510 511 ctx = cm_get_context(security_state); 512 assert(ctx); 513 514 /* Populate EL3 state so that ERET jumps to the correct entry */ 515 state = get_el3state_ctx(ctx); 516 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 517 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 518 } 519 520 /******************************************************************************* 521 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 522 * pertaining to the given security state using the value and bit position 523 * specified in the parameters. It preserves all other bits. 524 ******************************************************************************/ 525 void cm_write_scr_el3_bit(uint32_t security_state, 526 uint32_t bit_pos, 527 uint32_t value) 528 { 529 cpu_context_t *ctx; 530 el3_state_t *state; 531 uint32_t scr_el3; 532 533 ctx = cm_get_context(security_state); 534 assert(ctx); 535 536 /* Ensure that the bit position is a valid one */ 537 assert((1 << bit_pos) & SCR_VALID_BIT_MASK); 538 539 /* Ensure that the 'value' is only a bit wide */ 540 assert(value <= 1); 541 542 /* 543 * Get the SCR_EL3 value from the cpu context, clear the desired bit 544 * and set it to its new value. 545 */ 546 state = get_el3state_ctx(ctx); 547 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 548 scr_el3 &= ~(1 << bit_pos); 549 scr_el3 |= value << bit_pos; 550 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 551 } 552 553 /******************************************************************************* 554 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 555 * given security state. 556 ******************************************************************************/ 557 uint32_t cm_get_scr_el3(uint32_t security_state) 558 { 559 cpu_context_t *ctx; 560 el3_state_t *state; 561 562 ctx = cm_get_context(security_state); 563 assert(ctx); 564 565 /* Populate EL3 state so that ERET jumps to the correct entry */ 566 state = get_el3state_ctx(ctx); 567 return read_ctx_reg(state, CTX_SCR_EL3); 568 } 569 570 /******************************************************************************* 571 * This function is used to program the context that's used for exception 572 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 573 * the required security state 574 ******************************************************************************/ 575 void cm_set_next_eret_context(uint32_t security_state) 576 { 577 cpu_context_t *ctx; 578 579 ctx = cm_get_context(security_state); 580 assert(ctx); 581 582 cm_set_next_context(ctx); 583 } 584