1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/extensions/twed.h> 26 #include <lib/utils.h> 27 28 29 /******************************************************************************* 30 * Context management library initialisation routine. This library is used by 31 * runtime services to share pointers to 'cpu_context' structures for the secure 32 * and non-secure states. Management of the structures and their associated 33 * memory is not done by the context management library e.g. the PSCI service 34 * manages the cpu context used for entry from and exit to the non-secure state. 35 * The Secure payload dispatcher service manages the context(s) corresponding to 36 * the secure state. It also uses this library to get access to the non-secure 37 * state cpu context pointers. 38 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 39 * which will used for programming an entry into a lower EL. The same context 40 * will used to save state upon exception entry from that EL. 41 ******************************************************************************/ 42 void __init cm_init(void) 43 { 44 /* 45 * The context management library has only global data to intialize, but 46 * that will be done when the BSS is zeroed out 47 */ 48 } 49 50 /******************************************************************************* 51 * The following function initializes the cpu_context 'ctx' for 52 * first use, and sets the initial entrypoint state as specified by the 53 * entry_point_info structure. 54 * 55 * The security state to initialize is determined by the SECURE attribute 56 * of the entry_point_info. 57 * 58 * The EE and ST attributes are used to configure the endianness and secure 59 * timer availability for the new execution context. 60 * 61 * To prepare the register state for entry call cm_prepare_el3_exit() and 62 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 63 * cm_e1_sysreg_context_restore(). 64 ******************************************************************************/ 65 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 66 { 67 unsigned int security_state; 68 u_register_t scr_el3; 69 el3_state_t *state; 70 gp_regs_t *gp_regs; 71 u_register_t sctlr_elx, actlr_elx; 72 73 assert(ctx != NULL); 74 75 security_state = GET_SECURITY_STATE(ep->h.attr); 76 77 /* Clear any residual register values from the context */ 78 zeromem(ctx, sizeof(*ctx)); 79 80 /* 81 * SCR_EL3 was initialised during reset sequence in macro 82 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 83 * affect the next EL. 84 * 85 * The following fields are initially set to zero and then updated to 86 * the required value depending on the state of the SPSR_EL3 and the 87 * Security state and entrypoint attributes of the next EL. 88 */ 89 scr_el3 = read_scr(); 90 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 91 SCR_ST_BIT | SCR_HCE_BIT); 92 /* 93 * SCR_NS: Set the security state of the next EL. 94 */ 95 if (security_state != SECURE) 96 scr_el3 |= SCR_NS_BIT; 97 /* 98 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 99 * Exception level as specified by SPSR. 100 */ 101 if (GET_RW(ep->spsr) == MODE_RW_64) 102 scr_el3 |= SCR_RW_BIT; 103 /* 104 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 105 * Secure timer registers to EL3, from AArch64 state only, if specified 106 * by the entrypoint attributes. 107 */ 108 if (EP_GET_ST(ep->h.attr) != 0U) 109 scr_el3 |= SCR_ST_BIT; 110 111 #if !HANDLE_EA_EL3_FIRST 112 /* 113 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 114 * to EL3 when executing at a lower EL. When executing at EL3, External 115 * Aborts are taken to EL3. 116 */ 117 scr_el3 &= ~SCR_EA_BIT; 118 #endif 119 120 #if FAULT_INJECTION_SUPPORT 121 /* Enable fault injection from lower ELs */ 122 scr_el3 |= SCR_FIEN_BIT; 123 #endif 124 125 #if !CTX_INCLUDE_PAUTH_REGS 126 /* 127 * If the pointer authentication registers aren't saved during world 128 * switches the value of the registers can be leaked from the Secure to 129 * the Non-secure world. To prevent this, rather than enabling pointer 130 * authentication everywhere, we only enable it in the Non-secure world. 131 * 132 * If the Secure world wants to use pointer authentication, 133 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 134 */ 135 if (security_state == NON_SECURE) 136 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 137 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 138 139 /* 140 * Enable MTE support. Support is enabled unilaterally for the normal 141 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 142 * set. 143 */ 144 #if CTX_INCLUDE_MTE_REGS 145 assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX); 146 scr_el3 |= SCR_ATA_BIT; 147 #else 148 unsigned int mte = get_armv8_5_mte_support(); 149 if (mte == MTE_IMPLEMENTED_EL0) { 150 /* 151 * Can enable MTE across both worlds as no MTE registers are 152 * used 153 */ 154 scr_el3 |= SCR_ATA_BIT; 155 } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) { 156 /* 157 * Can only enable MTE in Non-Secure world without register 158 * saving 159 */ 160 scr_el3 |= SCR_ATA_BIT; 161 } 162 #endif 163 164 #ifdef IMAGE_BL31 165 /* 166 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 167 * indicated by the interrupt routing model for BL31. 168 */ 169 scr_el3 |= get_scr_el3_from_routing_model(security_state); 170 #endif 171 172 /* 173 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 174 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 175 * next mode is Hyp. 176 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 177 * same conditions as HVC instructions and when the processor supports 178 * ARMv8.6-FGT. 179 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 180 * CNTPOFF_EL2 register under the same conditions as HVC instructions 181 * and when the processor supports ECV. 182 */ 183 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 184 || ((GET_RW(ep->spsr) != MODE_RW_64) 185 && (GET_M32(ep->spsr) == MODE32_hyp))) { 186 scr_el3 |= SCR_HCE_BIT; 187 188 if (is_armv8_6_fgt_present()) { 189 scr_el3 |= SCR_FGTEN_BIT; 190 } 191 192 if (get_armv8_6_ecv_support() 193 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 194 scr_el3 |= SCR_ECVEN_BIT; 195 } 196 } 197 198 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 199 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { 200 if (GET_RW(ep->spsr) != MODE_RW_64) { 201 ERROR("S-EL2 can not be used in AArch32."); 202 panic(); 203 } 204 205 scr_el3 |= SCR_EEL2_BIT; 206 } 207 208 /* 209 * Initialise SCTLR_EL1 to the reset value corresponding to the target 210 * execution state setting all fields rather than relying of the hw. 211 * Some fields have architecturally UNKNOWN reset values and these are 212 * set to zero. 213 * 214 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 215 * 216 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 217 * required by PSCI specification) 218 */ 219 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 220 if (GET_RW(ep->spsr) == MODE_RW_64) 221 sctlr_elx |= SCTLR_EL1_RES1; 222 else { 223 /* 224 * If the target execution state is AArch32 then the following 225 * fields need to be set. 226 * 227 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 228 * instructions are not trapped to EL1. 229 * 230 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 231 * instructions are not trapped to EL1. 232 * 233 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 234 * CP15DMB, CP15DSB, and CP15ISB instructions. 235 */ 236 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 237 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 238 } 239 240 #if ERRATA_A75_764081 241 /* 242 * If workaround of errata 764081 for Cortex-A75 is used then set 243 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 244 */ 245 sctlr_elx |= SCTLR_IESB_BIT; 246 #endif 247 248 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 249 if (is_armv8_6_twed_present()) { 250 uint32_t delay = plat_arm_set_twedel_scr_el3(); 251 252 if (delay != TWED_DISABLED) { 253 /* Make sure delay value fits */ 254 assert((delay & ~SCR_TWEDEL_MASK) == 0U); 255 256 /* Set delay in SCR_EL3 */ 257 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 258 scr_el3 |= ((delay & SCR_TWEDEL_MASK) 259 << SCR_TWEDEL_SHIFT); 260 261 /* Enable WFE delay */ 262 scr_el3 |= SCR_TWEDEn_BIT; 263 } 264 } 265 266 /* 267 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 268 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 269 * are not part of the stored cpu_context. 270 */ 271 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 272 273 /* 274 * Base the context ACTLR_EL1 on the current value, as it is 275 * implementation defined. The context restore process will write 276 * the value from the context to the actual register and can cause 277 * problems for processor cores that don't expect certain bits to 278 * be zero. 279 */ 280 actlr_elx = read_actlr_el1(); 281 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 282 283 /* 284 * Populate EL3 state so that we've the right context 285 * before doing ERET 286 */ 287 state = get_el3state_ctx(ctx); 288 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 289 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 290 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 291 292 /* 293 * Store the X0-X7 value from the entrypoint into the context 294 * Use memcpy as we are in control of the layout of the structures 295 */ 296 gp_regs = get_gpregs_ctx(ctx); 297 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 298 } 299 300 /******************************************************************************* 301 * Enable architecture extensions on first entry to Non-secure world. 302 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 303 * it is zero. 304 ******************************************************************************/ 305 static void enable_extensions_nonsecure(bool el2_unused) 306 { 307 #if IMAGE_BL31 308 #if ENABLE_SPE_FOR_LOWER_ELS 309 spe_enable(el2_unused); 310 #endif 311 312 #if ENABLE_AMU 313 amu_enable(el2_unused); 314 #endif 315 316 #if ENABLE_SVE_FOR_NS 317 sve_enable(el2_unused); 318 #endif 319 320 #if ENABLE_MPAM_FOR_LOWER_ELS 321 mpam_enable(el2_unused); 322 #endif 323 #endif 324 } 325 326 /******************************************************************************* 327 * The following function initializes the cpu_context for a CPU specified by 328 * its `cpu_idx` for first use, and sets the initial entrypoint state as 329 * specified by the entry_point_info structure. 330 ******************************************************************************/ 331 void cm_init_context_by_index(unsigned int cpu_idx, 332 const entry_point_info_t *ep) 333 { 334 cpu_context_t *ctx; 335 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 336 cm_setup_context(ctx, ep); 337 } 338 339 /******************************************************************************* 340 * The following function initializes the cpu_context for the current CPU 341 * for first use, and sets the initial entrypoint state as specified by the 342 * entry_point_info structure. 343 ******************************************************************************/ 344 void cm_init_my_context(const entry_point_info_t *ep) 345 { 346 cpu_context_t *ctx; 347 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 348 cm_setup_context(ctx, ep); 349 } 350 351 /******************************************************************************* 352 * Prepare the CPU system registers for first entry into secure or normal world 353 * 354 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 355 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 356 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 357 * For all entries, the EL1 registers are initialized from the cpu_context 358 ******************************************************************************/ 359 void cm_prepare_el3_exit(uint32_t security_state) 360 { 361 u_register_t sctlr_elx, scr_el3, mdcr_el2; 362 cpu_context_t *ctx = cm_get_context(security_state); 363 bool el2_unused = false; 364 uint64_t hcr_el2 = 0U; 365 366 assert(ctx != NULL); 367 368 if (security_state == NON_SECURE) { 369 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 370 CTX_SCR_EL3); 371 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 372 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 373 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 374 CTX_SCTLR_EL1); 375 sctlr_elx &= SCTLR_EE_BIT; 376 sctlr_elx |= SCTLR_EL2_RES1; 377 #if ERRATA_A75_764081 378 /* 379 * If workaround of errata 764081 for Cortex-A75 is used 380 * then set SCTLR_EL2.IESB to enable Implicit Error 381 * Synchronization Barrier. 382 */ 383 sctlr_elx |= SCTLR_IESB_BIT; 384 #endif 385 write_sctlr_el2(sctlr_elx); 386 } else if (el_implemented(2) != EL_IMPL_NONE) { 387 el2_unused = true; 388 389 /* 390 * EL2 present but unused, need to disable safely. 391 * SCTLR_EL2 can be ignored in this case. 392 * 393 * Set EL2 register width appropriately: Set HCR_EL2 394 * field to match SCR_EL3.RW. 395 */ 396 if ((scr_el3 & SCR_RW_BIT) != 0U) 397 hcr_el2 |= HCR_RW_BIT; 398 399 /* 400 * For Armv8.3 pointer authentication feature, disable 401 * traps to EL2 when accessing key registers or using 402 * pointer authentication instructions from lower ELs. 403 */ 404 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 405 406 write_hcr_el2(hcr_el2); 407 408 /* 409 * Initialise CPTR_EL2 setting all fields rather than 410 * relying on the hw. All fields have architecturally 411 * UNKNOWN reset values. 412 * 413 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 414 * accesses to the CPACR_EL1 or CPACR from both 415 * Execution states do not trap to EL2. 416 * 417 * CPTR_EL2.TTA: Set to zero so that Non-secure System 418 * register accesses to the trace registers from both 419 * Execution states do not trap to EL2. 420 * 421 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 422 * to SIMD and floating-point functionality from both 423 * Execution states do not trap to EL2. 424 */ 425 write_cptr_el2(CPTR_EL2_RESET_VAL & 426 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 427 | CPTR_EL2_TFP_BIT)); 428 429 /* 430 * Initialise CNTHCTL_EL2. All fields are 431 * architecturally UNKNOWN on reset and are set to zero 432 * except for field(s) listed below. 433 * 434 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 435 * Hyp mode of Non-secure EL0 and EL1 accesses to the 436 * physical timer registers. 437 * 438 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 439 * Hyp mode of Non-secure EL0 and EL1 accesses to the 440 * physical counter registers. 441 */ 442 write_cnthctl_el2(CNTHCTL_RESET_VAL | 443 EL1PCEN_BIT | EL1PCTEN_BIT); 444 445 /* 446 * Initialise CNTVOFF_EL2 to zero as it resets to an 447 * architecturally UNKNOWN value. 448 */ 449 write_cntvoff_el2(0); 450 451 /* 452 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 453 * MPIDR_EL1 respectively. 454 */ 455 write_vpidr_el2(read_midr_el1()); 456 write_vmpidr_el2(read_mpidr_el1()); 457 458 /* 459 * Initialise VTTBR_EL2. All fields are architecturally 460 * UNKNOWN on reset. 461 * 462 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 463 * 2 address translation is disabled, cache maintenance 464 * operations depend on the VMID. 465 * 466 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 467 * translation is disabled. 468 */ 469 write_vttbr_el2(VTTBR_RESET_VAL & 470 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 471 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 472 473 /* 474 * Initialise MDCR_EL2, setting all fields rather than 475 * relying on hw. Some fields are architecturally 476 * UNKNOWN on reset. 477 * 478 * MDCR_EL2.HLP: Set to one so that event counter 479 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 480 * occurs on the increment that changes 481 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 482 * implemented. This bit is RES0 in versions of the 483 * architecture earlier than ARMv8.5, setting it to 1 484 * doesn't have any effect on them. 485 * 486 * MDCR_EL2.TTRF: Set to zero so that access to Trace 487 * Filter Control register TRFCR_EL1 at EL1 is not 488 * trapped to EL2. This bit is RES0 in versions of 489 * the architecture earlier than ARMv8.4. 490 * 491 * MDCR_EL2.HPMD: Set to one so that event counting is 492 * prohibited at EL2. This bit is RES0 in versions of 493 * the architecture earlier than ARMv8.1, setting it 494 * to 1 doesn't have any effect on them. 495 * 496 * MDCR_EL2.TPMS: Set to zero so that accesses to 497 * Statistical Profiling control registers from EL1 498 * do not trap to EL2. This bit is RES0 when SPE is 499 * not implemented. 500 * 501 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 502 * EL1 System register accesses to the Debug ROM 503 * registers are not trapped to EL2. 504 * 505 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 506 * System register accesses to the powerdown debug 507 * registers are not trapped to EL2. 508 * 509 * MDCR_EL2.TDA: Set to zero so that System register 510 * accesses to the debug registers do not trap to EL2. 511 * 512 * MDCR_EL2.TDE: Set to zero so that debug exceptions 513 * are not routed to EL2. 514 * 515 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 516 * Monitors. 517 * 518 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 519 * EL1 accesses to all Performance Monitors registers 520 * are not trapped to EL2. 521 * 522 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 523 * and EL1 accesses to the PMCR_EL0 or PMCR are not 524 * trapped to EL2. 525 * 526 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 527 * architecturally-defined reset value. 528 */ 529 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 530 MDCR_EL2_HPMD) | 531 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 532 >> PMCR_EL0_N_SHIFT)) & 533 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 534 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 535 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 536 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 537 MDCR_EL2_TPMCR_BIT); 538 539 write_mdcr_el2(mdcr_el2); 540 541 /* 542 * Initialise HSTR_EL2. All fields are architecturally 543 * UNKNOWN on reset. 544 * 545 * HSTR_EL2.T<n>: Set all these fields to zero so that 546 * Non-secure EL0 or EL1 accesses to System registers 547 * do not trap to EL2. 548 */ 549 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 550 /* 551 * Initialise CNTHP_CTL_EL2. All fields are 552 * architecturally UNKNOWN on reset. 553 * 554 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 555 * physical timer and prevent timer interrupts. 556 */ 557 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 558 ~(CNTHP_CTL_ENABLE_BIT)); 559 } 560 enable_extensions_nonsecure(el2_unused); 561 } 562 563 cm_el1_sysregs_context_restore(security_state); 564 cm_set_next_eret_context(security_state); 565 } 566 567 #if CTX_INCLUDE_EL2_REGS 568 /******************************************************************************* 569 * Save EL2 sysreg context 570 ******************************************************************************/ 571 void cm_el2_sysregs_context_save(uint32_t security_state) 572 { 573 u_register_t scr_el3 = read_scr(); 574 575 /* 576 * Always save the non-secure EL2 context, only save the 577 * S-EL2 context if S-EL2 is enabled. 578 */ 579 if ((security_state == NON_SECURE) || 580 ((scr_el3 & SCR_EEL2_BIT) != 0U)) { 581 cpu_context_t *ctx; 582 583 ctx = cm_get_context(security_state); 584 assert(ctx != NULL); 585 586 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 587 } 588 } 589 590 /******************************************************************************* 591 * Restore EL2 sysreg context 592 ******************************************************************************/ 593 void cm_el2_sysregs_context_restore(uint32_t security_state) 594 { 595 u_register_t scr_el3 = read_scr(); 596 597 /* 598 * Always restore the non-secure EL2 context, only restore the 599 * S-EL2 context if S-EL2 is enabled. 600 */ 601 if ((security_state == NON_SECURE) || 602 ((scr_el3 & SCR_EEL2_BIT) != 0U)) { 603 cpu_context_t *ctx; 604 605 ctx = cm_get_context(security_state); 606 assert(ctx != NULL); 607 608 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 609 } 610 } 611 #endif /* CTX_INCLUDE_EL2_REGS */ 612 613 /******************************************************************************* 614 * The next four functions are used by runtime services to save and restore 615 * EL1 context on the 'cpu_context' structure for the specified security 616 * state. 617 ******************************************************************************/ 618 void cm_el1_sysregs_context_save(uint32_t security_state) 619 { 620 cpu_context_t *ctx; 621 622 ctx = cm_get_context(security_state); 623 assert(ctx != NULL); 624 625 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 626 627 #if IMAGE_BL31 628 if (security_state == SECURE) 629 PUBLISH_EVENT(cm_exited_secure_world); 630 else 631 PUBLISH_EVENT(cm_exited_normal_world); 632 #endif 633 } 634 635 void cm_el1_sysregs_context_restore(uint32_t security_state) 636 { 637 cpu_context_t *ctx; 638 639 ctx = cm_get_context(security_state); 640 assert(ctx != NULL); 641 642 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 643 644 #if IMAGE_BL31 645 if (security_state == SECURE) 646 PUBLISH_EVENT(cm_entering_secure_world); 647 else 648 PUBLISH_EVENT(cm_entering_normal_world); 649 #endif 650 } 651 652 /******************************************************************************* 653 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 654 * given security state with the given entrypoint 655 ******************************************************************************/ 656 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 657 { 658 cpu_context_t *ctx; 659 el3_state_t *state; 660 661 ctx = cm_get_context(security_state); 662 assert(ctx != NULL); 663 664 /* Populate EL3 state so that ERET jumps to the correct entry */ 665 state = get_el3state_ctx(ctx); 666 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 667 } 668 669 /******************************************************************************* 670 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 671 * pertaining to the given security state 672 ******************************************************************************/ 673 void cm_set_elr_spsr_el3(uint32_t security_state, 674 uintptr_t entrypoint, uint32_t spsr) 675 { 676 cpu_context_t *ctx; 677 el3_state_t *state; 678 679 ctx = cm_get_context(security_state); 680 assert(ctx != NULL); 681 682 /* Populate EL3 state so that ERET jumps to the correct entry */ 683 state = get_el3state_ctx(ctx); 684 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 685 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 686 } 687 688 /******************************************************************************* 689 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 690 * pertaining to the given security state using the value and bit position 691 * specified in the parameters. It preserves all other bits. 692 ******************************************************************************/ 693 void cm_write_scr_el3_bit(uint32_t security_state, 694 uint32_t bit_pos, 695 uint32_t value) 696 { 697 cpu_context_t *ctx; 698 el3_state_t *state; 699 u_register_t scr_el3; 700 701 ctx = cm_get_context(security_state); 702 assert(ctx != NULL); 703 704 /* Ensure that the bit position is a valid one */ 705 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 706 707 /* Ensure that the 'value' is only a bit wide */ 708 assert(value <= 1U); 709 710 /* 711 * Get the SCR_EL3 value from the cpu context, clear the desired bit 712 * and set it to its new value. 713 */ 714 state = get_el3state_ctx(ctx); 715 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 716 scr_el3 &= ~(1U << bit_pos); 717 scr_el3 |= (u_register_t)value << bit_pos; 718 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 719 } 720 721 /******************************************************************************* 722 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 723 * given security state. 724 ******************************************************************************/ 725 u_register_t cm_get_scr_el3(uint32_t security_state) 726 { 727 cpu_context_t *ctx; 728 el3_state_t *state; 729 730 ctx = cm_get_context(security_state); 731 assert(ctx != NULL); 732 733 /* Populate EL3 state so that ERET jumps to the correct entry */ 734 state = get_el3state_ctx(ctx); 735 return read_ctx_reg(state, CTX_SCR_EL3); 736 } 737 738 /******************************************************************************* 739 * This function is used to program the context that's used for exception 740 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 741 * the required security state 742 ******************************************************************************/ 743 void cm_set_next_eret_context(uint32_t security_state) 744 { 745 cpu_context_t *ctx; 746 747 ctx = cm_get_context(security_state); 748 assert(ctx != NULL); 749 750 cm_set_next_context(ctx); 751 } 752