1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/extensions/trbe.h> 26 #include <lib/extensions/twed.h> 27 #include <lib/utils.h> 28 29 static void enable_extensions_secure(cpu_context_t *ctx); 30 31 /******************************************************************************* 32 * Context management library initialisation routine. This library is used by 33 * runtime services to share pointers to 'cpu_context' structures for the secure 34 * and non-secure states. Management of the structures and their associated 35 * memory is not done by the context management library e.g. the PSCI service 36 * manages the cpu context used for entry from and exit to the non-secure state. 37 * The Secure payload dispatcher service manages the context(s) corresponding to 38 * the secure state. It also uses this library to get access to the non-secure 39 * state cpu context pointers. 40 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 41 * which will used for programming an entry into a lower EL. The same context 42 * will used to save state upon exception entry from that EL. 43 ******************************************************************************/ 44 void __init cm_init(void) 45 { 46 /* 47 * The context management library has only global data to intialize, but 48 * that will be done when the BSS is zeroed out 49 */ 50 } 51 52 /******************************************************************************* 53 * The following function initializes the cpu_context 'ctx' for 54 * first use, and sets the initial entrypoint state as specified by the 55 * entry_point_info structure. 56 * 57 * The security state to initialize is determined by the SECURE attribute 58 * of the entry_point_info. 59 * 60 * The EE and ST attributes are used to configure the endianness and secure 61 * timer availability for the new execution context. 62 * 63 * To prepare the register state for entry call cm_prepare_el3_exit() and 64 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 65 * cm_el1_sysregs_context_restore(). 66 ******************************************************************************/ 67 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 68 { 69 unsigned int security_state; 70 u_register_t scr_el3; 71 el3_state_t *state; 72 gp_regs_t *gp_regs; 73 u_register_t sctlr_elx, actlr_elx; 74 75 assert(ctx != NULL); 76 77 security_state = GET_SECURITY_STATE(ep->h.attr); 78 79 /* Clear any residual register values from the context */ 80 zeromem(ctx, sizeof(*ctx)); 81 82 /* 83 * SCR_EL3 was initialised during reset sequence in macro 84 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 85 * affect the next EL. 86 * 87 * The following fields are initially set to zero and then updated to 88 * the required value depending on the state of the SPSR_EL3 and the 89 * Security state and entrypoint attributes of the next EL. 90 */ 91 scr_el3 = read_scr(); 92 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 93 SCR_ST_BIT | SCR_HCE_BIT); 94 /* 95 * SCR_NS: Set the security state of the next EL. 96 */ 97 if (security_state != SECURE) 98 scr_el3 |= SCR_NS_BIT; 99 /* 100 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 101 * Exception level as specified by SPSR. 102 */ 103 if (GET_RW(ep->spsr) == MODE_RW_64) 104 scr_el3 |= SCR_RW_BIT; 105 /* 106 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 107 * Secure timer registers to EL3, from AArch64 state only, if specified 108 * by the entrypoint attributes. 109 */ 110 if (EP_GET_ST(ep->h.attr) != 0U) 111 scr_el3 |= SCR_ST_BIT; 112 113 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 114 /* 115 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 116 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 117 */ 118 scr_el3 |= SCR_TERR_BIT; 119 #endif 120 121 #if !HANDLE_EA_EL3_FIRST 122 /* 123 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 124 * to EL3 when executing at a lower EL. When executing at EL3, External 125 * Aborts are taken to EL3. 126 */ 127 scr_el3 &= ~SCR_EA_BIT; 128 #endif 129 130 #if FAULT_INJECTION_SUPPORT 131 /* Enable fault injection from lower ELs */ 132 scr_el3 |= SCR_FIEN_BIT; 133 #endif 134 135 #if !CTX_INCLUDE_PAUTH_REGS 136 /* 137 * If the pointer authentication registers aren't saved during world 138 * switches the value of the registers can be leaked from the Secure to 139 * the Non-secure world. To prevent this, rather than enabling pointer 140 * authentication everywhere, we only enable it in the Non-secure world. 141 * 142 * If the Secure world wants to use pointer authentication, 143 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 144 */ 145 if (security_state == NON_SECURE) 146 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 147 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 148 149 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 150 /* Get Memory Tagging Extension support level */ 151 unsigned int mte = get_armv8_5_mte_support(); 152 #endif 153 /* 154 * Enable MTE support. Support is enabled unilaterally for the normal 155 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 156 * set. 157 */ 158 #if CTX_INCLUDE_MTE_REGS 159 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 160 scr_el3 |= SCR_ATA_BIT; 161 #else 162 /* 163 * When MTE is only implemented at EL0, it can be enabled 164 * across both worlds as no MTE registers are used. 165 */ 166 if ((mte == MTE_IMPLEMENTED_EL0) || 167 /* 168 * When MTE is implemented at all ELs, it can be only enabled 169 * in Non-Secure world without register saving. 170 */ 171 (((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) && 172 (security_state == NON_SECURE))) { 173 scr_el3 |= SCR_ATA_BIT; 174 } 175 #endif /* CTX_INCLUDE_MTE_REGS */ 176 177 #ifdef IMAGE_BL31 178 /* 179 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 180 * indicated by the interrupt routing model for BL31. 181 */ 182 scr_el3 |= get_scr_el3_from_routing_model(security_state); 183 #endif 184 185 /* Save the initialized value of CPTR_EL3 register */ 186 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 187 if (security_state == SECURE) { 188 enable_extensions_secure(ctx); 189 } 190 191 /* 192 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 193 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 194 * next mode is Hyp. 195 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 196 * same conditions as HVC instructions and when the processor supports 197 * ARMv8.6-FGT. 198 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 199 * CNTPOFF_EL2 register under the same conditions as HVC instructions 200 * and when the processor supports ECV. 201 */ 202 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 203 || ((GET_RW(ep->spsr) != MODE_RW_64) 204 && (GET_M32(ep->spsr) == MODE32_hyp))) { 205 scr_el3 |= SCR_HCE_BIT; 206 207 if (is_armv8_6_fgt_present()) { 208 scr_el3 |= SCR_FGTEN_BIT; 209 } 210 211 if (get_armv8_6_ecv_support() 212 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 213 scr_el3 |= SCR_ECVEN_BIT; 214 } 215 } 216 217 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 218 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { 219 if (GET_RW(ep->spsr) != MODE_RW_64) { 220 ERROR("S-EL2 can not be used in AArch32."); 221 panic(); 222 } 223 224 scr_el3 |= SCR_EEL2_BIT; 225 } 226 227 /* 228 * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3 229 * and EL2, when clear, this bit traps accesses from EL2 so we set it 230 * to 1 when EL2 is present. 231 */ 232 if (is_armv8_6_feat_amuv1p1_present() && 233 (el_implemented(2) != EL_IMPL_NONE)) { 234 scr_el3 |= SCR_AMVOFFEN_BIT; 235 } 236 237 /* 238 * Initialise SCTLR_EL1 to the reset value corresponding to the target 239 * execution state setting all fields rather than relying of the hw. 240 * Some fields have architecturally UNKNOWN reset values and these are 241 * set to zero. 242 * 243 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 244 * 245 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 246 * required by PSCI specification) 247 */ 248 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 249 if (GET_RW(ep->spsr) == MODE_RW_64) 250 sctlr_elx |= SCTLR_EL1_RES1; 251 else { 252 /* 253 * If the target execution state is AArch32 then the following 254 * fields need to be set. 255 * 256 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 257 * instructions are not trapped to EL1. 258 * 259 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 260 * instructions are not trapped to EL1. 261 * 262 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 263 * CP15DMB, CP15DSB, and CP15ISB instructions. 264 */ 265 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 266 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 267 } 268 269 #if ERRATA_A75_764081 270 /* 271 * If workaround of errata 764081 for Cortex-A75 is used then set 272 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 273 */ 274 sctlr_elx |= SCTLR_IESB_BIT; 275 #endif 276 277 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 278 if (is_armv8_6_twed_present()) { 279 uint32_t delay = plat_arm_set_twedel_scr_el3(); 280 281 if (delay != TWED_DISABLED) { 282 /* Make sure delay value fits */ 283 assert((delay & ~SCR_TWEDEL_MASK) == 0U); 284 285 /* Set delay in SCR_EL3 */ 286 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 287 scr_el3 |= ((delay & SCR_TWEDEL_MASK) 288 << SCR_TWEDEL_SHIFT); 289 290 /* Enable WFE delay */ 291 scr_el3 |= SCR_TWEDEn_BIT; 292 } 293 } 294 295 /* 296 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 297 * and other EL2 registers are set up by cm_prepare_el3_exit() as they 298 * are not part of the stored cpu_context. 299 */ 300 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 301 302 /* 303 * Base the context ACTLR_EL1 on the current value, as it is 304 * implementation defined. The context restore process will write 305 * the value from the context to the actual register and can cause 306 * problems for processor cores that don't expect certain bits to 307 * be zero. 308 */ 309 actlr_elx = read_actlr_el1(); 310 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 311 312 /* 313 * Populate EL3 state so that we've the right context 314 * before doing ERET 315 */ 316 state = get_el3state_ctx(ctx); 317 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 318 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 319 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 320 321 /* 322 * Store the X0-X7 value from the entrypoint into the context 323 * Use memcpy as we are in control of the layout of the structures 324 */ 325 gp_regs = get_gpregs_ctx(ctx); 326 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 327 } 328 329 /******************************************************************************* 330 * Enable architecture extensions on first entry to Non-secure world. 331 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 332 * it is zero. 333 ******************************************************************************/ 334 static void enable_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 335 { 336 #if IMAGE_BL31 337 #if ENABLE_SPE_FOR_LOWER_ELS 338 spe_enable(el2_unused); 339 #endif 340 341 #if ENABLE_AMU 342 amu_enable(el2_unused, ctx); 343 #endif 344 345 #if ENABLE_SVE_FOR_NS 346 sve_enable(ctx); 347 #endif 348 349 #if ENABLE_MPAM_FOR_LOWER_ELS 350 mpam_enable(el2_unused); 351 #endif 352 353 #if ENABLE_TRBE_FOR_NS 354 trbe_enable(); 355 #endif /* ENABLE_TRBE_FOR_NS */ 356 357 #endif 358 } 359 360 /******************************************************************************* 361 * Enable architecture extensions on first entry to Secure world. 362 ******************************************************************************/ 363 static void enable_extensions_secure(cpu_context_t *ctx) 364 { 365 #if IMAGE_BL31 366 #if ENABLE_SVE_FOR_SWD 367 sve_enable(ctx); 368 #endif 369 #endif 370 } 371 372 /******************************************************************************* 373 * The following function initializes the cpu_context for a CPU specified by 374 * its `cpu_idx` for first use, and sets the initial entrypoint state as 375 * specified by the entry_point_info structure. 376 ******************************************************************************/ 377 void cm_init_context_by_index(unsigned int cpu_idx, 378 const entry_point_info_t *ep) 379 { 380 cpu_context_t *ctx; 381 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 382 cm_setup_context(ctx, ep); 383 } 384 385 /******************************************************************************* 386 * The following function initializes the cpu_context for the current CPU 387 * for first use, and sets the initial entrypoint state as specified by the 388 * entry_point_info structure. 389 ******************************************************************************/ 390 void cm_init_my_context(const entry_point_info_t *ep) 391 { 392 cpu_context_t *ctx; 393 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 394 cm_setup_context(ctx, ep); 395 } 396 397 /******************************************************************************* 398 * Prepare the CPU system registers for first entry into secure or normal world 399 * 400 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 401 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 402 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 403 * For all entries, the EL1 registers are initialized from the cpu_context 404 ******************************************************************************/ 405 void cm_prepare_el3_exit(uint32_t security_state) 406 { 407 u_register_t sctlr_elx, scr_el3, mdcr_el2; 408 cpu_context_t *ctx = cm_get_context(security_state); 409 bool el2_unused = false; 410 uint64_t hcr_el2 = 0U; 411 412 assert(ctx != NULL); 413 414 if (security_state == NON_SECURE) { 415 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 416 CTX_SCR_EL3); 417 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 418 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 419 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 420 CTX_SCTLR_EL1); 421 sctlr_elx &= SCTLR_EE_BIT; 422 sctlr_elx |= SCTLR_EL2_RES1; 423 #if ERRATA_A75_764081 424 /* 425 * If workaround of errata 764081 for Cortex-A75 is used 426 * then set SCTLR_EL2.IESB to enable Implicit Error 427 * Synchronization Barrier. 428 */ 429 sctlr_elx |= SCTLR_IESB_BIT; 430 #endif 431 write_sctlr_el2(sctlr_elx); 432 } else if (el_implemented(2) != EL_IMPL_NONE) { 433 el2_unused = true; 434 435 /* 436 * EL2 present but unused, need to disable safely. 437 * SCTLR_EL2 can be ignored in this case. 438 * 439 * Set EL2 register width appropriately: Set HCR_EL2 440 * field to match SCR_EL3.RW. 441 */ 442 if ((scr_el3 & SCR_RW_BIT) != 0U) 443 hcr_el2 |= HCR_RW_BIT; 444 445 /* 446 * For Armv8.3 pointer authentication feature, disable 447 * traps to EL2 when accessing key registers or using 448 * pointer authentication instructions from lower ELs. 449 */ 450 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 451 452 write_hcr_el2(hcr_el2); 453 454 /* 455 * Initialise CPTR_EL2 setting all fields rather than 456 * relying on the hw. All fields have architecturally 457 * UNKNOWN reset values. 458 * 459 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 460 * accesses to the CPACR_EL1 or CPACR from both 461 * Execution states do not trap to EL2. 462 * 463 * CPTR_EL2.TTA: Set to zero so that Non-secure System 464 * register accesses to the trace registers from both 465 * Execution states do not trap to EL2. 466 * 467 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 468 * to SIMD and floating-point functionality from both 469 * Execution states do not trap to EL2. 470 */ 471 write_cptr_el2(CPTR_EL2_RESET_VAL & 472 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 473 | CPTR_EL2_TFP_BIT)); 474 475 /* 476 * Initialise CNTHCTL_EL2. All fields are 477 * architecturally UNKNOWN on reset and are set to zero 478 * except for field(s) listed below. 479 * 480 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 481 * Hyp mode of Non-secure EL0 and EL1 accesses to the 482 * physical timer registers. 483 * 484 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 485 * Hyp mode of Non-secure EL0 and EL1 accesses to the 486 * physical counter registers. 487 */ 488 write_cnthctl_el2(CNTHCTL_RESET_VAL | 489 EL1PCEN_BIT | EL1PCTEN_BIT); 490 491 /* 492 * Initialise CNTVOFF_EL2 to zero as it resets to an 493 * architecturally UNKNOWN value. 494 */ 495 write_cntvoff_el2(0); 496 497 /* 498 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 499 * MPIDR_EL1 respectively. 500 */ 501 write_vpidr_el2(read_midr_el1()); 502 write_vmpidr_el2(read_mpidr_el1()); 503 504 /* 505 * Initialise VTTBR_EL2. All fields are architecturally 506 * UNKNOWN on reset. 507 * 508 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 509 * 2 address translation is disabled, cache maintenance 510 * operations depend on the VMID. 511 * 512 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 513 * translation is disabled. 514 */ 515 write_vttbr_el2(VTTBR_RESET_VAL & 516 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 517 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 518 519 /* 520 * Initialise MDCR_EL2, setting all fields rather than 521 * relying on hw. Some fields are architecturally 522 * UNKNOWN on reset. 523 * 524 * MDCR_EL2.HLP: Set to one so that event counter 525 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 526 * occurs on the increment that changes 527 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 528 * implemented. This bit is RES0 in versions of the 529 * architecture earlier than ARMv8.5, setting it to 1 530 * doesn't have any effect on them. 531 * 532 * MDCR_EL2.TTRF: Set to zero so that access to Trace 533 * Filter Control register TRFCR_EL1 at EL1 is not 534 * trapped to EL2. This bit is RES0 in versions of 535 * the architecture earlier than ARMv8.4. 536 * 537 * MDCR_EL2.HPMD: Set to one so that event counting is 538 * prohibited at EL2. This bit is RES0 in versions of 539 * the architecture earlier than ARMv8.1, setting it 540 * to 1 doesn't have any effect on them. 541 * 542 * MDCR_EL2.TPMS: Set to zero so that accesses to 543 * Statistical Profiling control registers from EL1 544 * do not trap to EL2. This bit is RES0 when SPE is 545 * not implemented. 546 * 547 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 548 * EL1 System register accesses to the Debug ROM 549 * registers are not trapped to EL2. 550 * 551 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 552 * System register accesses to the powerdown debug 553 * registers are not trapped to EL2. 554 * 555 * MDCR_EL2.TDA: Set to zero so that System register 556 * accesses to the debug registers do not trap to EL2. 557 * 558 * MDCR_EL2.TDE: Set to zero so that debug exceptions 559 * are not routed to EL2. 560 * 561 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 562 * Monitors. 563 * 564 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 565 * EL1 accesses to all Performance Monitors registers 566 * are not trapped to EL2. 567 * 568 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 569 * and EL1 accesses to the PMCR_EL0 or PMCR are not 570 * trapped to EL2. 571 * 572 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 573 * architecturally-defined reset value. 574 * 575 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 576 * owning exception level is NS-EL1 and, tracing is 577 * prohibited at NS-EL2. These bits are RES0 when 578 * FEAT_TRBE is not implemented. 579 */ 580 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 581 MDCR_EL2_HPMD) | 582 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 583 >> PMCR_EL0_N_SHIFT)) & 584 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 585 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 586 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 587 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 588 MDCR_EL2_TPMCR_BIT | 589 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 590 591 write_mdcr_el2(mdcr_el2); 592 593 /* 594 * Initialise HSTR_EL2. All fields are architecturally 595 * UNKNOWN on reset. 596 * 597 * HSTR_EL2.T<n>: Set all these fields to zero so that 598 * Non-secure EL0 or EL1 accesses to System registers 599 * do not trap to EL2. 600 */ 601 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 602 /* 603 * Initialise CNTHP_CTL_EL2. All fields are 604 * architecturally UNKNOWN on reset. 605 * 606 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 607 * physical timer and prevent timer interrupts. 608 */ 609 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 610 ~(CNTHP_CTL_ENABLE_BIT)); 611 } 612 enable_extensions_nonsecure(el2_unused, ctx); 613 } 614 615 cm_el1_sysregs_context_restore(security_state); 616 cm_set_next_eret_context(security_state); 617 } 618 619 #if CTX_INCLUDE_EL2_REGS 620 /******************************************************************************* 621 * Save EL2 sysreg context 622 ******************************************************************************/ 623 void cm_el2_sysregs_context_save(uint32_t security_state) 624 { 625 u_register_t scr_el3 = read_scr(); 626 627 /* 628 * Always save the non-secure EL2 context, only save the 629 * S-EL2 context if S-EL2 is enabled. 630 */ 631 if ((security_state == NON_SECURE) || 632 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 633 cpu_context_t *ctx; 634 635 ctx = cm_get_context(security_state); 636 assert(ctx != NULL); 637 638 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 639 } 640 } 641 642 /******************************************************************************* 643 * Restore EL2 sysreg context 644 ******************************************************************************/ 645 void cm_el2_sysregs_context_restore(uint32_t security_state) 646 { 647 u_register_t scr_el3 = read_scr(); 648 649 /* 650 * Always restore the non-secure EL2 context, only restore the 651 * S-EL2 context if S-EL2 is enabled. 652 */ 653 if ((security_state == NON_SECURE) || 654 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 655 cpu_context_t *ctx; 656 657 ctx = cm_get_context(security_state); 658 assert(ctx != NULL); 659 660 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 661 } 662 } 663 #endif /* CTX_INCLUDE_EL2_REGS */ 664 665 /******************************************************************************* 666 * The next four functions are used by runtime services to save and restore 667 * EL1 context on the 'cpu_context' structure for the specified security 668 * state. 669 ******************************************************************************/ 670 void cm_el1_sysregs_context_save(uint32_t security_state) 671 { 672 cpu_context_t *ctx; 673 674 ctx = cm_get_context(security_state); 675 assert(ctx != NULL); 676 677 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 678 679 #if IMAGE_BL31 680 if (security_state == SECURE) 681 PUBLISH_EVENT(cm_exited_secure_world); 682 else 683 PUBLISH_EVENT(cm_exited_normal_world); 684 #endif 685 } 686 687 void cm_el1_sysregs_context_restore(uint32_t security_state) 688 { 689 cpu_context_t *ctx; 690 691 ctx = cm_get_context(security_state); 692 assert(ctx != NULL); 693 694 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 695 696 #if IMAGE_BL31 697 if (security_state == SECURE) 698 PUBLISH_EVENT(cm_entering_secure_world); 699 else 700 PUBLISH_EVENT(cm_entering_normal_world); 701 #endif 702 } 703 704 /******************************************************************************* 705 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 706 * given security state with the given entrypoint 707 ******************************************************************************/ 708 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 709 { 710 cpu_context_t *ctx; 711 el3_state_t *state; 712 713 ctx = cm_get_context(security_state); 714 assert(ctx != NULL); 715 716 /* Populate EL3 state so that ERET jumps to the correct entry */ 717 state = get_el3state_ctx(ctx); 718 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 719 } 720 721 /******************************************************************************* 722 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 723 * pertaining to the given security state 724 ******************************************************************************/ 725 void cm_set_elr_spsr_el3(uint32_t security_state, 726 uintptr_t entrypoint, uint32_t spsr) 727 { 728 cpu_context_t *ctx; 729 el3_state_t *state; 730 731 ctx = cm_get_context(security_state); 732 assert(ctx != NULL); 733 734 /* Populate EL3 state so that ERET jumps to the correct entry */ 735 state = get_el3state_ctx(ctx); 736 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 737 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 738 } 739 740 /******************************************************************************* 741 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 742 * pertaining to the given security state using the value and bit position 743 * specified in the parameters. It preserves all other bits. 744 ******************************************************************************/ 745 void cm_write_scr_el3_bit(uint32_t security_state, 746 uint32_t bit_pos, 747 uint32_t value) 748 { 749 cpu_context_t *ctx; 750 el3_state_t *state; 751 u_register_t scr_el3; 752 753 ctx = cm_get_context(security_state); 754 assert(ctx != NULL); 755 756 /* Ensure that the bit position is a valid one */ 757 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 758 759 /* Ensure that the 'value' is only a bit wide */ 760 assert(value <= 1U); 761 762 /* 763 * Get the SCR_EL3 value from the cpu context, clear the desired bit 764 * and set it to its new value. 765 */ 766 state = get_el3state_ctx(ctx); 767 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 768 scr_el3 &= ~(1UL << bit_pos); 769 scr_el3 |= (u_register_t)value << bit_pos; 770 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 771 } 772 773 /******************************************************************************* 774 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 775 * given security state. 776 ******************************************************************************/ 777 u_register_t cm_get_scr_el3(uint32_t security_state) 778 { 779 cpu_context_t *ctx; 780 el3_state_t *state; 781 782 ctx = cm_get_context(security_state); 783 assert(ctx != NULL); 784 785 /* Populate EL3 state so that ERET jumps to the correct entry */ 786 state = get_el3state_ctx(ctx); 787 return read_ctx_reg(state, CTX_SCR_EL3); 788 } 789 790 /******************************************************************************* 791 * This function is used to program the context that's used for exception 792 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 793 * the required security state 794 ******************************************************************************/ 795 void cm_set_next_eret_context(uint32_t security_state) 796 { 797 cpu_context_t *ctx; 798 799 ctx = cm_get_context(security_state); 800 assert(ctx != NULL); 801 802 cm_set_next_context(ctx); 803 } 804