1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/cpu_data.h> 24 #include <lib/el3_runtime/pubsub_events.h> 25 #include <lib/extensions/amu.h> 26 #include <lib/extensions/brbe.h> 27 #include <lib/extensions/debug_v8p9.h> 28 #include <lib/extensions/fgt2.h> 29 #include <lib/extensions/mpam.h> 30 #include <lib/extensions/pmuv3.h> 31 #include <lib/extensions/sme.h> 32 #include <lib/extensions/spe.h> 33 #include <lib/extensions/sve.h> 34 #include <lib/extensions/sys_reg_trace.h> 35 #include <lib/extensions/trbe.h> 36 #include <lib/extensions/trf.h> 37 #include <lib/utils.h> 38 39 #if ENABLE_FEAT_TWED 40 /* Make sure delay value fits within the range(0-15) */ 41 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 42 #endif /* ENABLE_FEAT_TWED */ 43 44 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 45 static bool has_secure_perworld_init; 46 47 static void manage_extensions_common(cpu_context_t *ctx); 48 static void manage_extensions_nonsecure(cpu_context_t *ctx); 49 static void manage_extensions_secure(cpu_context_t *ctx); 50 static void manage_extensions_secure_per_world(void); 51 52 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 53 { 54 u_register_t sctlr_elx, actlr_elx; 55 56 /* 57 * Initialise SCTLR_EL1 to the reset value corresponding to the target 58 * execution state setting all fields rather than relying on the hw. 59 * Some fields have architecturally UNKNOWN reset values and these are 60 * set to zero. 61 * 62 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 63 * 64 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 65 * required by PSCI specification) 66 */ 67 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 68 if (GET_RW(ep->spsr) == MODE_RW_64) { 69 sctlr_elx |= SCTLR_EL1_RES1; 70 } else { 71 /* 72 * If the target execution state is AArch32 then the following 73 * fields need to be set. 74 * 75 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 76 * instructions are not trapped to EL1. 77 * 78 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 79 * instructions are not trapped to EL1. 80 * 81 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 82 * CP15DMB, CP15DSB, and CP15ISB instructions. 83 */ 84 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 85 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 86 } 87 88 #if ERRATA_A75_764081 89 /* 90 * If workaround of errata 764081 for Cortex-A75 is used then set 91 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 92 */ 93 sctlr_elx |= SCTLR_IESB_BIT; 94 #endif 95 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 96 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 97 98 /* 99 * Base the context ACTLR_EL1 on the current value, as it is 100 * implementation defined. The context restore process will write 101 * the value from the context to the actual register and can cause 102 * problems for processor cores that don't expect certain bits to 103 * be zero. 104 */ 105 actlr_elx = read_actlr_el1(); 106 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 107 } 108 109 /****************************************************************************** 110 * This function performs initializations that are specific to SECURE state 111 * and updates the cpu context specified by 'ctx'. 112 *****************************************************************************/ 113 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 114 { 115 u_register_t scr_el3; 116 el3_state_t *state; 117 118 state = get_el3state_ctx(ctx); 119 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 120 121 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 122 /* 123 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 124 * indicated by the interrupt routing model for BL31. 125 */ 126 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 127 #endif 128 129 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 130 if (is_feat_mte2_supported()) { 131 scr_el3 |= SCR_ATA_BIT; 132 } 133 134 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 135 136 /* 137 * Initialize EL1 context registers unless SPMC is running 138 * at S-EL2. 139 */ 140 #if !SPMD_SPM_AT_SEL2 141 setup_el1_context(ctx, ep); 142 #endif 143 144 manage_extensions_secure(ctx); 145 146 /** 147 * manage_extensions_secure_per_world api has to be executed once, 148 * as the registers getting initialised, maintain constant value across 149 * all the cpus for the secure world. 150 * Henceforth, this check ensures that the registers are initialised once 151 * and avoids re-initialization from multiple cores. 152 */ 153 if (!has_secure_perworld_init) { 154 manage_extensions_secure_per_world(); 155 } 156 157 } 158 159 #if ENABLE_RME 160 /****************************************************************************** 161 * This function performs initializations that are specific to REALM state 162 * and updates the cpu context specified by 'ctx'. 163 *****************************************************************************/ 164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 165 { 166 u_register_t scr_el3; 167 el3_state_t *state; 168 169 state = get_el3state_ctx(ctx); 170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 173 174 /* CSV2 version 2 and above */ 175 if (is_feat_csv2_2_supported()) { 176 /* Enable access to the SCXTNUM_ELx registers. */ 177 scr_el3 |= SCR_EnSCXT_BIT; 178 } 179 180 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 181 } 182 #endif /* ENABLE_RME */ 183 184 /****************************************************************************** 185 * This function performs initializations that are specific to NON-SECURE state 186 * and updates the cpu context specified by 'ctx'. 187 *****************************************************************************/ 188 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 189 { 190 u_register_t scr_el3; 191 el3_state_t *state; 192 193 state = get_el3state_ctx(ctx); 194 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 195 196 /* SCR_NS: Set the NS bit */ 197 scr_el3 |= SCR_NS_BIT; 198 199 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 200 if (is_feat_mte2_supported()) { 201 scr_el3 |= SCR_ATA_BIT; 202 } 203 204 #if !CTX_INCLUDE_PAUTH_REGS 205 /* 206 * Pointer Authentication feature, if present, is always enabled by default 207 * for Non secure lower exception levels. We do not have an explicit 208 * flag to set it. 209 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 210 * exception levels of secure and realm worlds. 211 * 212 * To prevent the leakage between the worlds during world switch, 213 * we enable it only for the non-secure world. 214 * 215 * If the Secure/realm world wants to use pointer authentication, 216 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 217 * it will be enabled globally for all the contexts. 218 * 219 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 220 * other than EL3 221 * 222 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 223 * than EL3 224 */ 225 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 226 227 #endif /* CTX_INCLUDE_PAUTH_REGS */ 228 229 #if HANDLE_EA_EL3_FIRST_NS 230 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 231 scr_el3 |= SCR_EA_BIT; 232 #endif 233 234 #if RAS_TRAP_NS_ERR_REC_ACCESS 235 /* 236 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 237 * and RAS ERX registers from EL1 and EL2(from any security state) 238 * are trapped to EL3. 239 * Set here to trap only for NS EL1/EL2 240 * 241 */ 242 scr_el3 |= SCR_TERR_BIT; 243 #endif 244 245 /* CSV2 version 2 and above */ 246 if (is_feat_csv2_2_supported()) { 247 /* Enable access to the SCXTNUM_ELx registers. */ 248 scr_el3 |= SCR_EnSCXT_BIT; 249 } 250 251 #ifdef IMAGE_BL31 252 /* 253 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 254 * indicated by the interrupt routing model for BL31. 255 */ 256 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 257 #endif 258 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 259 260 /* Initialize EL1 context registers */ 261 setup_el1_context(ctx, ep); 262 263 /* Initialize EL2 context registers */ 264 #if CTX_INCLUDE_EL2_REGS 265 266 /* 267 * Initialize SCTLR_EL2 context register with reset value. 268 */ 269 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 270 271 if (is_feat_hcx_supported()) { 272 /* 273 * Initialize register HCRX_EL2 with its init value. 274 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 275 * chance that this can lead to unexpected behavior in lower 276 * ELs that have not been updated since the introduction of 277 * this feature if not properly initialized, especially when 278 * it comes to those bits that enable/disable traps. 279 */ 280 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 281 HCRX_EL2_INIT_VAL); 282 } 283 284 if (is_feat_fgt_supported()) { 285 /* 286 * Initialize HFG*_EL2 registers with a default value so legacy 287 * systems unaware of FEAT_FGT do not get trapped due to their lack 288 * of initialization for this feature. 289 */ 290 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 291 HFGITR_EL2_INIT_VAL); 292 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 293 HFGRTR_EL2_INIT_VAL); 294 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 295 HFGWTR_EL2_INIT_VAL); 296 } 297 298 #endif /* CTX_INCLUDE_EL2_REGS */ 299 300 manage_extensions_nonsecure(ctx); 301 } 302 303 /******************************************************************************* 304 * The following function performs initialization of the cpu_context 'ctx' 305 * for first use that is common to all security states, and sets the 306 * initial entrypoint state as specified by the entry_point_info structure. 307 * 308 * The EE and ST attributes are used to configure the endianness and secure 309 * timer availability for the new execution context. 310 ******************************************************************************/ 311 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 312 { 313 u_register_t scr_el3; 314 u_register_t mdcr_el3; 315 el3_state_t *state; 316 gp_regs_t *gp_regs; 317 318 state = get_el3state_ctx(ctx); 319 320 /* Clear any residual register values from the context */ 321 zeromem(ctx, sizeof(*ctx)); 322 323 /* 324 * The lower-EL context is zeroed so that no stale values leak to a world. 325 * It is assumed that an all-zero lower-EL context is good enough for it 326 * to boot correctly. However, there are very few registers where this 327 * is not true and some values need to be recreated. 328 */ 329 #if CTX_INCLUDE_EL2_REGS 330 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 331 332 /* 333 * These bits are set in the gicv3 driver. Losing them (especially the 334 * SRE bit) is problematic for all worlds. Henceforth recreate them. 335 */ 336 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 337 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 338 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 339 340 /* 341 * The actlr_el2 register can be initialized in platform's reset handler 342 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 343 */ 344 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 345 #endif /* CTX_INCLUDE_EL2_REGS */ 346 347 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 348 scr_el3 = SCR_RESET_VAL; 349 350 /* 351 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 352 * EL2, EL1 and EL0 are not trapped to EL3. 353 * 354 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 355 * EL2, EL1 and EL0 are not trapped to EL3. 356 * 357 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 358 * both Security states and both Execution states. 359 * 360 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 361 * Non-secure memory. 362 */ 363 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 364 365 scr_el3 |= SCR_SIF_BIT; 366 367 /* 368 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 369 * Exception level as specified by SPSR. 370 */ 371 if (GET_RW(ep->spsr) == MODE_RW_64) { 372 scr_el3 |= SCR_RW_BIT; 373 } 374 375 /* 376 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 377 * Secure timer registers to EL3, from AArch64 state only, if specified 378 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 379 * bit always behaves as 1 (i.e. secure physical timer register access 380 * is not trapped) 381 */ 382 if (EP_GET_ST(ep->h.attr) != 0U) { 383 scr_el3 |= SCR_ST_BIT; 384 } 385 386 /* 387 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 388 * SCR_EL3.HXEn. 389 */ 390 if (is_feat_hcx_supported()) { 391 scr_el3 |= SCR_HXEn_BIT; 392 } 393 394 /* 395 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 396 * registers are trapped to EL3. 397 */ 398 #if ENABLE_FEAT_RNG_TRAP 399 scr_el3 |= SCR_TRNDR_BIT; 400 #endif 401 402 #if FAULT_INJECTION_SUPPORT 403 /* Enable fault injection from lower ELs */ 404 scr_el3 |= SCR_FIEN_BIT; 405 #endif 406 407 #if CTX_INCLUDE_PAUTH_REGS 408 /* 409 * Enable Pointer Authentication globally for all the worlds. 410 * 411 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 412 * other than EL3 413 * 414 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 415 * than EL3 416 */ 417 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 418 #endif /* CTX_INCLUDE_PAUTH_REGS */ 419 420 /* 421 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 422 */ 423 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 424 scr_el3 |= SCR_TCR2EN_BIT; 425 } 426 427 /* 428 * SCR_EL3.PIEN: Enable permission indirection and overlay 429 * registers for AArch64 if present. 430 */ 431 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 432 scr_el3 |= SCR_PIEN_BIT; 433 } 434 435 /* 436 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 437 */ 438 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 439 scr_el3 |= SCR_GCSEn_BIT; 440 } 441 442 /* 443 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 444 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 445 * next mode is Hyp. 446 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 447 * same conditions as HVC instructions and when the processor supports 448 * ARMv8.6-FGT. 449 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 450 * CNTPOFF_EL2 register under the same conditions as HVC instructions 451 * and when the processor supports ECV. 452 */ 453 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 454 || ((GET_RW(ep->spsr) != MODE_RW_64) 455 && (GET_M32(ep->spsr) == MODE32_hyp))) { 456 scr_el3 |= SCR_HCE_BIT; 457 458 if (is_feat_fgt_supported()) { 459 scr_el3 |= SCR_FGTEN_BIT; 460 } 461 462 if (is_feat_ecv_supported()) { 463 scr_el3 |= SCR_ECVEN_BIT; 464 } 465 } 466 467 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 468 if (is_feat_twed_supported()) { 469 /* Set delay in SCR_EL3 */ 470 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 471 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 472 << SCR_TWEDEL_SHIFT); 473 474 /* Enable WFE delay */ 475 scr_el3 |= SCR_TWEDEn_BIT; 476 } 477 478 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 479 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 480 if (is_feat_sel2_supported()) { 481 scr_el3 |= SCR_EEL2_BIT; 482 } 483 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 484 485 /* 486 * Populate EL3 state so that we've the right context 487 * before doing ERET 488 */ 489 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 490 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 491 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 492 493 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 494 mdcr_el3 = MDCR_EL3_RESET_VAL; 495 496 /* --------------------------------------------------------------------- 497 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 498 * Some fields are architecturally UNKNOWN on reset. 499 * 500 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 501 * Debug exceptions, other than Breakpoint Instruction exceptions, are 502 * disabled from all ELs in Secure state. 503 * 504 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 505 * privileged debug from S-EL1. 506 * 507 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 508 * access to the powerdown debug registers do not trap to EL3. 509 * 510 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 511 * debug registers, other than those registers that are controlled by 512 * MDCR_EL3.TDOSA. 513 */ 514 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 515 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 516 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 517 518 /* 519 * Configure MDCR_EL3 register as applicable for each world 520 * (NS/Secure/Realm) context. 521 */ 522 manage_extensions_common(ctx); 523 524 /* 525 * Store the X0-X7 value from the entrypoint into the context 526 * Use memcpy as we are in control of the layout of the structures 527 */ 528 gp_regs = get_gpregs_ctx(ctx); 529 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 530 } 531 532 /******************************************************************************* 533 * Context management library initialization routine. This library is used by 534 * runtime services to share pointers to 'cpu_context' structures for secure 535 * non-secure and realm states. Management of the structures and their associated 536 * memory is not done by the context management library e.g. the PSCI service 537 * manages the cpu context used for entry from and exit to the non-secure state. 538 * The Secure payload dispatcher service manages the context(s) corresponding to 539 * the secure state. It also uses this library to get access to the non-secure 540 * state cpu context pointers. 541 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 542 * which will be used for programming an entry into a lower EL. The same context 543 * will be used to save state upon exception entry from that EL. 544 ******************************************************************************/ 545 void __init cm_init(void) 546 { 547 /* 548 * The context management library has only global data to initialize, but 549 * that will be done when the BSS is zeroed out. 550 */ 551 } 552 553 /******************************************************************************* 554 * This is the high-level function used to initialize the cpu_context 'ctx' for 555 * first use. It performs initializations that are common to all security states 556 * and initializations specific to the security state specified in 'ep' 557 ******************************************************************************/ 558 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 559 { 560 unsigned int security_state; 561 562 assert(ctx != NULL); 563 564 /* 565 * Perform initializations that are common 566 * to all security states 567 */ 568 setup_context_common(ctx, ep); 569 570 security_state = GET_SECURITY_STATE(ep->h.attr); 571 572 /* Perform security state specific initializations */ 573 switch (security_state) { 574 case SECURE: 575 setup_secure_context(ctx, ep); 576 break; 577 #if ENABLE_RME 578 case REALM: 579 setup_realm_context(ctx, ep); 580 break; 581 #endif 582 case NON_SECURE: 583 setup_ns_context(ctx, ep); 584 break; 585 default: 586 ERROR("Invalid security state\n"); 587 panic(); 588 break; 589 } 590 } 591 592 /******************************************************************************* 593 * Enable architecture extensions for EL3 execution. This function only updates 594 * registers in-place which are expected to either never change or be 595 * overwritten by el3_exit. 596 ******************************************************************************/ 597 #if IMAGE_BL31 598 void cm_manage_extensions_el3(void) 599 { 600 if (is_feat_amu_supported()) { 601 amu_init_el3(); 602 } 603 604 if (is_feat_sme_supported()) { 605 sme_init_el3(); 606 } 607 608 pmuv3_init_el3(); 609 } 610 #endif /* IMAGE_BL31 */ 611 612 /****************************************************************************** 613 * Function to initialise the registers with the RESET values in the context 614 * memory, which are maintained per world. 615 ******************************************************************************/ 616 #if IMAGE_BL31 617 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 618 { 619 /* 620 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 621 * 622 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 623 * by Advanced SIMD, floating-point or SVE instructions (if 624 * implemented) do not trap to EL3. 625 * 626 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 627 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 628 */ 629 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 630 631 per_world_ctx->ctx_cptr_el3 = cptr_el3; 632 633 /* 634 * Initialize MPAM3_EL3 to its default reset value 635 * 636 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 637 * all lower ELn MPAM3_EL3 register access to, trap to EL3 638 */ 639 640 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 641 } 642 #endif /* IMAGE_BL31 */ 643 644 /******************************************************************************* 645 * Initialise per_world_context for Non-Secure world. 646 * This function enables the architecture extensions, which have same value 647 * across the cores for the non-secure world. 648 ******************************************************************************/ 649 #if IMAGE_BL31 650 void manage_extensions_nonsecure_per_world(void) 651 { 652 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 653 654 if (is_feat_sme_supported()) { 655 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 656 } 657 658 if (is_feat_sve_supported()) { 659 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 660 } 661 662 if (is_feat_amu_supported()) { 663 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 664 } 665 666 if (is_feat_sys_reg_trace_supported()) { 667 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 668 } 669 670 if (is_feat_mpam_supported()) { 671 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 672 } 673 } 674 #endif /* IMAGE_BL31 */ 675 676 /******************************************************************************* 677 * Initialise per_world_context for Secure world. 678 * This function enables the architecture extensions, which have same value 679 * across the cores for the secure world. 680 ******************************************************************************/ 681 static void manage_extensions_secure_per_world(void) 682 { 683 #if IMAGE_BL31 684 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 685 686 if (is_feat_sme_supported()) { 687 688 if (ENABLE_SME_FOR_SWD) { 689 /* 690 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 691 * SME, SVE, and FPU/SIMD context properly managed. 692 */ 693 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 694 } else { 695 /* 696 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 697 * world can safely use the associated registers. 698 */ 699 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 700 } 701 } 702 if (is_feat_sve_supported()) { 703 if (ENABLE_SVE_FOR_SWD) { 704 /* 705 * Enable SVE and FPU in secure context, SPM must ensure 706 * that the SVE and FPU register contexts are properly managed. 707 */ 708 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 709 } else { 710 /* 711 * Disable SVE and FPU in secure context so non-secure world 712 * can safely use them. 713 */ 714 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 715 } 716 } 717 718 /* NS can access this but Secure shouldn't */ 719 if (is_feat_sys_reg_trace_supported()) { 720 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 721 } 722 723 has_secure_perworld_init = true; 724 #endif /* IMAGE_BL31 */ 725 } 726 727 /******************************************************************************* 728 * Enable architecture extensions on first entry to Non-secure world only 729 * and disable for secure world. 730 * 731 * NOTE: Arch features which have been provided with the capability of getting 732 * enabled only for non-secure world and being disabled for secure world are 733 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 734 ******************************************************************************/ 735 static void manage_extensions_common(cpu_context_t *ctx) 736 { 737 #if IMAGE_BL31 738 if (is_feat_spe_supported()) { 739 /* 740 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 741 */ 742 spe_enable(ctx); 743 } 744 745 if (is_feat_trbe_supported()) { 746 /* 747 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 748 * Realm state. 749 */ 750 trbe_enable(ctx); 751 } 752 753 if (is_feat_trf_supported()) { 754 /* 755 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 756 */ 757 trf_enable(ctx); 758 } 759 760 if (is_feat_brbe_supported()) { 761 /* 762 * Enable FEAT_BRBE for Non-Secure and prohibit for Secure state. 763 */ 764 brbe_enable(ctx); 765 } 766 #endif /* IMAGE_BL31 */ 767 } 768 769 /******************************************************************************* 770 * Enable architecture extensions on first entry to Non-secure world. 771 ******************************************************************************/ 772 static void manage_extensions_nonsecure(cpu_context_t *ctx) 773 { 774 #if IMAGE_BL31 775 if (is_feat_amu_supported()) { 776 amu_enable(ctx); 777 } 778 779 if (is_feat_sme_supported()) { 780 sme_enable(ctx); 781 } 782 783 if (is_feat_fgt2_supported()) { 784 fgt2_enable(ctx); 785 } 786 787 if (is_feat_debugv8p9_supported()) { 788 debugv8p9_extended_bp_wp_enable(ctx); 789 } 790 791 pmuv3_enable(ctx); 792 #endif /* IMAGE_BL31 */ 793 } 794 795 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 796 static __unused void enable_pauth_el2(void) 797 { 798 u_register_t hcr_el2 = read_hcr_el2(); 799 /* 800 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 801 * accessing key registers or using pointer authentication instructions 802 * from lower ELs. 803 */ 804 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 805 806 write_hcr_el2(hcr_el2); 807 } 808 809 #if INIT_UNUSED_NS_EL2 810 /******************************************************************************* 811 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 812 * world when EL2 is empty and unused. 813 ******************************************************************************/ 814 static void manage_extensions_nonsecure_el2_unused(void) 815 { 816 #if IMAGE_BL31 817 if (is_feat_spe_supported()) { 818 spe_init_el2_unused(); 819 } 820 821 if (is_feat_amu_supported()) { 822 amu_init_el2_unused(); 823 } 824 825 if (is_feat_mpam_supported()) { 826 mpam_init_el2_unused(); 827 } 828 829 if (is_feat_trbe_supported()) { 830 trbe_init_el2_unused(); 831 } 832 833 if (is_feat_sys_reg_trace_supported()) { 834 sys_reg_trace_init_el2_unused(); 835 } 836 837 if (is_feat_trf_supported()) { 838 trf_init_el2_unused(); 839 } 840 841 pmuv3_init_el2_unused(); 842 843 if (is_feat_sve_supported()) { 844 sve_init_el2_unused(); 845 } 846 847 if (is_feat_sme_supported()) { 848 sme_init_el2_unused(); 849 } 850 851 #if ENABLE_PAUTH 852 enable_pauth_el2(); 853 #endif /* ENABLE_PAUTH */ 854 #endif /* IMAGE_BL31 */ 855 } 856 #endif /* INIT_UNUSED_NS_EL2 */ 857 858 /******************************************************************************* 859 * Enable architecture extensions on first entry to Secure world. 860 ******************************************************************************/ 861 static void manage_extensions_secure(cpu_context_t *ctx) 862 { 863 #if IMAGE_BL31 864 if (is_feat_sme_supported()) { 865 if (ENABLE_SME_FOR_SWD) { 866 /* 867 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 868 * must ensure SME, SVE, and FPU/SIMD context properly managed. 869 */ 870 sme_init_el3(); 871 sme_enable(ctx); 872 } else { 873 /* 874 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 875 * world can safely use the associated registers. 876 */ 877 sme_disable(ctx); 878 } 879 } 880 #endif /* IMAGE_BL31 */ 881 } 882 883 #if !IMAGE_BL1 884 /******************************************************************************* 885 * The following function initializes the cpu_context for a CPU specified by 886 * its `cpu_idx` for first use, and sets the initial entrypoint state as 887 * specified by the entry_point_info structure. 888 ******************************************************************************/ 889 void cm_init_context_by_index(unsigned int cpu_idx, 890 const entry_point_info_t *ep) 891 { 892 cpu_context_t *ctx; 893 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 894 cm_setup_context(ctx, ep); 895 } 896 #endif /* !IMAGE_BL1 */ 897 898 /******************************************************************************* 899 * The following function initializes the cpu_context for the current CPU 900 * for first use, and sets the initial entrypoint state as specified by the 901 * entry_point_info structure. 902 ******************************************************************************/ 903 void cm_init_my_context(const entry_point_info_t *ep) 904 { 905 cpu_context_t *ctx; 906 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 907 cm_setup_context(ctx, ep); 908 } 909 910 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 911 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 912 { 913 #if INIT_UNUSED_NS_EL2 914 u_register_t hcr_el2 = HCR_RESET_VAL; 915 u_register_t mdcr_el2; 916 u_register_t scr_el3; 917 918 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 919 920 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 921 if ((scr_el3 & SCR_RW_BIT) != 0U) { 922 hcr_el2 |= HCR_RW_BIT; 923 } 924 925 write_hcr_el2(hcr_el2); 926 927 /* 928 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 929 * All fields have architecturally UNKNOWN reset values. 930 */ 931 write_cptr_el2(CPTR_EL2_RESET_VAL); 932 933 /* 934 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 935 * reset and are set to zero except for field(s) listed below. 936 * 937 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 938 * Non-secure EL0 and EL1 accesses to the physical timer registers. 939 * 940 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 941 * Non-secure EL0 and EL1 accesses to the physical counter registers. 942 */ 943 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 944 945 /* 946 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 947 * UNKNOWN value. 948 */ 949 write_cntvoff_el2(0); 950 951 /* 952 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 953 * respectively. 954 */ 955 write_vpidr_el2(read_midr_el1()); 956 write_vmpidr_el2(read_mpidr_el1()); 957 958 /* 959 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 960 * 961 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 962 * translation is disabled, cache maintenance operations depend on the 963 * VMID. 964 * 965 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 966 * disabled. 967 */ 968 write_vttbr_el2(VTTBR_RESET_VAL & 969 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 970 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 971 972 /* 973 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 974 * Some fields are architecturally UNKNOWN on reset. 975 * 976 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 977 * register accesses to the Debug ROM registers are not trapped to EL2. 978 * 979 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 980 * accesses to the powerdown debug registers are not trapped to EL2. 981 * 982 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 983 * debug registers do not trap to EL2. 984 * 985 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 986 * EL2. 987 */ 988 mdcr_el2 = MDCR_EL2_RESET_VAL & 989 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 990 MDCR_EL2_TDE_BIT); 991 992 write_mdcr_el2(mdcr_el2); 993 994 /* 995 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 996 * 997 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 998 * EL1 accesses to System registers do not trap to EL2. 999 */ 1000 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1001 1002 /* 1003 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1004 * reset. 1005 * 1006 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1007 * and prevent timer interrupts. 1008 */ 1009 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1010 1011 manage_extensions_nonsecure_el2_unused(); 1012 #endif /* INIT_UNUSED_NS_EL2 */ 1013 } 1014 1015 /******************************************************************************* 1016 * Prepare the CPU system registers for first entry into realm, secure, or 1017 * normal world. 1018 * 1019 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1020 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1021 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1022 * For all entries, the EL1 registers are initialized from the cpu_context 1023 ******************************************************************************/ 1024 void cm_prepare_el3_exit(uint32_t security_state) 1025 { 1026 u_register_t sctlr_el2, scr_el3; 1027 cpu_context_t *ctx = cm_get_context(security_state); 1028 1029 assert(ctx != NULL); 1030 1031 if (security_state == NON_SECURE) { 1032 uint64_t el2_implemented = el_implemented(2); 1033 1034 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1035 CTX_SCR_EL3); 1036 1037 if (el2_implemented != EL_IMPL_NONE) { 1038 1039 /* 1040 * If context is not being used for EL2, initialize 1041 * HCRX_EL2 with its init value here. 1042 */ 1043 if (is_feat_hcx_supported()) { 1044 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1045 } 1046 1047 /* 1048 * Initialize Fine-grained trap registers introduced 1049 * by FEAT_FGT so all traps are initially disabled when 1050 * switching to EL2 or a lower EL, preventing undesired 1051 * behavior. 1052 */ 1053 if (is_feat_fgt_supported()) { 1054 /* 1055 * Initialize HFG*_EL2 registers with a default 1056 * value so legacy systems unaware of FEAT_FGT 1057 * do not get trapped due to their lack of 1058 * initialization for this feature. 1059 */ 1060 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1061 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1062 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1063 } 1064 1065 /* Condition to ensure EL2 is being used. */ 1066 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1067 /* Initialize SCTLR_EL2 register with reset value. */ 1068 sctlr_el2 = SCTLR_EL2_RES1; 1069 #if ERRATA_A75_764081 1070 /* 1071 * If workaround of errata 764081 for Cortex-A75 1072 * is used then set SCTLR_EL2.IESB to enable 1073 * Implicit Error Synchronization Barrier. 1074 */ 1075 sctlr_el2 |= SCTLR_IESB_BIT; 1076 #endif 1077 write_sctlr_el2(sctlr_el2); 1078 } else { 1079 /* 1080 * (scr_el3 & SCR_HCE_BIT==0) 1081 * EL2 implemented but unused. 1082 */ 1083 init_nonsecure_el2_unused(ctx); 1084 } 1085 } 1086 } 1087 cm_el1_sysregs_context_restore(security_state); 1088 cm_set_next_eret_context(security_state); 1089 } 1090 1091 #if CTX_INCLUDE_EL2_REGS 1092 1093 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1094 { 1095 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1096 if (is_feat_amu_supported()) { 1097 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1098 } 1099 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1100 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1101 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1102 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1103 } 1104 1105 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1106 { 1107 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1108 if (is_feat_amu_supported()) { 1109 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1110 } 1111 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1112 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1113 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1114 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1115 } 1116 1117 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1118 { 1119 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1120 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1121 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1122 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1123 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1124 } 1125 1126 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1127 { 1128 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1129 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1130 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1131 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1132 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1133 } 1134 1135 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1136 { 1137 u_register_t mpam_idr = read_mpamidr_el1(); 1138 1139 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1140 1141 /* 1142 * The context registers that we intend to save would be part of the 1143 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1144 */ 1145 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1146 return; 1147 } 1148 1149 /* 1150 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1151 * MPAMIDR_HAS_HCR_BIT == 1. 1152 */ 1153 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1154 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1155 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1156 1157 /* 1158 * The number of MPAMVPM registers is implementation defined, their 1159 * number is stored in the MPAMIDR_EL1 register. 1160 */ 1161 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1162 case 7: 1163 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1164 __fallthrough; 1165 case 6: 1166 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1167 __fallthrough; 1168 case 5: 1169 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1170 __fallthrough; 1171 case 4: 1172 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1173 __fallthrough; 1174 case 3: 1175 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1176 __fallthrough; 1177 case 2: 1178 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1179 __fallthrough; 1180 case 1: 1181 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1182 break; 1183 } 1184 } 1185 1186 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1187 { 1188 u_register_t mpam_idr = read_mpamidr_el1(); 1189 1190 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1191 1192 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1193 return; 1194 } 1195 1196 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1197 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1198 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1199 1200 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1201 case 7: 1202 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1203 __fallthrough; 1204 case 6: 1205 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1206 __fallthrough; 1207 case 5: 1208 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1209 __fallthrough; 1210 case 4: 1211 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1212 __fallthrough; 1213 case 3: 1214 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1215 __fallthrough; 1216 case 2: 1217 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1218 __fallthrough; 1219 case 1: 1220 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1221 break; 1222 } 1223 } 1224 1225 /* --------------------------------------------------------------------------- 1226 * The following registers are not added: 1227 * ICH_AP0R<n>_EL2 1228 * ICH_AP1R<n>_EL2 1229 * ICH_LR<n>_EL2 1230 * 1231 * NOTE: For a system with S-EL2 present but not enabled, accessing 1232 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1233 * SCR_EL3.NS = 1 before accessing this register. 1234 * --------------------------------------------------------------------------- 1235 */ 1236 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1237 { 1238 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1239 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1240 #else 1241 u_register_t scr_el3 = read_scr_el3(); 1242 write_scr_el3(scr_el3 | SCR_NS_BIT); 1243 isb(); 1244 1245 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1246 1247 write_scr_el3(scr_el3); 1248 isb(); 1249 #endif 1250 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1251 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1252 } 1253 1254 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1255 { 1256 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1257 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1258 #else 1259 u_register_t scr_el3 = read_scr_el3(); 1260 write_scr_el3(scr_el3 | SCR_NS_BIT); 1261 isb(); 1262 1263 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1264 1265 write_scr_el3(scr_el3); 1266 isb(); 1267 #endif 1268 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1269 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1270 } 1271 1272 /* ----------------------------------------------------- 1273 * The following registers are not added: 1274 * AMEVCNTVOFF0<n>_EL2 1275 * AMEVCNTVOFF1<n>_EL2 1276 * ----------------------------------------------------- 1277 */ 1278 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1279 { 1280 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1281 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1282 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1283 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1284 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1285 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1286 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1287 if (CTX_INCLUDE_AARCH32_REGS) { 1288 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1289 } 1290 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1291 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1292 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1293 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1294 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1295 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1296 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1297 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1298 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1299 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1300 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1301 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1302 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1303 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1304 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2()); 1305 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1306 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1307 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1308 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1309 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2()); 1310 } 1311 1312 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1313 { 1314 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1315 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1316 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1317 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1318 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1319 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1320 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1321 if (CTX_INCLUDE_AARCH32_REGS) { 1322 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1323 } 1324 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1325 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1326 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1327 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1328 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1329 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1330 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1331 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1332 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1333 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1334 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1335 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1336 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1337 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1338 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1339 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1340 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1341 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1342 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1343 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1344 } 1345 1346 /******************************************************************************* 1347 * Save EL2 sysreg context 1348 ******************************************************************************/ 1349 void cm_el2_sysregs_context_save(uint32_t security_state) 1350 { 1351 cpu_context_t *ctx; 1352 el2_sysregs_t *el2_sysregs_ctx; 1353 1354 ctx = cm_get_context(security_state); 1355 assert(ctx != NULL); 1356 1357 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1358 1359 el2_sysregs_context_save_common(el2_sysregs_ctx); 1360 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1361 1362 if (is_feat_mte2_supported()) { 1363 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1364 } 1365 1366 if (is_feat_mpam_supported()) { 1367 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1368 } 1369 1370 if (is_feat_fgt_supported()) { 1371 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1372 } 1373 1374 if (is_feat_fgt2_supported()) { 1375 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1376 } 1377 1378 if (is_feat_ecv_v2_supported()) { 1379 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1380 } 1381 1382 if (is_feat_vhe_supported()) { 1383 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1384 read_contextidr_el2()); 1385 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1386 } 1387 1388 if (is_feat_ras_supported()) { 1389 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1390 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1391 } 1392 1393 if (is_feat_nv2_supported()) { 1394 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1395 } 1396 1397 if (is_feat_trf_supported()) { 1398 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1399 } 1400 1401 if (is_feat_csv2_2_supported()) { 1402 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1403 read_scxtnum_el2()); 1404 } 1405 1406 if (is_feat_hcx_supported()) { 1407 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1408 } 1409 1410 if (is_feat_tcr2_supported()) { 1411 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1412 } 1413 1414 if (is_feat_sxpie_supported()) { 1415 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1416 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1417 } 1418 1419 if (is_feat_sxpoe_supported()) { 1420 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1421 } 1422 1423 if (is_feat_s2pie_supported()) { 1424 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1425 } 1426 1427 if (is_feat_gcs_supported()) { 1428 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1429 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1430 } 1431 } 1432 1433 /******************************************************************************* 1434 * Restore EL2 sysreg context 1435 ******************************************************************************/ 1436 void cm_el2_sysregs_context_restore(uint32_t security_state) 1437 { 1438 cpu_context_t *ctx; 1439 el2_sysregs_t *el2_sysregs_ctx; 1440 1441 ctx = cm_get_context(security_state); 1442 assert(ctx != NULL); 1443 1444 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1445 1446 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1447 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1448 1449 if (is_feat_mte2_supported()) { 1450 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1451 } 1452 1453 if (is_feat_mpam_supported()) { 1454 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1455 } 1456 1457 if (is_feat_fgt_supported()) { 1458 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1459 } 1460 1461 if (is_feat_fgt2_supported()) { 1462 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1463 } 1464 1465 if (is_feat_ecv_v2_supported()) { 1466 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1467 } 1468 1469 if (is_feat_vhe_supported()) { 1470 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1471 contextidr_el2)); 1472 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1473 } 1474 1475 if (is_feat_ras_supported()) { 1476 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1477 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1478 } 1479 1480 if (is_feat_nv2_supported()) { 1481 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1482 } 1483 1484 if (is_feat_trf_supported()) { 1485 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1486 } 1487 1488 if (is_feat_csv2_2_supported()) { 1489 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1490 scxtnum_el2)); 1491 } 1492 1493 if (is_feat_hcx_supported()) { 1494 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1495 } 1496 1497 if (is_feat_tcr2_supported()) { 1498 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1499 } 1500 1501 if (is_feat_sxpie_supported()) { 1502 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1503 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1504 } 1505 1506 if (is_feat_sxpoe_supported()) { 1507 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1508 } 1509 1510 if (is_feat_s2pie_supported()) { 1511 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1512 } 1513 1514 if (is_feat_gcs_supported()) { 1515 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1516 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1517 } 1518 } 1519 #endif /* CTX_INCLUDE_EL2_REGS */ 1520 1521 /******************************************************************************* 1522 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1523 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1524 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1525 * cm_prepare_el3_exit function. 1526 ******************************************************************************/ 1527 void cm_prepare_el3_exit_ns(void) 1528 { 1529 #if CTX_INCLUDE_EL2_REGS 1530 #if ENABLE_ASSERTIONS 1531 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1532 assert(ctx != NULL); 1533 1534 /* Assert that EL2 is used. */ 1535 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1536 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1537 (el_implemented(2U) != EL_IMPL_NONE)); 1538 #endif /* ENABLE_ASSERTIONS */ 1539 1540 /* Restore EL2 and EL1 sysreg contexts */ 1541 cm_el2_sysregs_context_restore(NON_SECURE); 1542 cm_el1_sysregs_context_restore(NON_SECURE); 1543 cm_set_next_eret_context(NON_SECURE); 1544 #else 1545 cm_prepare_el3_exit(NON_SECURE); 1546 #endif /* CTX_INCLUDE_EL2_REGS */ 1547 } 1548 1549 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1550 { 1551 write_ctx_reg(ctx, CTX_SPSR_EL1, read_spsr_el1()); 1552 write_ctx_reg(ctx, CTX_ELR_EL1, read_elr_el1()); 1553 1554 #if !ERRATA_SPECULATIVE_AT 1555 write_ctx_reg(ctx, CTX_SCTLR_EL1, read_sctlr_el1()); 1556 write_ctx_reg(ctx, CTX_TCR_EL1, read_tcr_el1()); 1557 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1558 1559 write_ctx_reg(ctx, CTX_CPACR_EL1, read_cpacr_el1()); 1560 write_ctx_reg(ctx, CTX_CSSELR_EL1, read_csselr_el1()); 1561 write_ctx_reg(ctx, CTX_SP_EL1, read_sp_el1()); 1562 write_ctx_reg(ctx, CTX_ESR_EL1, read_esr_el1()); 1563 write_ctx_reg(ctx, CTX_TTBR0_EL1, read_ttbr0_el1()); 1564 write_ctx_reg(ctx, CTX_TTBR1_EL1, read_ttbr1_el1()); 1565 write_ctx_reg(ctx, CTX_MAIR_EL1, read_mair_el1()); 1566 write_ctx_reg(ctx, CTX_AMAIR_EL1, read_amair_el1()); 1567 write_ctx_reg(ctx, CTX_ACTLR_EL1, read_actlr_el1()); 1568 write_ctx_reg(ctx, CTX_TPIDR_EL1, read_tpidr_el1()); 1569 write_ctx_reg(ctx, CTX_TPIDR_EL0, read_tpidr_el0()); 1570 write_ctx_reg(ctx, CTX_TPIDRRO_EL0, read_tpidrro_el0()); 1571 write_ctx_reg(ctx, CTX_PAR_EL1, read_par_el1()); 1572 write_ctx_reg(ctx, CTX_FAR_EL1, read_far_el1()); 1573 write_ctx_reg(ctx, CTX_AFSR0_EL1, read_afsr0_el1()); 1574 write_ctx_reg(ctx, CTX_AFSR1_EL1, read_afsr1_el1()); 1575 write_ctx_reg(ctx, CTX_CONTEXTIDR_EL1, read_contextidr_el1()); 1576 write_ctx_reg(ctx, CTX_VBAR_EL1, read_vbar_el1()); 1577 write_ctx_reg(ctx, CTX_MDCCINT_EL1, read_mdccint_el1()); 1578 write_ctx_reg(ctx, CTX_MDSCR_EL1, read_mdscr_el1()); 1579 1580 #if CTX_INCLUDE_AARCH32_REGS 1581 write_ctx_reg(ctx, CTX_SPSR_ABT, read_spsr_abt()); 1582 write_ctx_reg(ctx, CTX_SPSR_UND, read_spsr_und()); 1583 write_ctx_reg(ctx, CTX_SPSR_IRQ, read_spsr_irq()); 1584 write_ctx_reg(ctx, CTX_SPSR_FIQ, read_spsr_fiq()); 1585 write_ctx_reg(ctx, CTX_DACR32_EL2, read_dacr32_el2()); 1586 write_ctx_reg(ctx, CTX_IFSR32_EL2, read_ifsr32_el2()); 1587 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1588 1589 #if NS_TIMER_SWITCH 1590 write_ctx_reg(ctx, CTX_CNTP_CTL_EL0, read_cntp_ctl_el0()); 1591 write_ctx_reg(ctx, CTX_CNTP_CVAL_EL0, read_cntp_cval_el0()); 1592 write_ctx_reg(ctx, CTX_CNTV_CTL_EL0, read_cntv_ctl_el0()); 1593 write_ctx_reg(ctx, CTX_CNTV_CVAL_EL0, read_cntv_cval_el0()); 1594 write_ctx_reg(ctx, CTX_CNTKCTL_EL1, read_cntkctl_el1()); 1595 #endif /* NS_TIMER_SWITCH */ 1596 1597 #if ENABLE_FEAT_MTE2 1598 write_ctx_reg(ctx, CTX_TFSRE0_EL1, read_tfsre0_el1()); 1599 write_ctx_reg(ctx, CTX_TFSR_EL1, read_tfsr_el1()); 1600 write_ctx_reg(ctx, CTX_RGSR_EL1, read_rgsr_el1()); 1601 write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1()); 1602 #endif /* ENABLE_FEAT_MTE2 */ 1603 1604 #if ENABLE_FEAT_RAS 1605 if (is_feat_ras_supported()) { 1606 write_ctx_reg(ctx, CTX_DISR_EL1, read_disr_el1()); 1607 } 1608 #endif 1609 1610 #if ENABLE_FEAT_S1PIE 1611 if (is_feat_s1pie_supported()) { 1612 write_ctx_reg(ctx, CTX_PIRE0_EL1, read_pire0_el1()); 1613 write_ctx_reg(ctx, CTX_PIR_EL1, read_pir_el1()); 1614 } 1615 #endif 1616 1617 #if ENABLE_FEAT_S1POE 1618 if (is_feat_s1poe_supported()) { 1619 write_ctx_reg(ctx, CTX_POR_EL1, read_por_el1()); 1620 } 1621 #endif 1622 1623 #if ENABLE_FEAT_S2POE 1624 if (is_feat_s2poe_supported()) { 1625 write_ctx_reg(ctx, CTX_S2POR_EL1, read_s2por_el1()); 1626 } 1627 #endif 1628 1629 #if ENABLE_FEAT_TCR2 1630 if (is_feat_tcr2_supported()) { 1631 write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1()); 1632 } 1633 #endif 1634 1635 #if ENABLE_TRF_FOR_NS 1636 if (is_feat_trf_supported()) { 1637 write_ctx_reg(ctx, CTX_TRFCR_EL1, read_trfcr_el1()); 1638 } 1639 #endif 1640 1641 #if ENABLE_FEAT_CSV2_2 1642 if (is_feat_csv2_2_supported()) { 1643 write_ctx_reg(ctx, CTX_SCXTNUM_EL0, read_scxtnum_el0()); 1644 write_ctx_reg(ctx, CTX_SCXTNUM_EL1, read_scxtnum_el1()); 1645 } 1646 #endif 1647 1648 #if ENABLE_FEAT_GCS 1649 if (is_feat_gcs_supported()) { 1650 write_ctx_reg(ctx, CTX_GCSCR_EL1, read_gcscr_el1()); 1651 write_ctx_reg(ctx, CTX_GCSCRE0_EL1, read_gcscre0_el1()); 1652 write_ctx_reg(ctx, CTX_GCSPR_EL1, read_gcspr_el1()); 1653 write_ctx_reg(ctx, CTX_GCSPR_EL0, read_gcspr_el0()); 1654 } 1655 #endif 1656 } 1657 1658 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1659 { 1660 write_spsr_el1(read_ctx_reg(ctx, CTX_SPSR_EL1)); 1661 write_elr_el1(read_ctx_reg(ctx, CTX_ELR_EL1)); 1662 1663 #if !ERRATA_SPECULATIVE_AT 1664 write_sctlr_el1(read_ctx_reg(ctx, CTX_SCTLR_EL1)); 1665 write_tcr_el1(read_ctx_reg(ctx, CTX_TCR_EL1)); 1666 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1667 1668 write_cpacr_el1(read_ctx_reg(ctx, CTX_CPACR_EL1)); 1669 write_csselr_el1(read_ctx_reg(ctx, CTX_CSSELR_EL1)); 1670 write_sp_el1(read_ctx_reg(ctx, CTX_SP_EL1)); 1671 write_esr_el1(read_ctx_reg(ctx, CTX_ESR_EL1)); 1672 write_ttbr0_el1(read_ctx_reg(ctx, CTX_TTBR0_EL1)); 1673 write_ttbr1_el1(read_ctx_reg(ctx, CTX_TTBR1_EL1)); 1674 write_mair_el1(read_ctx_reg(ctx, CTX_MAIR_EL1)); 1675 write_amair_el1(read_ctx_reg(ctx, CTX_AMAIR_EL1)); 1676 write_actlr_el1(read_ctx_reg(ctx, CTX_ACTLR_EL1)); 1677 write_tpidr_el1(read_ctx_reg(ctx, CTX_TPIDR_EL1)); 1678 write_tpidr_el0(read_ctx_reg(ctx, CTX_TPIDR_EL0)); 1679 write_tpidrro_el0(read_ctx_reg(ctx, CTX_TPIDRRO_EL0)); 1680 write_par_el1(read_ctx_reg(ctx, CTX_PAR_EL1)); 1681 write_far_el1(read_ctx_reg(ctx, CTX_FAR_EL1)); 1682 write_afsr0_el1(read_ctx_reg(ctx, CTX_AFSR0_EL1)); 1683 write_afsr1_el1(read_ctx_reg(ctx, CTX_AFSR1_EL1)); 1684 write_contextidr_el1(read_ctx_reg(ctx, CTX_CONTEXTIDR_EL1)); 1685 write_vbar_el1(read_ctx_reg(ctx, CTX_VBAR_EL1)); 1686 write_mdccint_el1(read_ctx_reg(ctx, CTX_MDCCINT_EL1)); 1687 write_mdscr_el1(read_ctx_reg(ctx, CTX_MDSCR_EL1)); 1688 1689 #if CTX_INCLUDE_AARCH32_REGS 1690 write_spsr_abt(read_ctx_reg(ctx, CTX_SPSR_ABT)); 1691 write_spsr_und(read_ctx_reg(ctx, CTX_SPSR_UND)); 1692 write_spsr_irq(read_ctx_reg(ctx, CTX_SPSR_IRQ)); 1693 write_spsr_fiq(read_ctx_reg(ctx, CTX_SPSR_FIQ)); 1694 write_dacr32_el2(read_ctx_reg(ctx, CTX_DACR32_EL2)); 1695 write_ifsr32_el2(read_ctx_reg(ctx, CTX_IFSR32_EL2)); 1696 #endif /* CTX_INCLUDE_AARCH32_REGS */ 1697 1698 #if NS_TIMER_SWITCH 1699 write_cntp_ctl_el0(read_ctx_reg(ctx, CTX_CNTP_CTL_EL0)); 1700 write_cntp_cval_el0(read_ctx_reg(ctx, CTX_CNTP_CVAL_EL0)); 1701 write_cntv_ctl_el0(read_ctx_reg(ctx, CTX_CNTV_CTL_EL0)); 1702 write_cntv_cval_el0(read_ctx_reg(ctx, CTX_CNTV_CVAL_EL0)); 1703 write_cntkctl_el1(read_ctx_reg(ctx, CTX_CNTKCTL_EL1)); 1704 #endif /* NS_TIMER_SWITCH */ 1705 1706 #if ENABLE_FEAT_MTE2 1707 write_tfsre0_el1(read_ctx_reg(ctx, CTX_TFSRE0_EL1)); 1708 write_tfsr_el1(read_ctx_reg(ctx, CTX_TFSR_EL1)); 1709 write_rgsr_el1(read_ctx_reg(ctx, CTX_RGSR_EL1)); 1710 write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1)); 1711 #endif /* ENABLE_FEAT_MTE2 */ 1712 1713 #if ENABLE_FEAT_RAS 1714 if (is_feat_ras_supported()) { 1715 write_disr_el1(read_ctx_reg(ctx, CTX_DISR_EL1)); 1716 } 1717 #endif 1718 1719 #if ENABLE_FEAT_S1PIE 1720 if (is_feat_s1pie_supported()) { 1721 write_pire0_el1(read_ctx_reg(ctx, CTX_PIRE0_EL1)); 1722 write_pir_el1(read_ctx_reg(ctx, CTX_PIR_EL1)); 1723 } 1724 #endif 1725 1726 #if ENABLE_FEAT_S1POE 1727 if (is_feat_s1poe_supported()) { 1728 write_por_el1(read_ctx_reg(ctx, CTX_POR_EL1)); 1729 } 1730 #endif 1731 1732 #if ENABLE_FEAT_S2POE 1733 if (is_feat_s2poe_supported()) { 1734 write_s2por_el1(read_ctx_reg(ctx, CTX_S2POR_EL1)); 1735 } 1736 #endif 1737 1738 #if ENABLE_FEAT_TCR2 1739 if (is_feat_tcr2_supported()) { 1740 write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1)); 1741 } 1742 #endif 1743 1744 #if ENABLE_TRF_FOR_NS 1745 if (is_feat_trf_supported()) { 1746 write_trfcr_el1(read_ctx_reg(ctx, CTX_TRFCR_EL1)); 1747 } 1748 #endif 1749 1750 #if ENABLE_FEAT_CSV2_2 1751 if (is_feat_csv2_2_supported()) { 1752 write_scxtnum_el0(read_ctx_reg(ctx, CTX_SCXTNUM_EL0)); 1753 write_scxtnum_el1(read_ctx_reg(ctx, CTX_SCXTNUM_EL1)); 1754 } 1755 #endif 1756 1757 #if ENABLE_FEAT_GCS 1758 if (is_feat_gcs_supported()) { 1759 write_gcscr_el1(read_ctx_reg(ctx, CTX_GCSCR_EL1)); 1760 write_gcscre0_el1(read_ctx_reg(ctx, CTX_GCSCRE0_EL1)); 1761 write_gcspr_el1(read_ctx_reg(ctx, CTX_GCSPR_EL1)); 1762 write_gcspr_el0(read_ctx_reg(ctx, CTX_GCSPR_EL0)); 1763 } 1764 #endif 1765 } 1766 1767 /******************************************************************************* 1768 * The next four functions are used by runtime services to save and restore 1769 * EL1 context on the 'cpu_context' structure for the specified security 1770 * state. 1771 ******************************************************************************/ 1772 void cm_el1_sysregs_context_save(uint32_t security_state) 1773 { 1774 cpu_context_t *ctx; 1775 1776 ctx = cm_get_context(security_state); 1777 assert(ctx != NULL); 1778 1779 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1780 1781 #if IMAGE_BL31 1782 if (security_state == SECURE) 1783 PUBLISH_EVENT(cm_exited_secure_world); 1784 else 1785 PUBLISH_EVENT(cm_exited_normal_world); 1786 #endif 1787 } 1788 1789 void cm_el1_sysregs_context_restore(uint32_t security_state) 1790 { 1791 cpu_context_t *ctx; 1792 1793 ctx = cm_get_context(security_state); 1794 assert(ctx != NULL); 1795 1796 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1797 1798 #if IMAGE_BL31 1799 if (security_state == SECURE) 1800 PUBLISH_EVENT(cm_entering_secure_world); 1801 else 1802 PUBLISH_EVENT(cm_entering_normal_world); 1803 #endif 1804 } 1805 1806 /******************************************************************************* 1807 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1808 * given security state with the given entrypoint 1809 ******************************************************************************/ 1810 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1811 { 1812 cpu_context_t *ctx; 1813 el3_state_t *state; 1814 1815 ctx = cm_get_context(security_state); 1816 assert(ctx != NULL); 1817 1818 /* Populate EL3 state so that ERET jumps to the correct entry */ 1819 state = get_el3state_ctx(ctx); 1820 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1821 } 1822 1823 /******************************************************************************* 1824 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1825 * pertaining to the given security state 1826 ******************************************************************************/ 1827 void cm_set_elr_spsr_el3(uint32_t security_state, 1828 uintptr_t entrypoint, uint32_t spsr) 1829 { 1830 cpu_context_t *ctx; 1831 el3_state_t *state; 1832 1833 ctx = cm_get_context(security_state); 1834 assert(ctx != NULL); 1835 1836 /* Populate EL3 state so that ERET jumps to the correct entry */ 1837 state = get_el3state_ctx(ctx); 1838 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1839 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1840 } 1841 1842 /******************************************************************************* 1843 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1844 * pertaining to the given security state using the value and bit position 1845 * specified in the parameters. It preserves all other bits. 1846 ******************************************************************************/ 1847 void cm_write_scr_el3_bit(uint32_t security_state, 1848 uint32_t bit_pos, 1849 uint32_t value) 1850 { 1851 cpu_context_t *ctx; 1852 el3_state_t *state; 1853 u_register_t scr_el3; 1854 1855 ctx = cm_get_context(security_state); 1856 assert(ctx != NULL); 1857 1858 /* Ensure that the bit position is a valid one */ 1859 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1860 1861 /* Ensure that the 'value' is only a bit wide */ 1862 assert(value <= 1U); 1863 1864 /* 1865 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1866 * and set it to its new value. 1867 */ 1868 state = get_el3state_ctx(ctx); 1869 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1870 scr_el3 &= ~(1UL << bit_pos); 1871 scr_el3 |= (u_register_t)value << bit_pos; 1872 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1873 } 1874 1875 /******************************************************************************* 1876 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1877 * given security state. 1878 ******************************************************************************/ 1879 u_register_t cm_get_scr_el3(uint32_t security_state) 1880 { 1881 cpu_context_t *ctx; 1882 el3_state_t *state; 1883 1884 ctx = cm_get_context(security_state); 1885 assert(ctx != NULL); 1886 1887 /* Populate EL3 state so that ERET jumps to the correct entry */ 1888 state = get_el3state_ctx(ctx); 1889 return read_ctx_reg(state, CTX_SCR_EL3); 1890 } 1891 1892 /******************************************************************************* 1893 * This function is used to program the context that's used for exception 1894 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1895 * the required security state 1896 ******************************************************************************/ 1897 void cm_set_next_eret_context(uint32_t security_state) 1898 { 1899 cpu_context_t *ctx; 1900 1901 ctx = cm_get_context(security_state); 1902 assert(ctx != NULL); 1903 1904 cm_set_next_context(ctx); 1905 } 1906