1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/extensions/twed.h> 26 #include <lib/utils.h> 27 28 29 /******************************************************************************* 30 * Context management library initialisation routine. This library is used by 31 * runtime services to share pointers to 'cpu_context' structures for the secure 32 * and non-secure states. Management of the structures and their associated 33 * memory is not done by the context management library e.g. the PSCI service 34 * manages the cpu context used for entry from and exit to the non-secure state. 35 * The Secure payload dispatcher service manages the context(s) corresponding to 36 * the secure state. It also uses this library to get access to the non-secure 37 * state cpu context pointers. 38 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 39 * which will used for programming an entry into a lower EL. The same context 40 * will used to save state upon exception entry from that EL. 41 ******************************************************************************/ 42 void __init cm_init(void) 43 { 44 /* 45 * The context management library has only global data to intialize, but 46 * that will be done when the BSS is zeroed out 47 */ 48 } 49 50 /******************************************************************************* 51 * The following function initializes the cpu_context 'ctx' for 52 * first use, and sets the initial entrypoint state as specified by the 53 * entry_point_info structure. 54 * 55 * The security state to initialize is determined by the SECURE attribute 56 * of the entry_point_info. 57 * 58 * The EE and ST attributes are used to configure the endianness and secure 59 * timer availability for the new execution context. 60 * 61 * To prepare the register state for entry call cm_prepare_el3_exit() and 62 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 63 * cm_e1_sysreg_context_restore(). 64 ******************************************************************************/ 65 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 66 { 67 unsigned int security_state; 68 u_register_t scr_el3; 69 el3_state_t *state; 70 gp_regs_t *gp_regs; 71 u_register_t sctlr_elx, actlr_elx; 72 73 assert(ctx != NULL); 74 75 security_state = GET_SECURITY_STATE(ep->h.attr); 76 77 /* Clear any residual register values from the context */ 78 zeromem(ctx, sizeof(*ctx)); 79 80 /* 81 * SCR_EL3 was initialised during reset sequence in macro 82 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 83 * affect the next EL. 84 * 85 * The following fields are initially set to zero and then updated to 86 * the required value depending on the state of the SPSR_EL3 and the 87 * Security state and entrypoint attributes of the next EL. 88 */ 89 scr_el3 = read_scr(); 90 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 91 SCR_ST_BIT | SCR_HCE_BIT); 92 /* 93 * SCR_NS: Set the security state of the next EL. 94 */ 95 if (security_state != SECURE) 96 scr_el3 |= SCR_NS_BIT; 97 /* 98 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 99 * Exception level as specified by SPSR. 100 */ 101 if (GET_RW(ep->spsr) == MODE_RW_64) 102 scr_el3 |= SCR_RW_BIT; 103 /* 104 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 105 * Secure timer registers to EL3, from AArch64 state only, if specified 106 * by the entrypoint attributes. 107 */ 108 if (EP_GET_ST(ep->h.attr) != 0U) 109 scr_el3 |= SCR_ST_BIT; 110 111 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 112 /* 113 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 114 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 115 */ 116 scr_el3 |= SCR_TERR_BIT; 117 #endif 118 119 #if !HANDLE_EA_EL3_FIRST 120 /* 121 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 122 * to EL3 when executing at a lower EL. When executing at EL3, External 123 * Aborts are taken to EL3. 124 */ 125 scr_el3 &= ~SCR_EA_BIT; 126 #endif 127 128 #if FAULT_INJECTION_SUPPORT 129 /* Enable fault injection from lower ELs */ 130 scr_el3 |= SCR_FIEN_BIT; 131 #endif 132 133 #if !CTX_INCLUDE_PAUTH_REGS 134 /* 135 * If the pointer authentication registers aren't saved during world 136 * switches the value of the registers can be leaked from the Secure to 137 * the Non-secure world. To prevent this, rather than enabling pointer 138 * authentication everywhere, we only enable it in the Non-secure world. 139 * 140 * If the Secure world wants to use pointer authentication, 141 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 142 */ 143 if (security_state == NON_SECURE) 144 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 145 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 146 147 /* 148 * Enable MTE support. Support is enabled unilaterally for the normal 149 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 150 * set. 151 */ 152 #if CTX_INCLUDE_MTE_REGS 153 assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX); 154 scr_el3 |= SCR_ATA_BIT; 155 #else 156 unsigned int mte = get_armv8_5_mte_support(); 157 if (mte == MTE_IMPLEMENTED_EL0) { 158 /* 159 * Can enable MTE across both worlds as no MTE registers are 160 * used 161 */ 162 scr_el3 |= SCR_ATA_BIT; 163 } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) { 164 /* 165 * Can only enable MTE in Non-Secure world without register 166 * saving 167 */ 168 scr_el3 |= SCR_ATA_BIT; 169 } 170 #endif 171 172 #ifdef IMAGE_BL31 173 /* 174 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 175 * indicated by the interrupt routing model for BL31. 176 */ 177 scr_el3 |= get_scr_el3_from_routing_model(security_state); 178 #endif 179 180 /* 181 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 182 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 183 * next mode is Hyp. 184 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 185 * same conditions as HVC instructions and when the processor supports 186 * ARMv8.6-FGT. 187 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 188 * CNTPOFF_EL2 register under the same conditions as HVC instructions 189 * and when the processor supports ECV. 190 */ 191 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 192 || ((GET_RW(ep->spsr) != MODE_RW_64) 193 && (GET_M32(ep->spsr) == MODE32_hyp))) { 194 scr_el3 |= SCR_HCE_BIT; 195 196 if (is_armv8_6_fgt_present()) { 197 scr_el3 |= SCR_FGTEN_BIT; 198 } 199 200 if (get_armv8_6_ecv_support() 201 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 202 scr_el3 |= SCR_ECVEN_BIT; 203 } 204 } 205 206 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 207 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { 208 if (GET_RW(ep->spsr) != MODE_RW_64) { 209 ERROR("S-EL2 can not be used in AArch32."); 210 panic(); 211 } 212 213 scr_el3 |= SCR_EEL2_BIT; 214 } 215 216 /* 217 * Initialise SCTLR_EL1 to the reset value corresponding to the target 218 * execution state setting all fields rather than relying of the hw. 219 * Some fields have architecturally UNKNOWN reset values and these are 220 * set to zero. 221 * 222 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 223 * 224 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 225 * required by PSCI specification) 226 */ 227 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 228 if (GET_RW(ep->spsr) == MODE_RW_64) 229 sctlr_elx |= SCTLR_EL1_RES1; 230 else { 231 /* 232 * If the target execution state is AArch32 then the following 233 * fields need to be set. 234 * 235 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 236 * instructions are not trapped to EL1. 237 * 238 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 239 * instructions are not trapped to EL1. 240 * 241 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 242 * CP15DMB, CP15DSB, and CP15ISB instructions. 243 */ 244 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 245 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 246 } 247 248 #if ERRATA_A75_764081 249 /* 250 * If workaround of errata 764081 for Cortex-A75 is used then set 251 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 252 */ 253 sctlr_elx |= SCTLR_IESB_BIT; 254 #endif 255 256 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 257 if (is_armv8_6_twed_present()) { 258 uint32_t delay = plat_arm_set_twedel_scr_el3(); 259 260 if (delay != TWED_DISABLED) { 261 /* Make sure delay value fits */ 262 assert((delay & ~SCR_TWEDEL_MASK) == 0U); 263 264 /* Set delay in SCR_EL3 */ 265 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 266 scr_el3 |= ((delay & SCR_TWEDEL_MASK) 267 << SCR_TWEDEL_SHIFT); 268 269 /* Enable WFE delay */ 270 scr_el3 |= SCR_TWEDEn_BIT; 271 } 272 } 273 274 /* 275 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 276 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 277 * are not part of the stored cpu_context. 278 */ 279 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 280 281 /* 282 * Base the context ACTLR_EL1 on the current value, as it is 283 * implementation defined. The context restore process will write 284 * the value from the context to the actual register and can cause 285 * problems for processor cores that don't expect certain bits to 286 * be zero. 287 */ 288 actlr_elx = read_actlr_el1(); 289 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 290 291 /* 292 * Populate EL3 state so that we've the right context 293 * before doing ERET 294 */ 295 state = get_el3state_ctx(ctx); 296 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 297 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 298 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 299 300 /* 301 * Store the X0-X7 value from the entrypoint into the context 302 * Use memcpy as we are in control of the layout of the structures 303 */ 304 gp_regs = get_gpregs_ctx(ctx); 305 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 306 } 307 308 /******************************************************************************* 309 * Enable architecture extensions on first entry to Non-secure world. 310 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 311 * it is zero. 312 ******************************************************************************/ 313 static void enable_extensions_nonsecure(bool el2_unused) 314 { 315 #if IMAGE_BL31 316 #if ENABLE_SPE_FOR_LOWER_ELS 317 spe_enable(el2_unused); 318 #endif 319 320 #if ENABLE_AMU 321 amu_enable(el2_unused); 322 #endif 323 324 #if ENABLE_SVE_FOR_NS 325 sve_enable(el2_unused); 326 #endif 327 328 #if ENABLE_MPAM_FOR_LOWER_ELS 329 mpam_enable(el2_unused); 330 #endif 331 #endif 332 } 333 334 /******************************************************************************* 335 * The following function initializes the cpu_context for a CPU specified by 336 * its `cpu_idx` for first use, and sets the initial entrypoint state as 337 * specified by the entry_point_info structure. 338 ******************************************************************************/ 339 void cm_init_context_by_index(unsigned int cpu_idx, 340 const entry_point_info_t *ep) 341 { 342 cpu_context_t *ctx; 343 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 344 cm_setup_context(ctx, ep); 345 } 346 347 /******************************************************************************* 348 * The following function initializes the cpu_context for the current CPU 349 * for first use, and sets the initial entrypoint state as specified by the 350 * entry_point_info structure. 351 ******************************************************************************/ 352 void cm_init_my_context(const entry_point_info_t *ep) 353 { 354 cpu_context_t *ctx; 355 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 356 cm_setup_context(ctx, ep); 357 } 358 359 /******************************************************************************* 360 * Prepare the CPU system registers for first entry into secure or normal world 361 * 362 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 363 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 364 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 365 * For all entries, the EL1 registers are initialized from the cpu_context 366 ******************************************************************************/ 367 void cm_prepare_el3_exit(uint32_t security_state) 368 { 369 u_register_t sctlr_elx, scr_el3, mdcr_el2; 370 cpu_context_t *ctx = cm_get_context(security_state); 371 bool el2_unused = false; 372 uint64_t hcr_el2 = 0U; 373 374 assert(ctx != NULL); 375 376 if (security_state == NON_SECURE) { 377 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 378 CTX_SCR_EL3); 379 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 380 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 381 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 382 CTX_SCTLR_EL1); 383 sctlr_elx &= SCTLR_EE_BIT; 384 sctlr_elx |= SCTLR_EL2_RES1; 385 #if ERRATA_A75_764081 386 /* 387 * If workaround of errata 764081 for Cortex-A75 is used 388 * then set SCTLR_EL2.IESB to enable Implicit Error 389 * Synchronization Barrier. 390 */ 391 sctlr_elx |= SCTLR_IESB_BIT; 392 #endif 393 write_sctlr_el2(sctlr_elx); 394 } else if (el_implemented(2) != EL_IMPL_NONE) { 395 el2_unused = true; 396 397 /* 398 * EL2 present but unused, need to disable safely. 399 * SCTLR_EL2 can be ignored in this case. 400 * 401 * Set EL2 register width appropriately: Set HCR_EL2 402 * field to match SCR_EL3.RW. 403 */ 404 if ((scr_el3 & SCR_RW_BIT) != 0U) 405 hcr_el2 |= HCR_RW_BIT; 406 407 /* 408 * For Armv8.3 pointer authentication feature, disable 409 * traps to EL2 when accessing key registers or using 410 * pointer authentication instructions from lower ELs. 411 */ 412 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 413 414 write_hcr_el2(hcr_el2); 415 416 /* 417 * Initialise CPTR_EL2 setting all fields rather than 418 * relying on the hw. All fields have architecturally 419 * UNKNOWN reset values. 420 * 421 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 422 * accesses to the CPACR_EL1 or CPACR from both 423 * Execution states do not trap to EL2. 424 * 425 * CPTR_EL2.TTA: Set to zero so that Non-secure System 426 * register accesses to the trace registers from both 427 * Execution states do not trap to EL2. 428 * 429 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 430 * to SIMD and floating-point functionality from both 431 * Execution states do not trap to EL2. 432 */ 433 write_cptr_el2(CPTR_EL2_RESET_VAL & 434 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 435 | CPTR_EL2_TFP_BIT)); 436 437 /* 438 * Initialise CNTHCTL_EL2. All fields are 439 * architecturally UNKNOWN on reset and are set to zero 440 * except for field(s) listed below. 441 * 442 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 443 * Hyp mode of Non-secure EL0 and EL1 accesses to the 444 * physical timer registers. 445 * 446 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 447 * Hyp mode of Non-secure EL0 and EL1 accesses to the 448 * physical counter registers. 449 */ 450 write_cnthctl_el2(CNTHCTL_RESET_VAL | 451 EL1PCEN_BIT | EL1PCTEN_BIT); 452 453 /* 454 * Initialise CNTVOFF_EL2 to zero as it resets to an 455 * architecturally UNKNOWN value. 456 */ 457 write_cntvoff_el2(0); 458 459 /* 460 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 461 * MPIDR_EL1 respectively. 462 */ 463 write_vpidr_el2(read_midr_el1()); 464 write_vmpidr_el2(read_mpidr_el1()); 465 466 /* 467 * Initialise VTTBR_EL2. All fields are architecturally 468 * UNKNOWN on reset. 469 * 470 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 471 * 2 address translation is disabled, cache maintenance 472 * operations depend on the VMID. 473 * 474 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 475 * translation is disabled. 476 */ 477 write_vttbr_el2(VTTBR_RESET_VAL & 478 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 479 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 480 481 /* 482 * Initialise MDCR_EL2, setting all fields rather than 483 * relying on hw. Some fields are architecturally 484 * UNKNOWN on reset. 485 * 486 * MDCR_EL2.HLP: Set to one so that event counter 487 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 488 * occurs on the increment that changes 489 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 490 * implemented. This bit is RES0 in versions of the 491 * architecture earlier than ARMv8.5, setting it to 1 492 * doesn't have any effect on them. 493 * 494 * MDCR_EL2.TTRF: Set to zero so that access to Trace 495 * Filter Control register TRFCR_EL1 at EL1 is not 496 * trapped to EL2. This bit is RES0 in versions of 497 * the architecture earlier than ARMv8.4. 498 * 499 * MDCR_EL2.HPMD: Set to one so that event counting is 500 * prohibited at EL2. This bit is RES0 in versions of 501 * the architecture earlier than ARMv8.1, setting it 502 * to 1 doesn't have any effect on them. 503 * 504 * MDCR_EL2.TPMS: Set to zero so that accesses to 505 * Statistical Profiling control registers from EL1 506 * do not trap to EL2. This bit is RES0 when SPE is 507 * not implemented. 508 * 509 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 510 * EL1 System register accesses to the Debug ROM 511 * registers are not trapped to EL2. 512 * 513 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 514 * System register accesses to the powerdown debug 515 * registers are not trapped to EL2. 516 * 517 * MDCR_EL2.TDA: Set to zero so that System register 518 * accesses to the debug registers do not trap to EL2. 519 * 520 * MDCR_EL2.TDE: Set to zero so that debug exceptions 521 * are not routed to EL2. 522 * 523 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 524 * Monitors. 525 * 526 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 527 * EL1 accesses to all Performance Monitors registers 528 * are not trapped to EL2. 529 * 530 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 531 * and EL1 accesses to the PMCR_EL0 or PMCR are not 532 * trapped to EL2. 533 * 534 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 535 * architecturally-defined reset value. 536 */ 537 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 538 MDCR_EL2_HPMD) | 539 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 540 >> PMCR_EL0_N_SHIFT)) & 541 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 542 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 543 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 544 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 545 MDCR_EL2_TPMCR_BIT); 546 547 write_mdcr_el2(mdcr_el2); 548 549 /* 550 * Initialise HSTR_EL2. All fields are architecturally 551 * UNKNOWN on reset. 552 * 553 * HSTR_EL2.T<n>: Set all these fields to zero so that 554 * Non-secure EL0 or EL1 accesses to System registers 555 * do not trap to EL2. 556 */ 557 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 558 /* 559 * Initialise CNTHP_CTL_EL2. All fields are 560 * architecturally UNKNOWN on reset. 561 * 562 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 563 * physical timer and prevent timer interrupts. 564 */ 565 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 566 ~(CNTHP_CTL_ENABLE_BIT)); 567 } 568 enable_extensions_nonsecure(el2_unused); 569 } 570 571 cm_el1_sysregs_context_restore(security_state); 572 cm_set_next_eret_context(security_state); 573 } 574 575 #if CTX_INCLUDE_EL2_REGS 576 /******************************************************************************* 577 * Save EL2 sysreg context 578 ******************************************************************************/ 579 void cm_el2_sysregs_context_save(uint32_t security_state) 580 { 581 u_register_t scr_el3 = read_scr(); 582 583 /* 584 * Always save the non-secure EL2 context, only save the 585 * S-EL2 context if S-EL2 is enabled. 586 */ 587 if ((security_state == NON_SECURE) || 588 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 589 cpu_context_t *ctx; 590 591 ctx = cm_get_context(security_state); 592 assert(ctx != NULL); 593 594 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 595 } 596 } 597 598 /******************************************************************************* 599 * Restore EL2 sysreg context 600 ******************************************************************************/ 601 void cm_el2_sysregs_context_restore(uint32_t security_state) 602 { 603 u_register_t scr_el3 = read_scr(); 604 605 /* 606 * Always restore the non-secure EL2 context, only restore the 607 * S-EL2 context if S-EL2 is enabled. 608 */ 609 if ((security_state == NON_SECURE) || 610 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 611 cpu_context_t *ctx; 612 613 ctx = cm_get_context(security_state); 614 assert(ctx != NULL); 615 616 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 617 } 618 } 619 #endif /* CTX_INCLUDE_EL2_REGS */ 620 621 /******************************************************************************* 622 * The next four functions are used by runtime services to save and restore 623 * EL1 context on the 'cpu_context' structure for the specified security 624 * state. 625 ******************************************************************************/ 626 void cm_el1_sysregs_context_save(uint32_t security_state) 627 { 628 cpu_context_t *ctx; 629 630 ctx = cm_get_context(security_state); 631 assert(ctx != NULL); 632 633 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 634 635 #if IMAGE_BL31 636 if (security_state == SECURE) 637 PUBLISH_EVENT(cm_exited_secure_world); 638 else 639 PUBLISH_EVENT(cm_exited_normal_world); 640 #endif 641 } 642 643 void cm_el1_sysregs_context_restore(uint32_t security_state) 644 { 645 cpu_context_t *ctx; 646 647 ctx = cm_get_context(security_state); 648 assert(ctx != NULL); 649 650 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 651 652 #if IMAGE_BL31 653 if (security_state == SECURE) 654 PUBLISH_EVENT(cm_entering_secure_world); 655 else 656 PUBLISH_EVENT(cm_entering_normal_world); 657 #endif 658 } 659 660 /******************************************************************************* 661 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 662 * given security state with the given entrypoint 663 ******************************************************************************/ 664 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 665 { 666 cpu_context_t *ctx; 667 el3_state_t *state; 668 669 ctx = cm_get_context(security_state); 670 assert(ctx != NULL); 671 672 /* Populate EL3 state so that ERET jumps to the correct entry */ 673 state = get_el3state_ctx(ctx); 674 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 675 } 676 677 /******************************************************************************* 678 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 679 * pertaining to the given security state 680 ******************************************************************************/ 681 void cm_set_elr_spsr_el3(uint32_t security_state, 682 uintptr_t entrypoint, uint32_t spsr) 683 { 684 cpu_context_t *ctx; 685 el3_state_t *state; 686 687 ctx = cm_get_context(security_state); 688 assert(ctx != NULL); 689 690 /* Populate EL3 state so that ERET jumps to the correct entry */ 691 state = get_el3state_ctx(ctx); 692 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 693 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 694 } 695 696 /******************************************************************************* 697 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 698 * pertaining to the given security state using the value and bit position 699 * specified in the parameters. It preserves all other bits. 700 ******************************************************************************/ 701 void cm_write_scr_el3_bit(uint32_t security_state, 702 uint32_t bit_pos, 703 uint32_t value) 704 { 705 cpu_context_t *ctx; 706 el3_state_t *state; 707 u_register_t scr_el3; 708 709 ctx = cm_get_context(security_state); 710 assert(ctx != NULL); 711 712 /* Ensure that the bit position is a valid one */ 713 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 714 715 /* Ensure that the 'value' is only a bit wide */ 716 assert(value <= 1U); 717 718 /* 719 * Get the SCR_EL3 value from the cpu context, clear the desired bit 720 * and set it to its new value. 721 */ 722 state = get_el3state_ctx(ctx); 723 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 724 scr_el3 &= ~(1U << bit_pos); 725 scr_el3 |= (u_register_t)value << bit_pos; 726 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 727 } 728 729 /******************************************************************************* 730 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 731 * given security state. 732 ******************************************************************************/ 733 u_register_t cm_get_scr_el3(uint32_t security_state) 734 { 735 cpu_context_t *ctx; 736 el3_state_t *state; 737 738 ctx = cm_get_context(security_state); 739 assert(ctx != NULL); 740 741 /* Populate EL3 state so that ERET jumps to the correct entry */ 742 state = get_el3state_ctx(ctx); 743 return read_ctx_reg(state, CTX_SCR_EL3); 744 } 745 746 /******************************************************************************* 747 * This function is used to program the context that's used for exception 748 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 749 * the required security state 750 ******************************************************************************/ 751 void cm_set_next_eret_context(uint32_t security_state) 752 { 753 cpu_context_t *ctx; 754 755 ctx = cm_get_context(security_state); 756 assert(ctx != NULL); 757 758 cm_set_next_context(ctx); 759 } 760