1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/mpam.h> 32 #include <lib/extensions/pmuv3.h> 33 #include <lib/extensions/sme.h> 34 #include <lib/extensions/spe.h> 35 #include <lib/extensions/sve.h> 36 #include <lib/extensions/sysreg128.h> 37 #include <lib/extensions/sys_reg_trace.h> 38 #include <lib/extensions/tcr2.h> 39 #include <lib/extensions/trbe.h> 40 #include <lib/extensions/trf.h> 41 #include <lib/utils.h> 42 43 #if ENABLE_FEAT_TWED 44 /* Make sure delay value fits within the range(0-15) */ 45 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 46 #endif /* ENABLE_FEAT_TWED */ 47 48 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 49 static bool has_secure_perworld_init; 50 51 static void manage_extensions_common(cpu_context_t *ctx); 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 static void manage_extensions_secure_per_world(void); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 153 /** 154 * manage_extensions_secure_per_world api has to be executed once, 155 * as the registers getting initialised, maintain constant value across 156 * all the cpus for the secure world. 157 * Henceforth, this check ensures that the registers are initialised once 158 * and avoids re-initialization from multiple cores. 159 */ 160 if (!has_secure_perworld_init) { 161 manage_extensions_secure_per_world(); 162 } 163 } 164 165 #if ENABLE_RME 166 /****************************************************************************** 167 * This function performs initializations that are specific to REALM state 168 * and updates the cpu context specified by 'ctx'. 169 *****************************************************************************/ 170 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 171 { 172 u_register_t scr_el3; 173 el3_state_t *state; 174 175 state = get_el3state_ctx(ctx); 176 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 177 178 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 179 180 /* CSV2 version 2 and above */ 181 if (is_feat_csv2_2_supported()) { 182 /* Enable access to the SCXTNUM_ELx registers. */ 183 scr_el3 |= SCR_EnSCXT_BIT; 184 } 185 186 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 187 } 188 #endif /* ENABLE_RME */ 189 190 /****************************************************************************** 191 * This function performs initializations that are specific to NON-SECURE state 192 * and updates the cpu context specified by 'ctx'. 193 *****************************************************************************/ 194 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 195 { 196 u_register_t scr_el3; 197 el3_state_t *state; 198 199 state = get_el3state_ctx(ctx); 200 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 201 202 /* SCR_NS: Set the NS bit */ 203 scr_el3 |= SCR_NS_BIT; 204 205 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 206 if (is_feat_mte2_supported()) { 207 scr_el3 |= SCR_ATA_BIT; 208 } 209 210 #if !CTX_INCLUDE_PAUTH_REGS 211 /* 212 * Pointer Authentication feature, if present, is always enabled by default 213 * for Non secure lower exception levels. We do not have an explicit 214 * flag to set it. 215 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 216 * exception levels of secure and realm worlds. 217 * 218 * To prevent the leakage between the worlds during world switch, 219 * we enable it only for the non-secure world. 220 * 221 * If the Secure/realm world wants to use pointer authentication, 222 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 223 * it will be enabled globally for all the contexts. 224 * 225 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 226 * other than EL3 227 * 228 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 229 * than EL3 230 */ 231 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 232 233 #endif /* CTX_INCLUDE_PAUTH_REGS */ 234 235 #if HANDLE_EA_EL3_FIRST_NS 236 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 237 scr_el3 |= SCR_EA_BIT; 238 #endif 239 240 #if RAS_TRAP_NS_ERR_REC_ACCESS 241 /* 242 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 243 * and RAS ERX registers from EL1 and EL2(from any security state) 244 * are trapped to EL3. 245 * Set here to trap only for NS EL1/EL2 246 * 247 */ 248 scr_el3 |= SCR_TERR_BIT; 249 #endif 250 251 /* CSV2 version 2 and above */ 252 if (is_feat_csv2_2_supported()) { 253 /* Enable access to the SCXTNUM_ELx registers. */ 254 scr_el3 |= SCR_EnSCXT_BIT; 255 } 256 257 #ifdef IMAGE_BL31 258 /* 259 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 260 * indicated by the interrupt routing model for BL31. 261 */ 262 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 263 #endif 264 265 if (is_feat_the_supported()) { 266 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 267 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 268 */ 269 scr_el3 |= SCR_RCWMASKEn_BIT; 270 } 271 272 if (is_feat_sctlr2_supported()) { 273 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 274 * SCTLR2_ELx registers. 275 */ 276 scr_el3 |= SCR_SCTLR2En_BIT; 277 } 278 279 if (is_feat_d128_supported()) { 280 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 281 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 282 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 283 */ 284 scr_el3 |= SCR_D128En_BIT; 285 } 286 287 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 288 289 /* Initialize EL2 context registers */ 290 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 291 292 /* 293 * Initialize SCTLR_EL2 context register with reset value. 294 */ 295 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 296 297 if (is_feat_hcx_supported()) { 298 /* 299 * Initialize register HCRX_EL2 with its init value. 300 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 301 * chance that this can lead to unexpected behavior in lower 302 * ELs that have not been updated since the introduction of 303 * this feature if not properly initialized, especially when 304 * it comes to those bits that enable/disable traps. 305 */ 306 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 307 HCRX_EL2_INIT_VAL); 308 } 309 310 if (is_feat_fgt_supported()) { 311 /* 312 * Initialize HFG*_EL2 registers with a default value so legacy 313 * systems unaware of FEAT_FGT do not get trapped due to their lack 314 * of initialization for this feature. 315 */ 316 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 317 HFGITR_EL2_INIT_VAL); 318 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 319 HFGRTR_EL2_INIT_VAL); 320 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 321 HFGWTR_EL2_INIT_VAL); 322 } 323 #else 324 /* Initialize EL1 context registers */ 325 setup_el1_context(ctx, ep); 326 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 327 328 manage_extensions_nonsecure(ctx); 329 } 330 331 /******************************************************************************* 332 * The following function performs initialization of the cpu_context 'ctx' 333 * for first use that is common to all security states, and sets the 334 * initial entrypoint state as specified by the entry_point_info structure. 335 * 336 * The EE and ST attributes are used to configure the endianness and secure 337 * timer availability for the new execution context. 338 ******************************************************************************/ 339 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 340 { 341 u_register_t scr_el3; 342 u_register_t mdcr_el3; 343 el3_state_t *state; 344 gp_regs_t *gp_regs; 345 346 state = get_el3state_ctx(ctx); 347 348 /* Clear any residual register values from the context */ 349 zeromem(ctx, sizeof(*ctx)); 350 351 /* 352 * The lower-EL context is zeroed so that no stale values leak to a world. 353 * It is assumed that an all-zero lower-EL context is good enough for it 354 * to boot correctly. However, there are very few registers where this 355 * is not true and some values need to be recreated. 356 */ 357 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 358 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 359 360 /* 361 * These bits are set in the gicv3 driver. Losing them (especially the 362 * SRE bit) is problematic for all worlds. Henceforth recreate them. 363 */ 364 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 365 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 366 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 367 368 /* 369 * The actlr_el2 register can be initialized in platform's reset handler 370 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 371 */ 372 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 373 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 374 375 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 376 scr_el3 = SCR_RESET_VAL; 377 378 /* 379 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 380 * EL2, EL1 and EL0 are not trapped to EL3. 381 * 382 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 383 * EL2, EL1 and EL0 are not trapped to EL3. 384 * 385 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 386 * both Security states and both Execution states. 387 * 388 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 389 * Non-secure memory. 390 */ 391 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 392 393 scr_el3 |= SCR_SIF_BIT; 394 395 /* 396 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 397 * Exception level as specified by SPSR. 398 */ 399 if (GET_RW(ep->spsr) == MODE_RW_64) { 400 scr_el3 |= SCR_RW_BIT; 401 } 402 403 /* 404 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 405 * Secure timer registers to EL3, from AArch64 state only, if specified 406 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 407 * bit always behaves as 1 (i.e. secure physical timer register access 408 * is not trapped) 409 */ 410 if (EP_GET_ST(ep->h.attr) != 0U) { 411 scr_el3 |= SCR_ST_BIT; 412 } 413 414 /* 415 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 416 * SCR_EL3.HXEn. 417 */ 418 if (is_feat_hcx_supported()) { 419 scr_el3 |= SCR_HXEn_BIT; 420 } 421 422 /* 423 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 424 * registers are trapped to EL3. 425 */ 426 #if ENABLE_FEAT_RNG_TRAP 427 scr_el3 |= SCR_TRNDR_BIT; 428 #endif 429 430 #if FAULT_INJECTION_SUPPORT 431 /* Enable fault injection from lower ELs */ 432 scr_el3 |= SCR_FIEN_BIT; 433 #endif 434 435 #if CTX_INCLUDE_PAUTH_REGS 436 /* 437 * Enable Pointer Authentication globally for all the worlds. 438 * 439 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 440 * other than EL3 441 * 442 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 443 * than EL3 444 */ 445 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 446 #endif /* CTX_INCLUDE_PAUTH_REGS */ 447 448 /* 449 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 450 */ 451 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 452 scr_el3 |= SCR_TCR2EN_BIT; 453 } 454 455 /* 456 * SCR_EL3.PIEN: Enable permission indirection and overlay 457 * registers for AArch64 if present. 458 */ 459 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 460 scr_el3 |= SCR_PIEN_BIT; 461 } 462 463 /* 464 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 465 */ 466 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 467 scr_el3 |= SCR_GCSEn_BIT; 468 } 469 470 /* 471 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 472 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 473 * next mode is Hyp. 474 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 475 * same conditions as HVC instructions and when the processor supports 476 * ARMv8.6-FGT. 477 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 478 * CNTPOFF_EL2 register under the same conditions as HVC instructions 479 * and when the processor supports ECV. 480 */ 481 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 482 || ((GET_RW(ep->spsr) != MODE_RW_64) 483 && (GET_M32(ep->spsr) == MODE32_hyp))) { 484 scr_el3 |= SCR_HCE_BIT; 485 486 if (is_feat_fgt_supported()) { 487 scr_el3 |= SCR_FGTEN_BIT; 488 } 489 490 if (is_feat_ecv_supported()) { 491 scr_el3 |= SCR_ECVEN_BIT; 492 } 493 } 494 495 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 496 if (is_feat_twed_supported()) { 497 /* Set delay in SCR_EL3 */ 498 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 499 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 500 << SCR_TWEDEL_SHIFT); 501 502 /* Enable WFE delay */ 503 scr_el3 |= SCR_TWEDEn_BIT; 504 } 505 506 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 507 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 508 if (is_feat_sel2_supported()) { 509 scr_el3 |= SCR_EEL2_BIT; 510 } 511 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 512 513 /* 514 * Populate EL3 state so that we've the right context 515 * before doing ERET 516 */ 517 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 518 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 519 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 520 521 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 522 mdcr_el3 = MDCR_EL3_RESET_VAL; 523 524 /* --------------------------------------------------------------------- 525 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 526 * Some fields are architecturally UNKNOWN on reset. 527 * 528 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 529 * Debug exceptions, other than Breakpoint Instruction exceptions, are 530 * disabled from all ELs in Secure state. 531 * 532 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 533 * privileged debug from S-EL1. 534 * 535 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 536 * access to the powerdown debug registers do not trap to EL3. 537 * 538 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 539 * debug registers, other than those registers that are controlled by 540 * MDCR_EL3.TDOSA. 541 */ 542 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 543 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 544 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 545 546 /* 547 * Configure MDCR_EL3 register as applicable for each world 548 * (NS/Secure/Realm) context. 549 */ 550 manage_extensions_common(ctx); 551 552 /* 553 * Store the X0-X7 value from the entrypoint into the context 554 * Use memcpy as we are in control of the layout of the structures 555 */ 556 gp_regs = get_gpregs_ctx(ctx); 557 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 558 } 559 560 /******************************************************************************* 561 * Context management library initialization routine. This library is used by 562 * runtime services to share pointers to 'cpu_context' structures for secure 563 * non-secure and realm states. Management of the structures and their associated 564 * memory is not done by the context management library e.g. the PSCI service 565 * manages the cpu context used for entry from and exit to the non-secure state. 566 * The Secure payload dispatcher service manages the context(s) corresponding to 567 * the secure state. It also uses this library to get access to the non-secure 568 * state cpu context pointers. 569 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 570 * which will be used for programming an entry into a lower EL. The same context 571 * will be used to save state upon exception entry from that EL. 572 ******************************************************************************/ 573 void __init cm_init(void) 574 { 575 /* 576 * The context management library has only global data to initialize, but 577 * that will be done when the BSS is zeroed out. 578 */ 579 } 580 581 /******************************************************************************* 582 * This is the high-level function used to initialize the cpu_context 'ctx' for 583 * first use. It performs initializations that are common to all security states 584 * and initializations specific to the security state specified in 'ep' 585 ******************************************************************************/ 586 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 587 { 588 unsigned int security_state; 589 590 assert(ctx != NULL); 591 592 /* 593 * Perform initializations that are common 594 * to all security states 595 */ 596 setup_context_common(ctx, ep); 597 598 security_state = GET_SECURITY_STATE(ep->h.attr); 599 600 /* Perform security state specific initializations */ 601 switch (security_state) { 602 case SECURE: 603 setup_secure_context(ctx, ep); 604 break; 605 #if ENABLE_RME 606 case REALM: 607 setup_realm_context(ctx, ep); 608 break; 609 #endif 610 case NON_SECURE: 611 setup_ns_context(ctx, ep); 612 break; 613 default: 614 ERROR("Invalid security state\n"); 615 panic(); 616 break; 617 } 618 } 619 620 /******************************************************************************* 621 * Enable architecture extensions for EL3 execution. This function only updates 622 * registers in-place which are expected to either never change or be 623 * overwritten by el3_exit. 624 ******************************************************************************/ 625 #if IMAGE_BL31 626 void cm_manage_extensions_el3(void) 627 { 628 if (is_feat_amu_supported()) { 629 amu_init_el3(); 630 } 631 632 if (is_feat_sme_supported()) { 633 sme_init_el3(); 634 } 635 636 pmuv3_init_el3(); 637 } 638 #endif /* IMAGE_BL31 */ 639 640 /****************************************************************************** 641 * Function to initialise the registers with the RESET values in the context 642 * memory, which are maintained per world. 643 ******************************************************************************/ 644 #if IMAGE_BL31 645 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 646 { 647 /* 648 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 649 * 650 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 651 * by Advanced SIMD, floating-point or SVE instructions (if 652 * implemented) do not trap to EL3. 653 * 654 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 655 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 656 */ 657 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 658 659 per_world_ctx->ctx_cptr_el3 = cptr_el3; 660 661 /* 662 * Initialize MPAM3_EL3 to its default reset value 663 * 664 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 665 * all lower ELn MPAM3_EL3 register access to, trap to EL3 666 */ 667 668 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 669 } 670 #endif /* IMAGE_BL31 */ 671 672 /******************************************************************************* 673 * Initialise per_world_context for Non-Secure world. 674 * This function enables the architecture extensions, which have same value 675 * across the cores for the non-secure world. 676 ******************************************************************************/ 677 #if IMAGE_BL31 678 void manage_extensions_nonsecure_per_world(void) 679 { 680 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 681 682 if (is_feat_sme_supported()) { 683 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 684 } 685 686 if (is_feat_sve_supported()) { 687 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 688 } 689 690 if (is_feat_amu_supported()) { 691 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 692 } 693 694 if (is_feat_sys_reg_trace_supported()) { 695 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 696 } 697 698 if (is_feat_mpam_supported()) { 699 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 700 } 701 } 702 #endif /* IMAGE_BL31 */ 703 704 /******************************************************************************* 705 * Initialise per_world_context for Secure world. 706 * This function enables the architecture extensions, which have same value 707 * across the cores for the secure world. 708 ******************************************************************************/ 709 static void manage_extensions_secure_per_world(void) 710 { 711 #if IMAGE_BL31 712 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 713 714 if (is_feat_sme_supported()) { 715 716 if (ENABLE_SME_FOR_SWD) { 717 /* 718 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 719 * SME, SVE, and FPU/SIMD context properly managed. 720 */ 721 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 722 } else { 723 /* 724 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 725 * world can safely use the associated registers. 726 */ 727 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 728 } 729 } 730 if (is_feat_sve_supported()) { 731 if (ENABLE_SVE_FOR_SWD) { 732 /* 733 * Enable SVE and FPU in secure context, SPM must ensure 734 * that the SVE and FPU register contexts are properly managed. 735 */ 736 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 737 } else { 738 /* 739 * Disable SVE and FPU in secure context so non-secure world 740 * can safely use them. 741 */ 742 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 743 } 744 } 745 746 /* NS can access this but Secure shouldn't */ 747 if (is_feat_sys_reg_trace_supported()) { 748 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 749 } 750 751 has_secure_perworld_init = true; 752 #endif /* IMAGE_BL31 */ 753 } 754 755 /******************************************************************************* 756 * Enable architecture extensions on first entry to Non-secure world only 757 * and disable for secure world. 758 * 759 * NOTE: Arch features which have been provided with the capability of getting 760 * enabled only for non-secure world and being disabled for secure world are 761 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 762 ******************************************************************************/ 763 static void manage_extensions_common(cpu_context_t *ctx) 764 { 765 #if IMAGE_BL31 766 if (is_feat_spe_supported()) { 767 /* 768 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 769 */ 770 spe_enable(ctx); 771 } 772 773 if (is_feat_trbe_supported()) { 774 /* 775 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 776 * Realm state. 777 */ 778 trbe_enable(ctx); 779 } 780 781 if (is_feat_trf_supported()) { 782 /* 783 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 784 */ 785 trf_enable(ctx); 786 } 787 #endif /* IMAGE_BL31 */ 788 } 789 790 /******************************************************************************* 791 * Enable architecture extensions on first entry to Non-secure world. 792 ******************************************************************************/ 793 static void manage_extensions_nonsecure(cpu_context_t *ctx) 794 { 795 #if IMAGE_BL31 796 if (is_feat_amu_supported()) { 797 amu_enable(ctx); 798 } 799 800 if (is_feat_sme_supported()) { 801 sme_enable(ctx); 802 } 803 804 if (is_feat_fgt2_supported()) { 805 fgt2_enable(ctx); 806 } 807 808 if (is_feat_debugv8p9_supported()) { 809 debugv8p9_extended_bp_wp_enable(ctx); 810 } 811 812 if (is_feat_brbe_supported()) { 813 brbe_enable(ctx); 814 } 815 816 pmuv3_enable(ctx); 817 #endif /* IMAGE_BL31 */ 818 } 819 820 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 821 static __unused void enable_pauth_el2(void) 822 { 823 u_register_t hcr_el2 = read_hcr_el2(); 824 /* 825 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 826 * accessing key registers or using pointer authentication instructions 827 * from lower ELs. 828 */ 829 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 830 831 write_hcr_el2(hcr_el2); 832 } 833 834 #if INIT_UNUSED_NS_EL2 835 /******************************************************************************* 836 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 837 * world when EL2 is empty and unused. 838 ******************************************************************************/ 839 static void manage_extensions_nonsecure_el2_unused(void) 840 { 841 #if IMAGE_BL31 842 if (is_feat_spe_supported()) { 843 spe_init_el2_unused(); 844 } 845 846 if (is_feat_amu_supported()) { 847 amu_init_el2_unused(); 848 } 849 850 if (is_feat_mpam_supported()) { 851 mpam_init_el2_unused(); 852 } 853 854 if (is_feat_trbe_supported()) { 855 trbe_init_el2_unused(); 856 } 857 858 if (is_feat_sys_reg_trace_supported()) { 859 sys_reg_trace_init_el2_unused(); 860 } 861 862 if (is_feat_trf_supported()) { 863 trf_init_el2_unused(); 864 } 865 866 pmuv3_init_el2_unused(); 867 868 if (is_feat_sve_supported()) { 869 sve_init_el2_unused(); 870 } 871 872 if (is_feat_sme_supported()) { 873 sme_init_el2_unused(); 874 } 875 876 #if ENABLE_PAUTH 877 enable_pauth_el2(); 878 #endif /* ENABLE_PAUTH */ 879 #endif /* IMAGE_BL31 */ 880 } 881 #endif /* INIT_UNUSED_NS_EL2 */ 882 883 /******************************************************************************* 884 * Enable architecture extensions on first entry to Secure world. 885 ******************************************************************************/ 886 static void manage_extensions_secure(cpu_context_t *ctx) 887 { 888 #if IMAGE_BL31 889 if (is_feat_sme_supported()) { 890 if (ENABLE_SME_FOR_SWD) { 891 /* 892 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 893 * must ensure SME, SVE, and FPU/SIMD context properly managed. 894 */ 895 sme_init_el3(); 896 sme_enable(ctx); 897 } else { 898 /* 899 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 900 * world can safely use the associated registers. 901 */ 902 sme_disable(ctx); 903 } 904 } 905 #endif /* IMAGE_BL31 */ 906 } 907 908 #if !IMAGE_BL1 909 /******************************************************************************* 910 * The following function initializes the cpu_context for a CPU specified by 911 * its `cpu_idx` for first use, and sets the initial entrypoint state as 912 * specified by the entry_point_info structure. 913 ******************************************************************************/ 914 void cm_init_context_by_index(unsigned int cpu_idx, 915 const entry_point_info_t *ep) 916 { 917 cpu_context_t *ctx; 918 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 919 cm_setup_context(ctx, ep); 920 } 921 #endif /* !IMAGE_BL1 */ 922 923 /******************************************************************************* 924 * The following function initializes the cpu_context for the current CPU 925 * for first use, and sets the initial entrypoint state as specified by the 926 * entry_point_info structure. 927 ******************************************************************************/ 928 void cm_init_my_context(const entry_point_info_t *ep) 929 { 930 cpu_context_t *ctx; 931 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 932 cm_setup_context(ctx, ep); 933 } 934 935 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 936 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 937 { 938 #if INIT_UNUSED_NS_EL2 939 u_register_t hcr_el2 = HCR_RESET_VAL; 940 u_register_t mdcr_el2; 941 u_register_t scr_el3; 942 943 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 944 945 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 946 if ((scr_el3 & SCR_RW_BIT) != 0U) { 947 hcr_el2 |= HCR_RW_BIT; 948 } 949 950 write_hcr_el2(hcr_el2); 951 952 /* 953 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 954 * All fields have architecturally UNKNOWN reset values. 955 */ 956 write_cptr_el2(CPTR_EL2_RESET_VAL); 957 958 /* 959 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 960 * reset and are set to zero except for field(s) listed below. 961 * 962 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 963 * Non-secure EL0 and EL1 accesses to the physical timer registers. 964 * 965 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 966 * Non-secure EL0 and EL1 accesses to the physical counter registers. 967 */ 968 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 969 970 /* 971 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 972 * UNKNOWN value. 973 */ 974 write_cntvoff_el2(0); 975 976 /* 977 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 978 * respectively. 979 */ 980 write_vpidr_el2(read_midr_el1()); 981 write_vmpidr_el2(read_mpidr_el1()); 982 983 /* 984 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 985 * 986 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 987 * translation is disabled, cache maintenance operations depend on the 988 * VMID. 989 * 990 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 991 * disabled. 992 */ 993 write_vttbr_el2(VTTBR_RESET_VAL & 994 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 995 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 996 997 /* 998 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 999 * Some fields are architecturally UNKNOWN on reset. 1000 * 1001 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1002 * register accesses to the Debug ROM registers are not trapped to EL2. 1003 * 1004 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1005 * accesses to the powerdown debug registers are not trapped to EL2. 1006 * 1007 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1008 * debug registers do not trap to EL2. 1009 * 1010 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1011 * EL2. 1012 */ 1013 mdcr_el2 = MDCR_EL2_RESET_VAL & 1014 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1015 MDCR_EL2_TDE_BIT); 1016 1017 write_mdcr_el2(mdcr_el2); 1018 1019 /* 1020 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1021 * 1022 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1023 * EL1 accesses to System registers do not trap to EL2. 1024 */ 1025 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1026 1027 /* 1028 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1029 * reset. 1030 * 1031 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1032 * and prevent timer interrupts. 1033 */ 1034 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1035 1036 manage_extensions_nonsecure_el2_unused(); 1037 #endif /* INIT_UNUSED_NS_EL2 */ 1038 } 1039 1040 /******************************************************************************* 1041 * Prepare the CPU system registers for first entry into realm, secure, or 1042 * normal world. 1043 * 1044 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1045 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1046 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1047 * For all entries, the EL1 registers are initialized from the cpu_context 1048 ******************************************************************************/ 1049 void cm_prepare_el3_exit(uint32_t security_state) 1050 { 1051 u_register_t sctlr_el2, scr_el3; 1052 cpu_context_t *ctx = cm_get_context(security_state); 1053 1054 assert(ctx != NULL); 1055 1056 if (security_state == NON_SECURE) { 1057 uint64_t el2_implemented = el_implemented(2); 1058 1059 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1060 CTX_SCR_EL3); 1061 1062 if (el2_implemented != EL_IMPL_NONE) { 1063 1064 /* 1065 * If context is not being used for EL2, initialize 1066 * HCRX_EL2 with its init value here. 1067 */ 1068 if (is_feat_hcx_supported()) { 1069 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1070 } 1071 1072 /* 1073 * Initialize Fine-grained trap registers introduced 1074 * by FEAT_FGT so all traps are initially disabled when 1075 * switching to EL2 or a lower EL, preventing undesired 1076 * behavior. 1077 */ 1078 if (is_feat_fgt_supported()) { 1079 /* 1080 * Initialize HFG*_EL2 registers with a default 1081 * value so legacy systems unaware of FEAT_FGT 1082 * do not get trapped due to their lack of 1083 * initialization for this feature. 1084 */ 1085 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1086 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1087 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1088 } 1089 1090 /* Condition to ensure EL2 is being used. */ 1091 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1092 /* Initialize SCTLR_EL2 register with reset value. */ 1093 sctlr_el2 = SCTLR_EL2_RES1; 1094 1095 /* 1096 * If workaround of errata 764081 for Cortex-A75 1097 * is used then set SCTLR_EL2.IESB to enable 1098 * Implicit Error Synchronization Barrier. 1099 */ 1100 if (errata_a75_764081_applies()) { 1101 sctlr_el2 |= SCTLR_IESB_BIT; 1102 } 1103 1104 write_sctlr_el2(sctlr_el2); 1105 } else { 1106 /* 1107 * (scr_el3 & SCR_HCE_BIT==0) 1108 * EL2 implemented but unused. 1109 */ 1110 init_nonsecure_el2_unused(ctx); 1111 } 1112 } 1113 } 1114 #if (!CTX_INCLUDE_EL2_REGS) 1115 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1116 cm_el1_sysregs_context_restore(security_state); 1117 #endif 1118 cm_set_next_eret_context(security_state); 1119 } 1120 1121 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1122 1123 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1124 { 1125 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1126 if (is_feat_amu_supported()) { 1127 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1128 } 1129 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1130 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1131 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1132 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1133 } 1134 1135 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1136 { 1137 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1138 if (is_feat_amu_supported()) { 1139 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1140 } 1141 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1142 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1143 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1144 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1145 } 1146 1147 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1148 { 1149 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1150 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1151 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1152 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1153 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1154 } 1155 1156 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1157 { 1158 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1159 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1160 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1161 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1162 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1163 } 1164 1165 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1166 { 1167 u_register_t mpam_idr = read_mpamidr_el1(); 1168 1169 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1170 1171 /* 1172 * The context registers that we intend to save would be part of the 1173 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1174 */ 1175 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1176 return; 1177 } 1178 1179 /* 1180 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1181 * MPAMIDR_HAS_HCR_BIT == 1. 1182 */ 1183 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1184 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1185 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1186 1187 /* 1188 * The number of MPAMVPM registers is implementation defined, their 1189 * number is stored in the MPAMIDR_EL1 register. 1190 */ 1191 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1192 case 7: 1193 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1194 __fallthrough; 1195 case 6: 1196 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1197 __fallthrough; 1198 case 5: 1199 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1200 __fallthrough; 1201 case 4: 1202 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1203 __fallthrough; 1204 case 3: 1205 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1206 __fallthrough; 1207 case 2: 1208 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1209 __fallthrough; 1210 case 1: 1211 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1212 break; 1213 } 1214 } 1215 1216 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1217 { 1218 u_register_t mpam_idr = read_mpamidr_el1(); 1219 1220 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1221 1222 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1223 return; 1224 } 1225 1226 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1227 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1228 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1229 1230 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1231 case 7: 1232 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1233 __fallthrough; 1234 case 6: 1235 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1236 __fallthrough; 1237 case 5: 1238 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1239 __fallthrough; 1240 case 4: 1241 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1242 __fallthrough; 1243 case 3: 1244 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1245 __fallthrough; 1246 case 2: 1247 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1248 __fallthrough; 1249 case 1: 1250 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1251 break; 1252 } 1253 } 1254 1255 /* --------------------------------------------------------------------------- 1256 * The following registers are not added: 1257 * ICH_AP0R<n>_EL2 1258 * ICH_AP1R<n>_EL2 1259 * ICH_LR<n>_EL2 1260 * 1261 * NOTE: For a system with S-EL2 present but not enabled, accessing 1262 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1263 * SCR_EL3.NS = 1 before accessing this register. 1264 * --------------------------------------------------------------------------- 1265 */ 1266 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1267 { 1268 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1269 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1270 #else 1271 u_register_t scr_el3 = read_scr_el3(); 1272 write_scr_el3(scr_el3 | SCR_NS_BIT); 1273 isb(); 1274 1275 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1276 1277 write_scr_el3(scr_el3); 1278 isb(); 1279 #endif 1280 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1281 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1282 } 1283 1284 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1285 { 1286 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1287 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1288 #else 1289 u_register_t scr_el3 = read_scr_el3(); 1290 write_scr_el3(scr_el3 | SCR_NS_BIT); 1291 isb(); 1292 1293 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1294 1295 write_scr_el3(scr_el3); 1296 isb(); 1297 #endif 1298 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1299 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1300 } 1301 1302 /* ----------------------------------------------------- 1303 * The following registers are not added: 1304 * AMEVCNTVOFF0<n>_EL2 1305 * AMEVCNTVOFF1<n>_EL2 1306 * ----------------------------------------------------- 1307 */ 1308 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1309 { 1310 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1311 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1312 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1313 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1314 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1315 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1316 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1317 if (CTX_INCLUDE_AARCH32_REGS) { 1318 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1319 } 1320 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1321 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1322 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1323 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1324 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1325 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1326 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1327 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1328 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1329 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1330 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1331 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1332 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1333 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1334 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1335 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1336 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1337 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1338 1339 write_el2_ctx_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1340 write_el2_ctx_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1341 } 1342 1343 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1344 { 1345 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1346 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1347 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1348 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1349 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1350 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1351 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1352 if (CTX_INCLUDE_AARCH32_REGS) { 1353 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1354 } 1355 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1356 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1357 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1358 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1359 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1360 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1361 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1362 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1363 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1364 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1365 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1366 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1367 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1368 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1369 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1370 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1371 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1372 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1373 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1374 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1375 } 1376 1377 /******************************************************************************* 1378 * Save EL2 sysreg context 1379 ******************************************************************************/ 1380 void cm_el2_sysregs_context_save(uint32_t security_state) 1381 { 1382 cpu_context_t *ctx; 1383 el2_sysregs_t *el2_sysregs_ctx; 1384 1385 ctx = cm_get_context(security_state); 1386 assert(ctx != NULL); 1387 1388 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1389 1390 el2_sysregs_context_save_common(el2_sysregs_ctx); 1391 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1392 1393 if (is_feat_mte2_supported()) { 1394 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1395 } 1396 1397 if (is_feat_mpam_supported()) { 1398 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1399 } 1400 1401 if (is_feat_fgt_supported()) { 1402 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1403 } 1404 1405 if (is_feat_fgt2_supported()) { 1406 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1407 } 1408 1409 if (is_feat_ecv_v2_supported()) { 1410 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1411 } 1412 1413 if (is_feat_vhe_supported()) { 1414 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1415 read_contextidr_el2()); 1416 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1417 } 1418 1419 if (is_feat_ras_supported()) { 1420 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1421 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1422 } 1423 1424 if (is_feat_nv2_supported()) { 1425 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1426 } 1427 1428 if (is_feat_trf_supported()) { 1429 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1430 } 1431 1432 if (is_feat_csv2_2_supported()) { 1433 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1434 read_scxtnum_el2()); 1435 } 1436 1437 if (is_feat_hcx_supported()) { 1438 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1439 } 1440 1441 if (is_feat_tcr2_supported()) { 1442 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1443 } 1444 1445 if (is_feat_sxpie_supported()) { 1446 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1447 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1448 } 1449 1450 if (is_feat_sxpoe_supported()) { 1451 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1452 } 1453 1454 if (is_feat_s2pie_supported()) { 1455 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1456 } 1457 1458 if (is_feat_gcs_supported()) { 1459 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1460 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1461 } 1462 1463 if (is_feat_sctlr2_supported()) { 1464 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1465 } 1466 } 1467 1468 /******************************************************************************* 1469 * Restore EL2 sysreg context 1470 ******************************************************************************/ 1471 void cm_el2_sysregs_context_restore(uint32_t security_state) 1472 { 1473 cpu_context_t *ctx; 1474 el2_sysregs_t *el2_sysregs_ctx; 1475 1476 ctx = cm_get_context(security_state); 1477 assert(ctx != NULL); 1478 1479 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1480 1481 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1482 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1483 1484 if (is_feat_mte2_supported()) { 1485 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1486 } 1487 1488 if (is_feat_mpam_supported()) { 1489 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1490 } 1491 1492 if (is_feat_fgt_supported()) { 1493 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1494 } 1495 1496 if (is_feat_fgt2_supported()) { 1497 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1498 } 1499 1500 if (is_feat_ecv_v2_supported()) { 1501 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1502 } 1503 1504 if (is_feat_vhe_supported()) { 1505 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1506 contextidr_el2)); 1507 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1508 } 1509 1510 if (is_feat_ras_supported()) { 1511 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1512 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1513 } 1514 1515 if (is_feat_nv2_supported()) { 1516 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1517 } 1518 1519 if (is_feat_trf_supported()) { 1520 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1521 } 1522 1523 if (is_feat_csv2_2_supported()) { 1524 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1525 scxtnum_el2)); 1526 } 1527 1528 if (is_feat_hcx_supported()) { 1529 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1530 } 1531 1532 if (is_feat_tcr2_supported()) { 1533 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1534 } 1535 1536 if (is_feat_sxpie_supported()) { 1537 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1538 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1539 } 1540 1541 if (is_feat_sxpoe_supported()) { 1542 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1543 } 1544 1545 if (is_feat_s2pie_supported()) { 1546 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1547 } 1548 1549 if (is_feat_gcs_supported()) { 1550 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1551 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1552 } 1553 1554 if (is_feat_sctlr2_supported()) { 1555 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1556 } 1557 } 1558 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1559 1560 #if IMAGE_BL31 1561 /********************************************************************************* 1562 * This function allows Architecture features asymmetry among cores. 1563 * TF-A assumes that all the cores in the platform has architecture feature parity 1564 * and hence the context is setup on different core (e.g. primary sets up the 1565 * context for secondary cores).This assumption may not be true for systems where 1566 * cores are not conforming to same Arch version or there is CPU Erratum which 1567 * requires certain feature to be be disabled only on a given core. 1568 * 1569 * This function is called on secondary cores to override any disparity in context 1570 * setup by primary, this would be called during warmboot path. 1571 *********************************************************************************/ 1572 void cm_handle_asymmetric_features(void) 1573 { 1574 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1575 1576 assert(ctx != NULL); 1577 1578 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1579 if (is_feat_spe_supported()) { 1580 spe_enable(ctx); 1581 } else { 1582 spe_disable(ctx); 1583 } 1584 #endif 1585 1586 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1587 if (check_if_affected_core() == ERRATA_APPLIES) { 1588 if (is_feat_trbe_supported()) { 1589 trbe_disable(ctx); 1590 } 1591 } 1592 #endif 1593 1594 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1595 el3_state_t *el3_state = get_el3state_ctx(ctx); 1596 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1597 1598 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1599 tcr2_enable(ctx); 1600 } else { 1601 tcr2_disable(ctx); 1602 } 1603 #endif 1604 1605 } 1606 #endif 1607 1608 /******************************************************************************* 1609 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1610 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1611 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1612 * cm_prepare_el3_exit function. 1613 ******************************************************************************/ 1614 void cm_prepare_el3_exit_ns(void) 1615 { 1616 #if IMAGE_BL31 1617 /* 1618 * Check and handle Architecture feature asymmetry among cores. 1619 * 1620 * In warmboot path secondary cores context is initialized on core which 1621 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1622 * it in this function call. 1623 * For Symmetric cores this is an empty function. 1624 */ 1625 cm_handle_asymmetric_features(); 1626 #endif 1627 1628 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1629 #if ENABLE_ASSERTIONS 1630 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1631 assert(ctx != NULL); 1632 1633 /* Assert that EL2 is used. */ 1634 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1635 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1636 (el_implemented(2U) != EL_IMPL_NONE)); 1637 #endif /* ENABLE_ASSERTIONS */ 1638 1639 /* Restore EL2 sysreg contexts */ 1640 cm_el2_sysregs_context_restore(NON_SECURE); 1641 cm_set_next_eret_context(NON_SECURE); 1642 #else 1643 cm_prepare_el3_exit(NON_SECURE); 1644 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1645 } 1646 1647 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1648 /******************************************************************************* 1649 * The next set of six functions are used by runtime services to save and restore 1650 * EL1 context on the 'cpu_context' structure for the specified security state. 1651 ******************************************************************************/ 1652 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1653 { 1654 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1655 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1656 1657 #if (!ERRATA_SPECULATIVE_AT) 1658 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1659 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1660 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1661 1662 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1663 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1664 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1665 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1666 write_el1_ctx_common(ctx, ttbr0_el1, read_ttbr0_el1()); 1667 write_el1_ctx_common(ctx, ttbr1_el1, read_ttbr1_el1()); 1668 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1669 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1670 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1671 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1672 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1673 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1674 write_el1_ctx_common(ctx, par_el1, read_par_el1()); 1675 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1676 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1677 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1678 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1679 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1680 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1681 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1682 1683 if (CTX_INCLUDE_AARCH32_REGS) { 1684 /* Save Aarch32 registers */ 1685 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1686 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1687 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1688 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1689 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1690 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1691 } 1692 1693 if (NS_TIMER_SWITCH) { 1694 /* Save NS Timer registers */ 1695 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1696 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1697 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1698 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1699 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1700 } 1701 1702 if (is_feat_mte2_supported()) { 1703 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1704 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1705 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1706 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1707 } 1708 1709 if (is_feat_ras_supported()) { 1710 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1711 } 1712 1713 if (is_feat_s1pie_supported()) { 1714 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1715 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1716 } 1717 1718 if (is_feat_s1poe_supported()) { 1719 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1720 } 1721 1722 if (is_feat_s2poe_supported()) { 1723 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1724 } 1725 1726 if (is_feat_tcr2_supported()) { 1727 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1728 } 1729 1730 if (is_feat_trf_supported()) { 1731 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1732 } 1733 1734 if (is_feat_csv2_2_supported()) { 1735 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1736 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1737 } 1738 1739 if (is_feat_gcs_supported()) { 1740 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1741 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1742 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1743 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1744 } 1745 1746 if (is_feat_the_supported()) { 1747 write_el1_ctx_the(ctx, rcwmask_el1, read_rcwmask_el1()); 1748 write_el1_ctx_the(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1749 } 1750 1751 if (is_feat_sctlr2_supported()) { 1752 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1753 } 1754 1755 } 1756 1757 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1758 { 1759 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1760 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1761 1762 #if (!ERRATA_SPECULATIVE_AT) 1763 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1764 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1765 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1766 1767 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1768 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1769 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1770 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1771 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1772 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1773 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1774 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1775 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1776 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1777 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1778 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1779 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1780 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1781 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1782 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1783 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1784 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1785 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1786 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1787 1788 if (CTX_INCLUDE_AARCH32_REGS) { 1789 /* Restore Aarch32 registers */ 1790 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1791 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1792 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1793 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1794 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1795 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1796 } 1797 1798 if (NS_TIMER_SWITCH) { 1799 /* Restore NS Timer registers */ 1800 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1801 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1802 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1803 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1804 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1805 } 1806 1807 if (is_feat_mte2_supported()) { 1808 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1809 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1810 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1811 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1812 } 1813 1814 if (is_feat_ras_supported()) { 1815 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1816 } 1817 1818 if (is_feat_s1pie_supported()) { 1819 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1820 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1821 } 1822 1823 if (is_feat_s1poe_supported()) { 1824 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1825 } 1826 1827 if (is_feat_s2poe_supported()) { 1828 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1829 } 1830 1831 if (is_feat_tcr2_supported()) { 1832 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1833 } 1834 1835 if (is_feat_trf_supported()) { 1836 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1837 } 1838 1839 if (is_feat_csv2_2_supported()) { 1840 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1841 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1842 } 1843 1844 if (is_feat_gcs_supported()) { 1845 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1846 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1847 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1848 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1849 } 1850 1851 if (is_feat_the_supported()) { 1852 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1853 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1854 } 1855 1856 if (is_feat_sctlr2_supported()) { 1857 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1858 } 1859 1860 } 1861 1862 /******************************************************************************* 1863 * The next couple of functions are used by runtime services to save and restore 1864 * EL1 context on the 'cpu_context' structure for the specified security state. 1865 ******************************************************************************/ 1866 void cm_el1_sysregs_context_save(uint32_t security_state) 1867 { 1868 cpu_context_t *ctx; 1869 1870 ctx = cm_get_context(security_state); 1871 assert(ctx != NULL); 1872 1873 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1874 1875 #if IMAGE_BL31 1876 if (security_state == SECURE) 1877 PUBLISH_EVENT(cm_exited_secure_world); 1878 else 1879 PUBLISH_EVENT(cm_exited_normal_world); 1880 #endif 1881 } 1882 1883 void cm_el1_sysregs_context_restore(uint32_t security_state) 1884 { 1885 cpu_context_t *ctx; 1886 1887 ctx = cm_get_context(security_state); 1888 assert(ctx != NULL); 1889 1890 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1891 1892 #if IMAGE_BL31 1893 if (security_state == SECURE) 1894 PUBLISH_EVENT(cm_entering_secure_world); 1895 else 1896 PUBLISH_EVENT(cm_entering_normal_world); 1897 #endif 1898 } 1899 1900 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1901 1902 /******************************************************************************* 1903 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1904 * given security state with the given entrypoint 1905 ******************************************************************************/ 1906 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1907 { 1908 cpu_context_t *ctx; 1909 el3_state_t *state; 1910 1911 ctx = cm_get_context(security_state); 1912 assert(ctx != NULL); 1913 1914 /* Populate EL3 state so that ERET jumps to the correct entry */ 1915 state = get_el3state_ctx(ctx); 1916 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1917 } 1918 1919 /******************************************************************************* 1920 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1921 * pertaining to the given security state 1922 ******************************************************************************/ 1923 void cm_set_elr_spsr_el3(uint32_t security_state, 1924 uintptr_t entrypoint, uint32_t spsr) 1925 { 1926 cpu_context_t *ctx; 1927 el3_state_t *state; 1928 1929 ctx = cm_get_context(security_state); 1930 assert(ctx != NULL); 1931 1932 /* Populate EL3 state so that ERET jumps to the correct entry */ 1933 state = get_el3state_ctx(ctx); 1934 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1935 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1936 } 1937 1938 /******************************************************************************* 1939 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1940 * pertaining to the given security state using the value and bit position 1941 * specified in the parameters. It preserves all other bits. 1942 ******************************************************************************/ 1943 void cm_write_scr_el3_bit(uint32_t security_state, 1944 uint32_t bit_pos, 1945 uint32_t value) 1946 { 1947 cpu_context_t *ctx; 1948 el3_state_t *state; 1949 u_register_t scr_el3; 1950 1951 ctx = cm_get_context(security_state); 1952 assert(ctx != NULL); 1953 1954 /* Ensure that the bit position is a valid one */ 1955 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1956 1957 /* Ensure that the 'value' is only a bit wide */ 1958 assert(value <= 1U); 1959 1960 /* 1961 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1962 * and set it to its new value. 1963 */ 1964 state = get_el3state_ctx(ctx); 1965 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1966 scr_el3 &= ~(1UL << bit_pos); 1967 scr_el3 |= (u_register_t)value << bit_pos; 1968 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1969 } 1970 1971 /******************************************************************************* 1972 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1973 * given security state. 1974 ******************************************************************************/ 1975 u_register_t cm_get_scr_el3(uint32_t security_state) 1976 { 1977 cpu_context_t *ctx; 1978 el3_state_t *state; 1979 1980 ctx = cm_get_context(security_state); 1981 assert(ctx != NULL); 1982 1983 /* Populate EL3 state so that ERET jumps to the correct entry */ 1984 state = get_el3state_ctx(ctx); 1985 return read_ctx_reg(state, CTX_SCR_EL3); 1986 } 1987 1988 /******************************************************************************* 1989 * This function is used to program the context that's used for exception 1990 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1991 * the required security state 1992 ******************************************************************************/ 1993 void cm_set_next_eret_context(uint32_t security_state) 1994 { 1995 cpu_context_t *ctx; 1996 1997 ctx = cm_get_context(security_state); 1998 assert(ctx != NULL); 1999 2000 cm_set_next_context(ctx); 2001 } 2002