1 /* 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <drivers/arm/gicv3.h> 20 #include <lib/el3_runtime/context_mgmt.h> 21 #include <lib/el3_runtime/pubsub_events.h> 22 #include <lib/extensions/amu.h> 23 #include <lib/extensions/brbe.h> 24 #include <lib/extensions/mpam.h> 25 #include <lib/extensions/sme.h> 26 #include <lib/extensions/spe.h> 27 #include <lib/extensions/sve.h> 28 #include <lib/extensions/sys_reg_trace.h> 29 #include <lib/extensions/trbe.h> 30 #include <lib/extensions/trf.h> 31 #include <lib/utils.h> 32 33 #if ENABLE_FEAT_TWED 34 /* Make sure delay value fits within the range(0-15) */ 35 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 36 #endif /* ENABLE_FEAT_TWED */ 37 38 static void manage_extensions_secure(cpu_context_t *ctx); 39 /****************************************************************************** 40 * This function performs initializations that are specific to SECURE state 41 * and updates the cpu context specified by 'ctx'. 42 *****************************************************************************/ 43 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 44 { 45 u_register_t scr_el3; 46 el3_state_t *state; 47 48 state = get_el3state_ctx(ctx); 49 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 50 51 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 52 /* 53 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 54 * indicated by the interrupt routing model for BL31. 55 */ 56 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 57 #endif 58 59 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 60 /* Get Memory Tagging Extension support level */ 61 unsigned int mte = get_armv8_5_mte_support(); 62 #endif 63 /* 64 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 65 * is set, or when MTE is only implemented at EL0. 66 */ 67 #if CTX_INCLUDE_MTE_REGS 68 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 69 scr_el3 |= SCR_ATA_BIT; 70 #else 71 if (mte == MTE_IMPLEMENTED_EL0) { 72 scr_el3 |= SCR_ATA_BIT; 73 } 74 #endif /* CTX_INCLUDE_MTE_REGS */ 75 76 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 77 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) { 78 if (GET_RW(ep->spsr) != MODE_RW_64) { 79 ERROR("S-EL2 can not be used in AArch32\n."); 80 panic(); 81 } 82 83 scr_el3 |= SCR_EEL2_BIT; 84 } 85 86 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 87 88 manage_extensions_secure(ctx); 89 } 90 91 #if ENABLE_RME 92 /****************************************************************************** 93 * This function performs initializations that are specific to REALM state 94 * and updates the cpu context specified by 'ctx'. 95 *****************************************************************************/ 96 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 97 { 98 u_register_t scr_el3; 99 el3_state_t *state; 100 101 state = get_el3state_ctx(ctx); 102 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 103 104 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT; 105 106 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 107 } 108 #endif /* ENABLE_RME */ 109 110 /****************************************************************************** 111 * This function performs initializations that are specific to NON-SECURE state 112 * and updates the cpu context specified by 'ctx'. 113 *****************************************************************************/ 114 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 115 { 116 u_register_t scr_el3; 117 el3_state_t *state; 118 119 state = get_el3state_ctx(ctx); 120 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 121 122 /* SCR_NS: Set the NS bit */ 123 scr_el3 |= SCR_NS_BIT; 124 125 #if !CTX_INCLUDE_PAUTH_REGS 126 /* 127 * If the pointer authentication registers aren't saved during world 128 * switches the value of the registers can be leaked from the Secure to 129 * the Non-secure world. To prevent this, rather than enabling pointer 130 * authentication everywhere, we only enable it in the Non-secure world. 131 * 132 * If the Secure world wants to use pointer authentication, 133 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 134 */ 135 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 136 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 137 138 /* Allow access to Allocation Tags when MTE is implemented. */ 139 scr_el3 |= SCR_ATA_BIT; 140 141 #ifdef IMAGE_BL31 142 /* 143 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 144 * indicated by the interrupt routing model for BL31. 145 */ 146 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 147 #endif 148 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 149 150 /* Initialize EL2 context registers */ 151 #if CTX_INCLUDE_EL2_REGS 152 153 /* 154 * Initialize SCTLR_EL2 context register using Endianness value 155 * taken from the entrypoint attribute. 156 */ 157 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 158 sctlr_el2 |= SCTLR_EL2_RES1; 159 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 160 sctlr_el2); 161 162 /* 163 * The GICv3 driver initializes the ICC_SRE_EL2 register during 164 * platform setup. Use the same setting for the corresponding 165 * context register to make sure the correct bits are set when 166 * restoring NS context. 167 */ 168 u_register_t icc_sre_el2 = read_icc_sre_el2(); 169 icc_sre_el2 |= (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT); 170 icc_sre_el2 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 171 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 172 icc_sre_el2); 173 #endif /* CTX_INCLUDE_EL2_REGS */ 174 } 175 176 /******************************************************************************* 177 * The following function performs initialization of the cpu_context 'ctx' 178 * for first use that is common to all security states, and sets the 179 * initial entrypoint state as specified by the entry_point_info structure. 180 * 181 * The EE and ST attributes are used to configure the endianness and secure 182 * timer availability for the new execution context. 183 ******************************************************************************/ 184 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 185 { 186 u_register_t scr_el3; 187 el3_state_t *state; 188 gp_regs_t *gp_regs; 189 u_register_t sctlr_elx, actlr_elx; 190 191 /* Clear any residual register values from the context */ 192 zeromem(ctx, sizeof(*ctx)); 193 194 /* 195 * SCR_EL3 was initialised during reset sequence in macro 196 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 197 * affect the next EL. 198 * 199 * The following fields are initially set to zero and then updated to 200 * the required value depending on the state of the SPSR_EL3 and the 201 * Security state and entrypoint attributes of the next EL. 202 */ 203 scr_el3 = read_scr(); 204 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 205 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 206 207 /* 208 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 209 * Exception level as specified by SPSR. 210 */ 211 if (GET_RW(ep->spsr) == MODE_RW_64) { 212 scr_el3 |= SCR_RW_BIT; 213 } 214 215 /* 216 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 217 * Secure timer registers to EL3, from AArch64 state only, if specified 218 * by the entrypoint attributes. 219 */ 220 if (EP_GET_ST(ep->h.attr) != 0U) { 221 scr_el3 |= SCR_ST_BIT; 222 } 223 224 /* 225 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 226 * SCR_EL3.HXEn. 227 */ 228 #if ENABLE_FEAT_HCX 229 scr_el3 |= SCR_HXEn_BIT; 230 #endif 231 232 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 233 /* 234 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 235 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 236 */ 237 scr_el3 |= SCR_TERR_BIT; 238 #endif 239 240 #if !HANDLE_EA_EL3_FIRST 241 /* 242 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 243 * to EL3 when executing at a lower EL. When executing at EL3, External 244 * Aborts are taken to EL3. 245 */ 246 scr_el3 &= ~SCR_EA_BIT; 247 #endif 248 249 #if FAULT_INJECTION_SUPPORT 250 /* Enable fault injection from lower ELs */ 251 scr_el3 |= SCR_FIEN_BIT; 252 #endif 253 254 /* 255 * CPTR_EL3 was initialized out of reset, copy that value to the 256 * context register. 257 */ 258 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 259 260 /* 261 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 262 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 263 * next mode is Hyp. 264 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 265 * same conditions as HVC instructions and when the processor supports 266 * ARMv8.6-FGT. 267 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 268 * CNTPOFF_EL2 register under the same conditions as HVC instructions 269 * and when the processor supports ECV. 270 */ 271 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 272 || ((GET_RW(ep->spsr) != MODE_RW_64) 273 && (GET_M32(ep->spsr) == MODE32_hyp))) { 274 scr_el3 |= SCR_HCE_BIT; 275 276 if (is_armv8_6_fgt_present()) { 277 scr_el3 |= SCR_FGTEN_BIT; 278 } 279 280 if (get_armv8_6_ecv_support() 281 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 282 scr_el3 |= SCR_ECVEN_BIT; 283 } 284 } 285 286 /* 287 * Initialise SCTLR_EL1 to the reset value corresponding to the target 288 * execution state setting all fields rather than relying of the hw. 289 * Some fields have architecturally UNKNOWN reset values and these are 290 * set to zero. 291 * 292 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 293 * 294 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 295 * required by PSCI specification) 296 */ 297 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 298 if (GET_RW(ep->spsr) == MODE_RW_64) { 299 sctlr_elx |= SCTLR_EL1_RES1; 300 } else { 301 /* 302 * If the target execution state is AArch32 then the following 303 * fields need to be set. 304 * 305 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 306 * instructions are not trapped to EL1. 307 * 308 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 309 * instructions are not trapped to EL1. 310 * 311 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 312 * CP15DMB, CP15DSB, and CP15ISB instructions. 313 */ 314 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 315 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 316 } 317 318 #if ERRATA_A75_764081 319 /* 320 * If workaround of errata 764081 for Cortex-A75 is used then set 321 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 322 */ 323 sctlr_elx |= SCTLR_IESB_BIT; 324 #endif 325 326 #if ENABLE_FEAT_TWED 327 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 328 /* Set delay in SCR_EL3 */ 329 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 330 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 331 << SCR_TWEDEL_SHIFT); 332 333 /* Enable WFE delay */ 334 scr_el3 |= SCR_TWEDEn_BIT; 335 #endif /* ENABLE_FEAT_TWED */ 336 337 /* 338 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 339 * and other EL2 registers are set up by cm_prepare_el3_exit() as they 340 * are not part of the stored cpu_context. 341 */ 342 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 343 344 /* 345 * Base the context ACTLR_EL1 on the current value, as it is 346 * implementation defined. The context restore process will write 347 * the value from the context to the actual register and can cause 348 * problems for processor cores that don't expect certain bits to 349 * be zero. 350 */ 351 actlr_elx = read_actlr_el1(); 352 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 353 354 /* 355 * Populate EL3 state so that we've the right context 356 * before doing ERET 357 */ 358 state = get_el3state_ctx(ctx); 359 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 360 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 361 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 362 363 /* 364 * Store the X0-X7 value from the entrypoint into the context 365 * Use memcpy as we are in control of the layout of the structures 366 */ 367 gp_regs = get_gpregs_ctx(ctx); 368 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 369 } 370 371 /******************************************************************************* 372 * Context management library initialization routine. This library is used by 373 * runtime services to share pointers to 'cpu_context' structures for secure 374 * non-secure and realm states. Management of the structures and their associated 375 * memory is not done by the context management library e.g. the PSCI service 376 * manages the cpu context used for entry from and exit to the non-secure state. 377 * The Secure payload dispatcher service manages the context(s) corresponding to 378 * the secure state. It also uses this library to get access to the non-secure 379 * state cpu context pointers. 380 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 381 * which will be used for programming an entry into a lower EL. The same context 382 * will be used to save state upon exception entry from that EL. 383 ******************************************************************************/ 384 void __init cm_init(void) 385 { 386 /* 387 * The context management library has only global data to intialize, but 388 * that will be done when the BSS is zeroed out. 389 */ 390 } 391 392 /******************************************************************************* 393 * This is the high-level function used to initialize the cpu_context 'ctx' for 394 * first use. It performs initializations that are common to all security states 395 * and initializations specific to the security state specified in 'ep' 396 ******************************************************************************/ 397 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 398 { 399 unsigned int security_state; 400 401 assert(ctx != NULL); 402 403 /* 404 * Perform initializations that are common 405 * to all security states 406 */ 407 setup_context_common(ctx, ep); 408 409 security_state = GET_SECURITY_STATE(ep->h.attr); 410 411 /* Perform security state specific initializations */ 412 switch (security_state) { 413 case SECURE: 414 setup_secure_context(ctx, ep); 415 break; 416 #if ENABLE_RME 417 case REALM: 418 setup_realm_context(ctx, ep); 419 break; 420 #endif 421 case NON_SECURE: 422 setup_ns_context(ctx, ep); 423 break; 424 default: 425 ERROR("Invalid security state\n"); 426 panic(); 427 break; 428 } 429 } 430 431 /******************************************************************************* 432 * Enable architecture extensions on first entry to Non-secure world. 433 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 434 * it is zero. 435 ******************************************************************************/ 436 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 437 { 438 #if IMAGE_BL31 439 #if ENABLE_SPE_FOR_LOWER_ELS 440 spe_enable(el2_unused); 441 #endif 442 443 #if ENABLE_AMU 444 amu_enable(el2_unused, ctx); 445 #endif 446 447 #if ENABLE_SME_FOR_NS 448 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 449 sme_enable(ctx); 450 #elif ENABLE_SVE_FOR_NS 451 /* Enable SVE and FPU/SIMD for non-secure world. */ 452 sve_enable(ctx); 453 #endif 454 455 #if ENABLE_MPAM_FOR_LOWER_ELS 456 mpam_enable(el2_unused); 457 #endif 458 459 #if ENABLE_TRBE_FOR_NS 460 trbe_enable(); 461 #endif /* ENABLE_TRBE_FOR_NS */ 462 463 #if ENABLE_BRBE_FOR_NS 464 brbe_enable(); 465 #endif /* ENABLE_BRBE_FOR_NS */ 466 467 #if ENABLE_SYS_REG_TRACE_FOR_NS 468 sys_reg_trace_enable(ctx); 469 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 470 471 #if ENABLE_TRF_FOR_NS 472 trf_enable(); 473 #endif /* ENABLE_TRF_FOR_NS */ 474 #endif 475 } 476 477 /******************************************************************************* 478 * Enable architecture extensions on first entry to Secure world. 479 ******************************************************************************/ 480 static void manage_extensions_secure(cpu_context_t *ctx) 481 { 482 #if IMAGE_BL31 483 #if ENABLE_SME_FOR_NS 484 #if ENABLE_SME_FOR_SWD 485 /* 486 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must 487 * ensure SME, SVE, and FPU/SIMD context properly managed. 488 */ 489 sme_enable(ctx); 490 #else /* ENABLE_SME_FOR_SWD */ 491 /* 492 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can 493 * safely use the associated registers. 494 */ 495 sme_disable(ctx); 496 #endif /* ENABLE_SME_FOR_SWD */ 497 #elif ENABLE_SVE_FOR_NS 498 #if ENABLE_SVE_FOR_SWD 499 /* 500 * Enable SVE and FPU in secure context, secure manager must ensure that 501 * the SVE and FPU register contexts are properly managed. 502 */ 503 sve_enable(ctx); 504 #else /* ENABLE_SVE_FOR_SWD */ 505 /* 506 * Disable SVE and FPU in secure context so non-secure world can safely 507 * use them. 508 */ 509 sve_disable(ctx); 510 #endif /* ENABLE_SVE_FOR_SWD */ 511 #endif /* ENABLE_SVE_FOR_NS */ 512 #endif /* IMAGE_BL31 */ 513 } 514 515 /******************************************************************************* 516 * The following function initializes the cpu_context for a CPU specified by 517 * its `cpu_idx` for first use, and sets the initial entrypoint state as 518 * specified by the entry_point_info structure. 519 ******************************************************************************/ 520 void cm_init_context_by_index(unsigned int cpu_idx, 521 const entry_point_info_t *ep) 522 { 523 cpu_context_t *ctx; 524 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 525 cm_setup_context(ctx, ep); 526 } 527 528 /******************************************************************************* 529 * The following function initializes the cpu_context for the current CPU 530 * for first use, and sets the initial entrypoint state as specified by the 531 * entry_point_info structure. 532 ******************************************************************************/ 533 void cm_init_my_context(const entry_point_info_t *ep) 534 { 535 cpu_context_t *ctx; 536 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 537 cm_setup_context(ctx, ep); 538 } 539 540 /******************************************************************************* 541 * Prepare the CPU system registers for first entry into realm, secure, or 542 * normal world. 543 * 544 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 545 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 546 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 547 * For all entries, the EL1 registers are initialized from the cpu_context 548 ******************************************************************************/ 549 void cm_prepare_el3_exit(uint32_t security_state) 550 { 551 u_register_t sctlr_elx, scr_el3, mdcr_el2; 552 cpu_context_t *ctx = cm_get_context(security_state); 553 bool el2_unused = false; 554 uint64_t hcr_el2 = 0U; 555 556 assert(ctx != NULL); 557 558 if (security_state == NON_SECURE) { 559 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 560 CTX_SCR_EL3); 561 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 562 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 563 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 564 CTX_SCTLR_EL1); 565 sctlr_elx &= SCTLR_EE_BIT; 566 sctlr_elx |= SCTLR_EL2_RES1; 567 #if ERRATA_A75_764081 568 /* 569 * If workaround of errata 764081 for Cortex-A75 is used 570 * then set SCTLR_EL2.IESB to enable Implicit Error 571 * Synchronization Barrier. 572 */ 573 sctlr_elx |= SCTLR_IESB_BIT; 574 #endif 575 write_sctlr_el2(sctlr_elx); 576 } else if (el_implemented(2) != EL_IMPL_NONE) { 577 el2_unused = true; 578 579 /* 580 * EL2 present but unused, need to disable safely. 581 * SCTLR_EL2 can be ignored in this case. 582 * 583 * Set EL2 register width appropriately: Set HCR_EL2 584 * field to match SCR_EL3.RW. 585 */ 586 if ((scr_el3 & SCR_RW_BIT) != 0U) 587 hcr_el2 |= HCR_RW_BIT; 588 589 /* 590 * For Armv8.3 pointer authentication feature, disable 591 * traps to EL2 when accessing key registers or using 592 * pointer authentication instructions from lower ELs. 593 */ 594 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 595 596 write_hcr_el2(hcr_el2); 597 598 /* 599 * Initialise CPTR_EL2 setting all fields rather than 600 * relying on the hw. All fields have architecturally 601 * UNKNOWN reset values. 602 * 603 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 604 * accesses to the CPACR_EL1 or CPACR from both 605 * Execution states do not trap to EL2. 606 * 607 * CPTR_EL2.TTA: Set to zero so that Non-secure System 608 * register accesses to the trace registers from both 609 * Execution states do not trap to EL2. 610 * If PE trace unit System registers are not implemented 611 * then this bit is reserved, and must be set to zero. 612 * 613 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 614 * to SIMD and floating-point functionality from both 615 * Execution states do not trap to EL2. 616 */ 617 write_cptr_el2(CPTR_EL2_RESET_VAL & 618 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 619 | CPTR_EL2_TFP_BIT)); 620 621 /* 622 * Initialise CNTHCTL_EL2. All fields are 623 * architecturally UNKNOWN on reset and are set to zero 624 * except for field(s) listed below. 625 * 626 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 627 * Hyp mode of Non-secure EL0 and EL1 accesses to the 628 * physical timer registers. 629 * 630 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 631 * Hyp mode of Non-secure EL0 and EL1 accesses to the 632 * physical counter registers. 633 */ 634 write_cnthctl_el2(CNTHCTL_RESET_VAL | 635 EL1PCEN_BIT | EL1PCTEN_BIT); 636 637 /* 638 * Initialise CNTVOFF_EL2 to zero as it resets to an 639 * architecturally UNKNOWN value. 640 */ 641 write_cntvoff_el2(0); 642 643 /* 644 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 645 * MPIDR_EL1 respectively. 646 */ 647 write_vpidr_el2(read_midr_el1()); 648 write_vmpidr_el2(read_mpidr_el1()); 649 650 /* 651 * Initialise VTTBR_EL2. All fields are architecturally 652 * UNKNOWN on reset. 653 * 654 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 655 * 2 address translation is disabled, cache maintenance 656 * operations depend on the VMID. 657 * 658 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 659 * translation is disabled. 660 */ 661 write_vttbr_el2(VTTBR_RESET_VAL & 662 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 663 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 664 665 /* 666 * Initialise MDCR_EL2, setting all fields rather than 667 * relying on hw. Some fields are architecturally 668 * UNKNOWN on reset. 669 * 670 * MDCR_EL2.HLP: Set to one so that event counter 671 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 672 * occurs on the increment that changes 673 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 674 * implemented. This bit is RES0 in versions of the 675 * architecture earlier than ARMv8.5, setting it to 1 676 * doesn't have any effect on them. 677 * 678 * MDCR_EL2.TTRF: Set to zero so that access to Trace 679 * Filter Control register TRFCR_EL1 at EL1 is not 680 * trapped to EL2. This bit is RES0 in versions of 681 * the architecture earlier than ARMv8.4. 682 * 683 * MDCR_EL2.HPMD: Set to one so that event counting is 684 * prohibited at EL2. This bit is RES0 in versions of 685 * the architecture earlier than ARMv8.1, setting it 686 * to 1 doesn't have any effect on them. 687 * 688 * MDCR_EL2.TPMS: Set to zero so that accesses to 689 * Statistical Profiling control registers from EL1 690 * do not trap to EL2. This bit is RES0 when SPE is 691 * not implemented. 692 * 693 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 694 * EL1 System register accesses to the Debug ROM 695 * registers are not trapped to EL2. 696 * 697 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 698 * System register accesses to the powerdown debug 699 * registers are not trapped to EL2. 700 * 701 * MDCR_EL2.TDA: Set to zero so that System register 702 * accesses to the debug registers do not trap to EL2. 703 * 704 * MDCR_EL2.TDE: Set to zero so that debug exceptions 705 * are not routed to EL2. 706 * 707 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 708 * Monitors. 709 * 710 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 711 * EL1 accesses to all Performance Monitors registers 712 * are not trapped to EL2. 713 * 714 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 715 * and EL1 accesses to the PMCR_EL0 or PMCR are not 716 * trapped to EL2. 717 * 718 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 719 * architecturally-defined reset value. 720 * 721 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 722 * owning exception level is NS-EL1 and, tracing is 723 * prohibited at NS-EL2. These bits are RES0 when 724 * FEAT_TRBE is not implemented. 725 */ 726 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 727 MDCR_EL2_HPMD) | 728 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 729 >> PMCR_EL0_N_SHIFT)) & 730 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 731 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 732 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 733 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 734 MDCR_EL2_TPMCR_BIT | 735 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 736 737 write_mdcr_el2(mdcr_el2); 738 739 /* 740 * Initialise HSTR_EL2. All fields are architecturally 741 * UNKNOWN on reset. 742 * 743 * HSTR_EL2.T<n>: Set all these fields to zero so that 744 * Non-secure EL0 or EL1 accesses to System registers 745 * do not trap to EL2. 746 */ 747 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 748 /* 749 * Initialise CNTHP_CTL_EL2. All fields are 750 * architecturally UNKNOWN on reset. 751 * 752 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 753 * physical timer and prevent timer interrupts. 754 */ 755 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 756 ~(CNTHP_CTL_ENABLE_BIT)); 757 } 758 manage_extensions_nonsecure(el2_unused, ctx); 759 } 760 761 cm_el1_sysregs_context_restore(security_state); 762 cm_set_next_eret_context(security_state); 763 } 764 765 #if CTX_INCLUDE_EL2_REGS 766 /******************************************************************************* 767 * Save EL2 sysreg context 768 ******************************************************************************/ 769 void cm_el2_sysregs_context_save(uint32_t security_state) 770 { 771 u_register_t scr_el3 = read_scr(); 772 773 /* 774 * Always save the non-secure and realm EL2 context, only save the 775 * S-EL2 context if S-EL2 is enabled. 776 */ 777 if ((security_state != SECURE) || 778 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 779 cpu_context_t *ctx; 780 781 ctx = cm_get_context(security_state); 782 assert(ctx != NULL); 783 784 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 785 } 786 } 787 788 /******************************************************************************* 789 * Restore EL2 sysreg context 790 ******************************************************************************/ 791 void cm_el2_sysregs_context_restore(uint32_t security_state) 792 { 793 u_register_t scr_el3 = read_scr(); 794 795 /* 796 * Always restore the non-secure and realm EL2 context, only restore the 797 * S-EL2 context if S-EL2 is enabled. 798 */ 799 if ((security_state != SECURE) || 800 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 801 cpu_context_t *ctx; 802 803 ctx = cm_get_context(security_state); 804 assert(ctx != NULL); 805 806 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 807 } 808 } 809 #endif /* CTX_INCLUDE_EL2_REGS */ 810 811 /******************************************************************************* 812 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 813 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 814 * updating EL1 and EL2 registers. Otherwise, it calls the generic 815 * cm_prepare_el3_exit function. 816 ******************************************************************************/ 817 void cm_prepare_el3_exit_ns(void) 818 { 819 #if CTX_INCLUDE_EL2_REGS 820 cpu_context_t *ctx = cm_get_context(NON_SECURE); 821 assert(ctx != NULL); 822 823 /* 824 * Currently some extensions are configured using 825 * direct register updates. Therefore, do this here 826 * instead of when setting up context. 827 */ 828 manage_extensions_nonsecure(0, ctx); 829 830 /* 831 * Set the NS bit to be able to access the ICC_SRE_EL2 832 * register when restoring context. 833 */ 834 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 835 836 /* 837 * Ensure the NS bit change is committed before the EL2/EL1 838 * state restoration. 839 */ 840 isb(); 841 842 /* Restore EL2 and EL1 sysreg contexts */ 843 cm_el2_sysregs_context_restore(NON_SECURE); 844 cm_el1_sysregs_context_restore(NON_SECURE); 845 cm_set_next_eret_context(NON_SECURE); 846 #else 847 cm_prepare_el3_exit(NON_SECURE); 848 #endif /* CTX_INCLUDE_EL2_REGS */ 849 } 850 851 /******************************************************************************* 852 * The next four functions are used by runtime services to save and restore 853 * EL1 context on the 'cpu_context' structure for the specified security 854 * state. 855 ******************************************************************************/ 856 void cm_el1_sysregs_context_save(uint32_t security_state) 857 { 858 cpu_context_t *ctx; 859 860 ctx = cm_get_context(security_state); 861 assert(ctx != NULL); 862 863 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 864 865 #if IMAGE_BL31 866 if (security_state == SECURE) 867 PUBLISH_EVENT(cm_exited_secure_world); 868 else 869 PUBLISH_EVENT(cm_exited_normal_world); 870 #endif 871 } 872 873 void cm_el1_sysregs_context_restore(uint32_t security_state) 874 { 875 cpu_context_t *ctx; 876 877 ctx = cm_get_context(security_state); 878 assert(ctx != NULL); 879 880 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 881 882 #if IMAGE_BL31 883 if (security_state == SECURE) 884 PUBLISH_EVENT(cm_entering_secure_world); 885 else 886 PUBLISH_EVENT(cm_entering_normal_world); 887 #endif 888 } 889 890 /******************************************************************************* 891 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 892 * given security state with the given entrypoint 893 ******************************************************************************/ 894 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 895 { 896 cpu_context_t *ctx; 897 el3_state_t *state; 898 899 ctx = cm_get_context(security_state); 900 assert(ctx != NULL); 901 902 /* Populate EL3 state so that ERET jumps to the correct entry */ 903 state = get_el3state_ctx(ctx); 904 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 905 } 906 907 /******************************************************************************* 908 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 909 * pertaining to the given security state 910 ******************************************************************************/ 911 void cm_set_elr_spsr_el3(uint32_t security_state, 912 uintptr_t entrypoint, uint32_t spsr) 913 { 914 cpu_context_t *ctx; 915 el3_state_t *state; 916 917 ctx = cm_get_context(security_state); 918 assert(ctx != NULL); 919 920 /* Populate EL3 state so that ERET jumps to the correct entry */ 921 state = get_el3state_ctx(ctx); 922 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 923 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 924 } 925 926 /******************************************************************************* 927 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 928 * pertaining to the given security state using the value and bit position 929 * specified in the parameters. It preserves all other bits. 930 ******************************************************************************/ 931 void cm_write_scr_el3_bit(uint32_t security_state, 932 uint32_t bit_pos, 933 uint32_t value) 934 { 935 cpu_context_t *ctx; 936 el3_state_t *state; 937 u_register_t scr_el3; 938 939 ctx = cm_get_context(security_state); 940 assert(ctx != NULL); 941 942 /* Ensure that the bit position is a valid one */ 943 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 944 945 /* Ensure that the 'value' is only a bit wide */ 946 assert(value <= 1U); 947 948 /* 949 * Get the SCR_EL3 value from the cpu context, clear the desired bit 950 * and set it to its new value. 951 */ 952 state = get_el3state_ctx(ctx); 953 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 954 scr_el3 &= ~(1UL << bit_pos); 955 scr_el3 |= (u_register_t)value << bit_pos; 956 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 957 } 958 959 /******************************************************************************* 960 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 961 * given security state. 962 ******************************************************************************/ 963 u_register_t cm_get_scr_el3(uint32_t security_state) 964 { 965 cpu_context_t *ctx; 966 el3_state_t *state; 967 968 ctx = cm_get_context(security_state); 969 assert(ctx != NULL); 970 971 /* Populate EL3 state so that ERET jumps to the correct entry */ 972 state = get_el3state_ctx(ctx); 973 return read_ctx_reg(state, CTX_SCR_EL3); 974 } 975 976 /******************************************************************************* 977 * This function is used to program the context that's used for exception 978 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 979 * the required security state 980 ******************************************************************************/ 981 void cm_set_next_eret_context(uint32_t security_state) 982 { 983 cpu_context_t *ctx; 984 985 ctx = cm_get_context(security_state); 986 assert(ctx != NULL); 987 988 cm_set_next_context(ctx); 989 } 990