1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/sme.h> 28 #include <lib/extensions/spe.h> 29 #include <lib/extensions/sve.h> 30 #include <lib/extensions/sys_reg_trace.h> 31 #include <lib/extensions/trbe.h> 32 #include <lib/extensions/trf.h> 33 #include <lib/utils.h> 34 35 #if ENABLE_FEAT_TWED 36 /* Make sure delay value fits within the range(0-15) */ 37 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 38 #endif /* ENABLE_FEAT_TWED */ 39 40 static void manage_extensions_secure(cpu_context_t *ctx); 41 42 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 43 { 44 u_register_t sctlr_elx, actlr_elx; 45 46 /* 47 * Initialise SCTLR_EL1 to the reset value corresponding to the target 48 * execution state setting all fields rather than relying on the hw. 49 * Some fields have architecturally UNKNOWN reset values and these are 50 * set to zero. 51 * 52 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 53 * 54 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 55 * required by PSCI specification) 56 */ 57 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 58 if (GET_RW(ep->spsr) == MODE_RW_64) { 59 sctlr_elx |= SCTLR_EL1_RES1; 60 } else { 61 /* 62 * If the target execution state is AArch32 then the following 63 * fields need to be set. 64 * 65 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 66 * instructions are not trapped to EL1. 67 * 68 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 69 * instructions are not trapped to EL1. 70 * 71 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 72 * CP15DMB, CP15DSB, and CP15ISB instructions. 73 */ 74 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 75 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 76 } 77 78 #if ERRATA_A75_764081 79 /* 80 * If workaround of errata 764081 for Cortex-A75 is used then set 81 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 82 */ 83 sctlr_elx |= SCTLR_IESB_BIT; 84 #endif 85 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 86 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 87 88 /* 89 * Base the context ACTLR_EL1 on the current value, as it is 90 * implementation defined. The context restore process will write 91 * the value from the context to the actual register and can cause 92 * problems for processor cores that don't expect certain bits to 93 * be zero. 94 */ 95 actlr_elx = read_actlr_el1(); 96 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 97 } 98 99 /****************************************************************************** 100 * This function performs initializations that are specific to SECURE state 101 * and updates the cpu context specified by 'ctx'. 102 *****************************************************************************/ 103 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 104 { 105 u_register_t scr_el3; 106 el3_state_t *state; 107 108 state = get_el3state_ctx(ctx); 109 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 110 111 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 112 /* 113 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 114 * indicated by the interrupt routing model for BL31. 115 */ 116 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 117 #endif 118 119 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 120 /* Get Memory Tagging Extension support level */ 121 unsigned int mte = get_armv8_5_mte_support(); 122 #endif 123 /* 124 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 125 * is set, or when MTE is only implemented at EL0. 126 */ 127 #if CTX_INCLUDE_MTE_REGS 128 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 129 scr_el3 |= SCR_ATA_BIT; 130 #else 131 if (mte == MTE_IMPLEMENTED_EL0) { 132 scr_el3 |= SCR_ATA_BIT; 133 } 134 #endif /* CTX_INCLUDE_MTE_REGS */ 135 136 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 137 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) { 138 if (GET_RW(ep->spsr) != MODE_RW_64) { 139 ERROR("S-EL2 can not be used in AArch32\n."); 140 panic(); 141 } 142 143 scr_el3 |= SCR_EEL2_BIT; 144 } 145 146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 147 148 /* 149 * Initialize EL1 context registers unless SPMC is running 150 * at S-EL2. 151 */ 152 #if !SPMD_SPM_AT_SEL2 153 setup_el1_context(ctx, ep); 154 #endif 155 156 manage_extensions_secure(ctx); 157 } 158 159 #if ENABLE_RME 160 /****************************************************************************** 161 * This function performs initializations that are specific to REALM state 162 * and updates the cpu context specified by 'ctx'. 163 *****************************************************************************/ 164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 165 { 166 u_register_t scr_el3; 167 el3_state_t *state; 168 169 state = get_el3state_ctx(ctx); 170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 173 174 #if ENABLE_FEAT_CSV2_2 175 /* Enable access to the SCXTNUM_ELx registers. */ 176 scr_el3 |= SCR_EnSCXT_BIT; 177 #endif 178 179 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 180 } 181 #endif /* ENABLE_RME */ 182 183 /****************************************************************************** 184 * This function performs initializations that are specific to NON-SECURE state 185 * and updates the cpu context specified by 'ctx'. 186 *****************************************************************************/ 187 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 188 { 189 u_register_t scr_el3; 190 el3_state_t *state; 191 192 state = get_el3state_ctx(ctx); 193 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 194 195 /* SCR_NS: Set the NS bit */ 196 scr_el3 |= SCR_NS_BIT; 197 198 #if !CTX_INCLUDE_PAUTH_REGS 199 /* 200 * If the pointer authentication registers aren't saved during world 201 * switches the value of the registers can be leaked from the Secure to 202 * the Non-secure world. To prevent this, rather than enabling pointer 203 * authentication everywhere, we only enable it in the Non-secure world. 204 * 205 * If the Secure world wants to use pointer authentication, 206 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 207 */ 208 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 209 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 210 211 /* Allow access to Allocation Tags when MTE is implemented. */ 212 scr_el3 |= SCR_ATA_BIT; 213 214 #if HANDLE_EA_EL3_FIRST_NS 215 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 216 scr_el3 |= SCR_EA_BIT; 217 #endif 218 219 #if RAS_TRAP_NS_ERR_REC_ACCESS 220 /* 221 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 222 * and RAS ERX registers from EL1 and EL2(from any security state) 223 * are trapped to EL3. 224 * Set here to trap only for NS EL1/EL2 225 * 226 */ 227 scr_el3 |= SCR_TERR_BIT; 228 #endif 229 230 #if ENABLE_FEAT_CSV2_2 231 /* Enable access to the SCXTNUM_ELx registers. */ 232 scr_el3 |= SCR_EnSCXT_BIT; 233 #endif 234 235 #ifdef IMAGE_BL31 236 /* 237 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 238 * indicated by the interrupt routing model for BL31. 239 */ 240 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 241 #endif 242 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 243 244 /* Initialize EL1 context registers */ 245 setup_el1_context(ctx, ep); 246 247 /* Initialize EL2 context registers */ 248 #if CTX_INCLUDE_EL2_REGS 249 250 /* 251 * Initialize SCTLR_EL2 context register using Endianness value 252 * taken from the entrypoint attribute. 253 */ 254 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 255 sctlr_el2 |= SCTLR_EL2_RES1; 256 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 257 sctlr_el2); 258 259 /* 260 * Program the ICC_SRE_EL2 to make sure the correct bits are set 261 * when restoring NS context. 262 */ 263 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 264 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 265 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 266 icc_sre_el2); 267 268 /* 269 * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't 270 * throw anyone off who expects this to be sensible. 271 * TODO: A similar thing happens in cm_prepare_el3_exit. They should be 272 * unified with the proper PMU implementation 273 */ 274 u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & 275 PMCR_EL0_N_MASK); 276 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2); 277 #endif /* CTX_INCLUDE_EL2_REGS */ 278 } 279 280 /******************************************************************************* 281 * The following function performs initialization of the cpu_context 'ctx' 282 * for first use that is common to all security states, and sets the 283 * initial entrypoint state as specified by the entry_point_info structure. 284 * 285 * The EE and ST attributes are used to configure the endianness and secure 286 * timer availability for the new execution context. 287 ******************************************************************************/ 288 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 289 { 290 u_register_t scr_el3; 291 el3_state_t *state; 292 gp_regs_t *gp_regs; 293 294 /* Clear any residual register values from the context */ 295 zeromem(ctx, sizeof(*ctx)); 296 297 /* 298 * SCR_EL3 was initialised during reset sequence in macro 299 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 300 * affect the next EL. 301 * 302 * The following fields are initially set to zero and then updated to 303 * the required value depending on the state of the SPSR_EL3 and the 304 * Security state and entrypoint attributes of the next EL. 305 */ 306 scr_el3 = read_scr(); 307 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 308 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 309 310 /* 311 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 312 * Exception level as specified by SPSR. 313 */ 314 if (GET_RW(ep->spsr) == MODE_RW_64) { 315 scr_el3 |= SCR_RW_BIT; 316 } 317 318 /* 319 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 320 * Secure timer registers to EL3, from AArch64 state only, if specified 321 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 322 * bit always behaves as 1 (i.e. secure physical timer register access 323 * is not trapped) 324 */ 325 if (EP_GET_ST(ep->h.attr) != 0U) { 326 scr_el3 |= SCR_ST_BIT; 327 } 328 329 /* 330 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 331 * SCR_EL3.HXEn. 332 */ 333 if (is_feat_hcx_supported()) { 334 scr_el3 |= SCR_HXEn_BIT; 335 } 336 337 /* 338 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 339 * registers are trapped to EL3. 340 */ 341 #if ENABLE_FEAT_RNG_TRAP 342 scr_el3 |= SCR_TRNDR_BIT; 343 #endif 344 345 #if FAULT_INJECTION_SUPPORT 346 /* Enable fault injection from lower ELs */ 347 scr_el3 |= SCR_FIEN_BIT; 348 #endif 349 350 /* 351 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 352 */ 353 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 354 scr_el3 |= SCR_TCR2EN_BIT; 355 } 356 357 /* 358 * CPTR_EL3 was initialized out of reset, copy that value to the 359 * context register. 360 */ 361 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 362 363 /* 364 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 365 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 366 * next mode is Hyp. 367 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 368 * same conditions as HVC instructions and when the processor supports 369 * ARMv8.6-FGT. 370 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 371 * CNTPOFF_EL2 register under the same conditions as HVC instructions 372 * and when the processor supports ECV. 373 */ 374 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 375 || ((GET_RW(ep->spsr) != MODE_RW_64) 376 && (GET_M32(ep->spsr) == MODE32_hyp))) { 377 scr_el3 |= SCR_HCE_BIT; 378 379 if (is_feat_fgt_supported()) { 380 scr_el3 |= SCR_FGTEN_BIT; 381 } 382 383 if (get_armv8_6_ecv_support() 384 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 385 scr_el3 |= SCR_ECVEN_BIT; 386 } 387 } 388 389 #if ENABLE_FEAT_TWED 390 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 391 /* Set delay in SCR_EL3 */ 392 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 393 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 394 << SCR_TWEDEL_SHIFT); 395 396 /* Enable WFE delay */ 397 scr_el3 |= SCR_TWEDEn_BIT; 398 #endif /* ENABLE_FEAT_TWED */ 399 400 /* 401 * Populate EL3 state so that we've the right context 402 * before doing ERET 403 */ 404 state = get_el3state_ctx(ctx); 405 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 406 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 407 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 408 409 /* 410 * Store the X0-X7 value from the entrypoint into the context 411 * Use memcpy as we are in control of the layout of the structures 412 */ 413 gp_regs = get_gpregs_ctx(ctx); 414 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 415 } 416 417 /******************************************************************************* 418 * Context management library initialization routine. This library is used by 419 * runtime services to share pointers to 'cpu_context' structures for secure 420 * non-secure and realm states. Management of the structures and their associated 421 * memory is not done by the context management library e.g. the PSCI service 422 * manages the cpu context used for entry from and exit to the non-secure state. 423 * The Secure payload dispatcher service manages the context(s) corresponding to 424 * the secure state. It also uses this library to get access to the non-secure 425 * state cpu context pointers. 426 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 427 * which will be used for programming an entry into a lower EL. The same context 428 * will be used to save state upon exception entry from that EL. 429 ******************************************************************************/ 430 void __init cm_init(void) 431 { 432 /* 433 * The context management library has only global data to intialize, but 434 * that will be done when the BSS is zeroed out. 435 */ 436 } 437 438 /******************************************************************************* 439 * This is the high-level function used to initialize the cpu_context 'ctx' for 440 * first use. It performs initializations that are common to all security states 441 * and initializations specific to the security state specified in 'ep' 442 ******************************************************************************/ 443 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 444 { 445 unsigned int security_state; 446 447 assert(ctx != NULL); 448 449 /* 450 * Perform initializations that are common 451 * to all security states 452 */ 453 setup_context_common(ctx, ep); 454 455 security_state = GET_SECURITY_STATE(ep->h.attr); 456 457 /* Perform security state specific initializations */ 458 switch (security_state) { 459 case SECURE: 460 setup_secure_context(ctx, ep); 461 break; 462 #if ENABLE_RME 463 case REALM: 464 setup_realm_context(ctx, ep); 465 break; 466 #endif 467 case NON_SECURE: 468 setup_ns_context(ctx, ep); 469 break; 470 default: 471 ERROR("Invalid security state\n"); 472 panic(); 473 break; 474 } 475 } 476 477 /******************************************************************************* 478 * Enable architecture extensions on first entry to Non-secure world. 479 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 480 * it is zero. 481 ******************************************************************************/ 482 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 483 { 484 #if IMAGE_BL31 485 if (is_feat_spe_supported()) { 486 spe_enable(el2_unused); 487 } 488 489 #if ENABLE_AMU 490 amu_enable(el2_unused, ctx); 491 #endif 492 493 #if ENABLE_SME_FOR_NS 494 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 495 sme_enable(ctx); 496 #elif ENABLE_SVE_FOR_NS 497 /* Enable SVE and FPU/SIMD for non-secure world. */ 498 sve_enable(ctx); 499 #endif 500 501 #if ENABLE_MPAM_FOR_LOWER_ELS 502 mpam_enable(el2_unused); 503 #endif 504 505 if (is_feat_trbe_supported()) { 506 trbe_enable(); 507 } 508 509 if (is_feat_brbe_supported()) { 510 brbe_enable(); 511 } 512 513 #if ENABLE_SYS_REG_TRACE_FOR_NS 514 sys_reg_trace_enable(ctx); 515 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ 516 517 if (is_feat_trf_supported()) { 518 trf_enable(); 519 } 520 #endif 521 } 522 523 /******************************************************************************* 524 * Enable architecture extensions on first entry to Secure world. 525 ******************************************************************************/ 526 static void manage_extensions_secure(cpu_context_t *ctx) 527 { 528 #if IMAGE_BL31 529 #if ENABLE_SME_FOR_NS 530 #if ENABLE_SME_FOR_SWD 531 /* 532 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must 533 * ensure SME, SVE, and FPU/SIMD context properly managed. 534 */ 535 sme_enable(ctx); 536 #else /* ENABLE_SME_FOR_SWD */ 537 /* 538 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can 539 * safely use the associated registers. 540 */ 541 sme_disable(ctx); 542 #endif /* ENABLE_SME_FOR_SWD */ 543 #elif ENABLE_SVE_FOR_NS 544 #if ENABLE_SVE_FOR_SWD 545 /* 546 * Enable SVE and FPU in secure context, secure manager must ensure that 547 * the SVE and FPU register contexts are properly managed. 548 */ 549 sve_enable(ctx); 550 #else /* ENABLE_SVE_FOR_SWD */ 551 /* 552 * Disable SVE and FPU in secure context so non-secure world can safely 553 * use them. 554 */ 555 sve_disable(ctx); 556 #endif /* ENABLE_SVE_FOR_SWD */ 557 #endif /* ENABLE_SVE_FOR_NS */ 558 #endif /* IMAGE_BL31 */ 559 } 560 561 /******************************************************************************* 562 * The following function initializes the cpu_context for a CPU specified by 563 * its `cpu_idx` for first use, and sets the initial entrypoint state as 564 * specified by the entry_point_info structure. 565 ******************************************************************************/ 566 void cm_init_context_by_index(unsigned int cpu_idx, 567 const entry_point_info_t *ep) 568 { 569 cpu_context_t *ctx; 570 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 571 cm_setup_context(ctx, ep); 572 } 573 574 /******************************************************************************* 575 * The following function initializes the cpu_context for the current CPU 576 * for first use, and sets the initial entrypoint state as specified by the 577 * entry_point_info structure. 578 ******************************************************************************/ 579 void cm_init_my_context(const entry_point_info_t *ep) 580 { 581 cpu_context_t *ctx; 582 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 583 cm_setup_context(ctx, ep); 584 } 585 586 /******************************************************************************* 587 * Prepare the CPU system registers for first entry into realm, secure, or 588 * normal world. 589 * 590 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 591 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 592 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 593 * For all entries, the EL1 registers are initialized from the cpu_context 594 ******************************************************************************/ 595 void cm_prepare_el3_exit(uint32_t security_state) 596 { 597 u_register_t sctlr_elx, scr_el3, mdcr_el2; 598 cpu_context_t *ctx = cm_get_context(security_state); 599 bool el2_unused = false; 600 uint64_t hcr_el2 = 0U; 601 602 assert(ctx != NULL); 603 604 if (security_state == NON_SECURE) { 605 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 606 CTX_SCR_EL3); 607 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 608 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 609 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 610 CTX_SCTLR_EL1); 611 sctlr_elx &= SCTLR_EE_BIT; 612 sctlr_elx |= SCTLR_EL2_RES1; 613 #if ERRATA_A75_764081 614 /* 615 * If workaround of errata 764081 for Cortex-A75 is used 616 * then set SCTLR_EL2.IESB to enable Implicit Error 617 * Synchronization Barrier. 618 */ 619 sctlr_elx |= SCTLR_IESB_BIT; 620 #endif 621 write_sctlr_el2(sctlr_elx); 622 } else if (el_implemented(2) != EL_IMPL_NONE) { 623 el2_unused = true; 624 625 /* 626 * EL2 present but unused, need to disable safely. 627 * SCTLR_EL2 can be ignored in this case. 628 * 629 * Set EL2 register width appropriately: Set HCR_EL2 630 * field to match SCR_EL3.RW. 631 */ 632 if ((scr_el3 & SCR_RW_BIT) != 0U) 633 hcr_el2 |= HCR_RW_BIT; 634 635 /* 636 * For Armv8.3 pointer authentication feature, disable 637 * traps to EL2 when accessing key registers or using 638 * pointer authentication instructions from lower ELs. 639 */ 640 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 641 642 write_hcr_el2(hcr_el2); 643 644 /* 645 * Initialise CPTR_EL2 setting all fields rather than 646 * relying on the hw. All fields have architecturally 647 * UNKNOWN reset values. 648 * 649 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 650 * accesses to the CPACR_EL1 or CPACR from both 651 * Execution states do not trap to EL2. 652 * 653 * CPTR_EL2.TTA: Set to zero so that Non-secure System 654 * register accesses to the trace registers from both 655 * Execution states do not trap to EL2. 656 * If PE trace unit System registers are not implemented 657 * then this bit is reserved, and must be set to zero. 658 * 659 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 660 * to SIMD and floating-point functionality from both 661 * Execution states do not trap to EL2. 662 */ 663 write_cptr_el2(CPTR_EL2_RESET_VAL & 664 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 665 | CPTR_EL2_TFP_BIT)); 666 667 /* 668 * Initialise CNTHCTL_EL2. All fields are 669 * architecturally UNKNOWN on reset and are set to zero 670 * except for field(s) listed below. 671 * 672 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 673 * Hyp mode of Non-secure EL0 and EL1 accesses to the 674 * physical timer registers. 675 * 676 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 677 * Hyp mode of Non-secure EL0 and EL1 accesses to the 678 * physical counter registers. 679 */ 680 write_cnthctl_el2(CNTHCTL_RESET_VAL | 681 EL1PCEN_BIT | EL1PCTEN_BIT); 682 683 /* 684 * Initialise CNTVOFF_EL2 to zero as it resets to an 685 * architecturally UNKNOWN value. 686 */ 687 write_cntvoff_el2(0); 688 689 /* 690 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 691 * MPIDR_EL1 respectively. 692 */ 693 write_vpidr_el2(read_midr_el1()); 694 write_vmpidr_el2(read_mpidr_el1()); 695 696 /* 697 * Initialise VTTBR_EL2. All fields are architecturally 698 * UNKNOWN on reset. 699 * 700 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 701 * 2 address translation is disabled, cache maintenance 702 * operations depend on the VMID. 703 * 704 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 705 * translation is disabled. 706 */ 707 write_vttbr_el2(VTTBR_RESET_VAL & 708 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 709 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 710 711 /* 712 * Initialise MDCR_EL2, setting all fields rather than 713 * relying on hw. Some fields are architecturally 714 * UNKNOWN on reset. 715 * 716 * MDCR_EL2.HLP: Set to one so that event counter 717 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 718 * occurs on the increment that changes 719 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 720 * implemented. This bit is RES0 in versions of the 721 * architecture earlier than ARMv8.5, setting it to 1 722 * doesn't have any effect on them. 723 * 724 * MDCR_EL2.TTRF: Set to zero so that access to Trace 725 * Filter Control register TRFCR_EL1 at EL1 is not 726 * trapped to EL2. This bit is RES0 in versions of 727 * the architecture earlier than ARMv8.4. 728 * 729 * MDCR_EL2.HPMD: Set to one so that event counting is 730 * prohibited at EL2. This bit is RES0 in versions of 731 * the architecture earlier than ARMv8.1, setting it 732 * to 1 doesn't have any effect on them. 733 * 734 * MDCR_EL2.TPMS: Set to zero so that accesses to 735 * Statistical Profiling control registers from EL1 736 * do not trap to EL2. This bit is RES0 when SPE is 737 * not implemented. 738 * 739 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 740 * EL1 System register accesses to the Debug ROM 741 * registers are not trapped to EL2. 742 * 743 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 744 * System register accesses to the powerdown debug 745 * registers are not trapped to EL2. 746 * 747 * MDCR_EL2.TDA: Set to zero so that System register 748 * accesses to the debug registers do not trap to EL2. 749 * 750 * MDCR_EL2.TDE: Set to zero so that debug exceptions 751 * are not routed to EL2. 752 * 753 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 754 * Monitors. 755 * 756 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 757 * EL1 accesses to all Performance Monitors registers 758 * are not trapped to EL2. 759 * 760 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 761 * and EL1 accesses to the PMCR_EL0 or PMCR are not 762 * trapped to EL2. 763 * 764 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 765 * architecturally-defined reset value. 766 * 767 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 768 * owning exception level is NS-EL1 and, tracing is 769 * prohibited at NS-EL2. These bits are RES0 when 770 * FEAT_TRBE is not implemented. 771 */ 772 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 773 MDCR_EL2_HPMD) | 774 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 775 >> PMCR_EL0_N_SHIFT)) & 776 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 777 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 778 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 779 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 780 MDCR_EL2_TPMCR_BIT | 781 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 782 783 write_mdcr_el2(mdcr_el2); 784 785 /* 786 * Initialise HSTR_EL2. All fields are architecturally 787 * UNKNOWN on reset. 788 * 789 * HSTR_EL2.T<n>: Set all these fields to zero so that 790 * Non-secure EL0 or EL1 accesses to System registers 791 * do not trap to EL2. 792 */ 793 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 794 /* 795 * Initialise CNTHP_CTL_EL2. All fields are 796 * architecturally UNKNOWN on reset. 797 * 798 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 799 * physical timer and prevent timer interrupts. 800 */ 801 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 802 ~(CNTHP_CTL_ENABLE_BIT)); 803 } 804 manage_extensions_nonsecure(el2_unused, ctx); 805 } 806 807 cm_el1_sysregs_context_restore(security_state); 808 cm_set_next_eret_context(security_state); 809 } 810 811 #if CTX_INCLUDE_EL2_REGS 812 813 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 814 { 815 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 816 if (is_feat_amu_supported()) { 817 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 818 } 819 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 820 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 821 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 822 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 823 } 824 825 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 826 { 827 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 828 if (is_feat_amu_supported()) { 829 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 830 } 831 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 832 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 833 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 834 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 835 } 836 837 /******************************************************************************* 838 * Save EL2 sysreg context 839 ******************************************************************************/ 840 void cm_el2_sysregs_context_save(uint32_t security_state) 841 { 842 u_register_t scr_el3 = read_scr(); 843 844 /* 845 * Always save the non-secure and realm EL2 context, only save the 846 * S-EL2 context if S-EL2 is enabled. 847 */ 848 if ((security_state != SECURE) || 849 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 850 cpu_context_t *ctx; 851 el2_sysregs_t *el2_sysregs_ctx; 852 853 ctx = cm_get_context(security_state); 854 assert(ctx != NULL); 855 856 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 857 858 el2_sysregs_context_save_common(el2_sysregs_ctx); 859 #if CTX_INCLUDE_MTE_REGS 860 el2_sysregs_context_save_mte(el2_sysregs_ctx); 861 #endif 862 #if ENABLE_MPAM_FOR_LOWER_ELS 863 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 864 #endif 865 866 if (is_feat_fgt_supported()) { 867 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 868 } 869 870 #if ENABLE_FEAT_ECV 871 el2_sysregs_context_save_ecv(el2_sysregs_ctx); 872 #endif 873 #if ENABLE_FEAT_VHE 874 el2_sysregs_context_save_vhe(el2_sysregs_ctx); 875 #endif 876 #if RAS_EXTENSION 877 el2_sysregs_context_save_ras(el2_sysregs_ctx); 878 #endif 879 #if CTX_INCLUDE_NEVE_REGS 880 el2_sysregs_context_save_nv2(el2_sysregs_ctx); 881 #endif 882 if (is_feat_trf_supported()) { 883 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 884 } 885 #if ENABLE_FEAT_CSV2_2 886 el2_sysregs_context_save_csv2(el2_sysregs_ctx); 887 #endif 888 if (is_feat_hcx_supported()) { 889 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 890 } 891 if (is_feat_tcr2_supported()) { 892 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 893 } 894 } 895 } 896 897 /******************************************************************************* 898 * Restore EL2 sysreg context 899 ******************************************************************************/ 900 void cm_el2_sysregs_context_restore(uint32_t security_state) 901 { 902 u_register_t scr_el3 = read_scr(); 903 904 /* 905 * Always restore the non-secure and realm EL2 context, only restore the 906 * S-EL2 context if S-EL2 is enabled. 907 */ 908 if ((security_state != SECURE) || 909 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 910 cpu_context_t *ctx; 911 el2_sysregs_t *el2_sysregs_ctx; 912 913 ctx = cm_get_context(security_state); 914 assert(ctx != NULL); 915 916 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 917 918 el2_sysregs_context_restore_common(el2_sysregs_ctx); 919 #if CTX_INCLUDE_MTE_REGS 920 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 921 #endif 922 #if ENABLE_MPAM_FOR_LOWER_ELS 923 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 924 #endif 925 926 if (is_feat_fgt_supported()) { 927 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 928 } 929 930 #if ENABLE_FEAT_ECV 931 el2_sysregs_context_restore_ecv(el2_sysregs_ctx); 932 #endif 933 #if ENABLE_FEAT_VHE 934 el2_sysregs_context_restore_vhe(el2_sysregs_ctx); 935 #endif 936 #if RAS_EXTENSION 937 el2_sysregs_context_restore_ras(el2_sysregs_ctx); 938 #endif 939 #if CTX_INCLUDE_NEVE_REGS 940 el2_sysregs_context_restore_nv2(el2_sysregs_ctx); 941 #endif 942 if (is_feat_trf_supported()) { 943 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 944 } 945 #if ENABLE_FEAT_CSV2_2 946 el2_sysregs_context_restore_csv2(el2_sysregs_ctx); 947 #endif 948 if (is_feat_hcx_supported()) { 949 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 950 } 951 if (is_feat_tcr2_supported()) { 952 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 953 } 954 } 955 } 956 #endif /* CTX_INCLUDE_EL2_REGS */ 957 958 /******************************************************************************* 959 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 960 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 961 * updating EL1 and EL2 registers. Otherwise, it calls the generic 962 * cm_prepare_el3_exit function. 963 ******************************************************************************/ 964 void cm_prepare_el3_exit_ns(void) 965 { 966 #if CTX_INCLUDE_EL2_REGS 967 cpu_context_t *ctx = cm_get_context(NON_SECURE); 968 assert(ctx != NULL); 969 970 /* Assert that EL2 is used. */ 971 #if ENABLE_ASSERTIONS 972 el3_state_t *state = get_el3state_ctx(ctx); 973 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 974 #endif 975 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 976 (el_implemented(2U) != EL_IMPL_NONE)); 977 978 /* 979 * Currently some extensions are configured using 980 * direct register updates. Therefore, do this here 981 * instead of when setting up context. 982 */ 983 manage_extensions_nonsecure(0, ctx); 984 985 /* 986 * Set the NS bit to be able to access the ICC_SRE_EL2 987 * register when restoring context. 988 */ 989 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 990 991 /* 992 * Ensure the NS bit change is committed before the EL2/EL1 993 * state restoration. 994 */ 995 isb(); 996 997 /* Restore EL2 and EL1 sysreg contexts */ 998 cm_el2_sysregs_context_restore(NON_SECURE); 999 cm_el1_sysregs_context_restore(NON_SECURE); 1000 cm_set_next_eret_context(NON_SECURE); 1001 #else 1002 cm_prepare_el3_exit(NON_SECURE); 1003 #endif /* CTX_INCLUDE_EL2_REGS */ 1004 } 1005 1006 /******************************************************************************* 1007 * The next four functions are used by runtime services to save and restore 1008 * EL1 context on the 'cpu_context' structure for the specified security 1009 * state. 1010 ******************************************************************************/ 1011 void cm_el1_sysregs_context_save(uint32_t security_state) 1012 { 1013 cpu_context_t *ctx; 1014 1015 ctx = cm_get_context(security_state); 1016 assert(ctx != NULL); 1017 1018 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1019 1020 #if IMAGE_BL31 1021 if (security_state == SECURE) 1022 PUBLISH_EVENT(cm_exited_secure_world); 1023 else 1024 PUBLISH_EVENT(cm_exited_normal_world); 1025 #endif 1026 } 1027 1028 void cm_el1_sysregs_context_restore(uint32_t security_state) 1029 { 1030 cpu_context_t *ctx; 1031 1032 ctx = cm_get_context(security_state); 1033 assert(ctx != NULL); 1034 1035 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1036 1037 #if IMAGE_BL31 1038 if (security_state == SECURE) 1039 PUBLISH_EVENT(cm_entering_secure_world); 1040 else 1041 PUBLISH_EVENT(cm_entering_normal_world); 1042 #endif 1043 } 1044 1045 /******************************************************************************* 1046 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1047 * given security state with the given entrypoint 1048 ******************************************************************************/ 1049 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1050 { 1051 cpu_context_t *ctx; 1052 el3_state_t *state; 1053 1054 ctx = cm_get_context(security_state); 1055 assert(ctx != NULL); 1056 1057 /* Populate EL3 state so that ERET jumps to the correct entry */ 1058 state = get_el3state_ctx(ctx); 1059 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1060 } 1061 1062 /******************************************************************************* 1063 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1064 * pertaining to the given security state 1065 ******************************************************************************/ 1066 void cm_set_elr_spsr_el3(uint32_t security_state, 1067 uintptr_t entrypoint, uint32_t spsr) 1068 { 1069 cpu_context_t *ctx; 1070 el3_state_t *state; 1071 1072 ctx = cm_get_context(security_state); 1073 assert(ctx != NULL); 1074 1075 /* Populate EL3 state so that ERET jumps to the correct entry */ 1076 state = get_el3state_ctx(ctx); 1077 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1078 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1079 } 1080 1081 /******************************************************************************* 1082 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1083 * pertaining to the given security state using the value and bit position 1084 * specified in the parameters. It preserves all other bits. 1085 ******************************************************************************/ 1086 void cm_write_scr_el3_bit(uint32_t security_state, 1087 uint32_t bit_pos, 1088 uint32_t value) 1089 { 1090 cpu_context_t *ctx; 1091 el3_state_t *state; 1092 u_register_t scr_el3; 1093 1094 ctx = cm_get_context(security_state); 1095 assert(ctx != NULL); 1096 1097 /* Ensure that the bit position is a valid one */ 1098 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1099 1100 /* Ensure that the 'value' is only a bit wide */ 1101 assert(value <= 1U); 1102 1103 /* 1104 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1105 * and set it to its new value. 1106 */ 1107 state = get_el3state_ctx(ctx); 1108 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1109 scr_el3 &= ~(1UL << bit_pos); 1110 scr_el3 |= (u_register_t)value << bit_pos; 1111 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1112 } 1113 1114 /******************************************************************************* 1115 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1116 * given security state. 1117 ******************************************************************************/ 1118 u_register_t cm_get_scr_el3(uint32_t security_state) 1119 { 1120 cpu_context_t *ctx; 1121 el3_state_t *state; 1122 1123 ctx = cm_get_context(security_state); 1124 assert(ctx != NULL); 1125 1126 /* Populate EL3 state so that ERET jumps to the correct entry */ 1127 state = get_el3state_ctx(ctx); 1128 return read_ctx_reg(state, CTX_SCR_EL3); 1129 } 1130 1131 /******************************************************************************* 1132 * This function is used to program the context that's used for exception 1133 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1134 * the required security state 1135 ******************************************************************************/ 1136 void cm_set_next_eret_context(uint32_t security_state) 1137 { 1138 cpu_context_t *ctx; 1139 1140 ctx = cm_get_context(security_state); 1141 assert(ctx != NULL); 1142 1143 cm_set_next_context(ctx); 1144 } 1145