1# 2# Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are met: 6# 7# Redistributions of source code must retain the above copyright notice, this 8# list of conditions and the following disclaimer. 9# 10# Redistributions in binary form must reproduce the above copyright notice, 11# this list of conditions and the following disclaimer in the documentation 12# and/or other materials provided with the distribution. 13# 14# Neither the name of ARM nor the names of its contributors may be used 15# to endorse or promote products derived from this software without specific 16# prior written permission. 17# 18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28# POSSIBILITY OF SUCH DAMAGE. 29# 30 31# Cortex A57 specific optimisation to skip L1 cache flush when 32# cluster is powered down. 33SKIP_A57_L1_FLUSH_PWR_DWN ?=0 34 35# Flag to disable the cache non-temporal hint. 36# It is enabled by default. 37A53_DISABLE_NON_TEMPORAL_HINT ?=1 38 39# Flag to disable the cache non-temporal hint. 40# It is enabled by default. 41A57_DISABLE_NON_TEMPORAL_HINT ?=1 42 43# Process SKIP_A57_L1_FLUSH_PWR_DWN flag 44$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) 45$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) 46 47# Process A53_DISABLE_NON_TEMPORAL_HINT flag 48$(eval $(call assert_boolean,A53_DISABLE_NON_TEMPORAL_HINT)) 49$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT)) 50 51# Process A57_DISABLE_NON_TEMPORAL_HINT flag 52$(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT)) 53$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT)) 54 55 56# CPU Errata Build flags. These should be enabled by the 57# platform if the errata needs to be applied. 58 59# Flag to apply errata 826319 during reset. This errata applies only to 60# revision <= r0p2 of the Cortex A53 cpu. 61ERRATA_A53_826319 ?=0 62 63# Flag to apply errata 836870 during reset. This errata applies only to 64# revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this 65# errata is enabled by default. 66ERRATA_A53_836870 ?=0 67 68# Flag to apply errata 806969 during reset. This errata applies only to 69# revision r0p0 of the Cortex A57 cpu. 70ERRATA_A57_806969 ?=0 71 72# Flag to apply errata 813420 during reset. This errata applies only to 73# revision r0p0 of the Cortex A57 cpu. 74ERRATA_A57_813420 ?=0 75 76# Process ERRATA_A53_826319 flag 77$(eval $(call assert_boolean,ERRATA_A53_826319)) 78$(eval $(call add_define,ERRATA_A53_826319)) 79 80# Process ERRATA_A53_836870 flag 81$(eval $(call assert_boolean,ERRATA_A53_836870)) 82$(eval $(call add_define,ERRATA_A53_836870)) 83 84# Process ERRATA_A57_806969 flag 85$(eval $(call assert_boolean,ERRATA_A57_806969)) 86$(eval $(call add_define,ERRATA_A57_806969)) 87 88# Process ERRATA_A57_813420 flag 89$(eval $(call assert_boolean,ERRATA_A57_813420)) 90$(eval $(call add_define,ERRATA_A57_813420)) 91