1# 2# Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Cortex A57 specific optimisation to skip L1 cache flush when 8# cluster is powered down. 9SKIP_A57_L1_FLUSH_PWR_DWN ?=0 10 11# Flag to disable the cache non-temporal hint. 12# It is enabled by default. 13A53_DISABLE_NON_TEMPORAL_HINT ?=1 14 15# Flag to disable the cache non-temporal hint. 16# It is enabled by default. 17A57_DISABLE_NON_TEMPORAL_HINT ?=1 18 19WORKAROUND_CVE_2017_5715 ?=1 20 21# Process SKIP_A57_L1_FLUSH_PWR_DWN flag 22$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) 23$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) 24 25# Process A53_DISABLE_NON_TEMPORAL_HINT flag 26$(eval $(call assert_boolean,A53_DISABLE_NON_TEMPORAL_HINT)) 27$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT)) 28 29# Process A57_DISABLE_NON_TEMPORAL_HINT flag 30$(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT)) 31$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT)) 32 33# Process WORKAROUND_CVE_2017_5715 flag 34$(eval $(call assert_boolean,WORKAROUND_CVE_2017_5715)) 35$(eval $(call add_define,WORKAROUND_CVE_2017_5715)) 36 37# CPU Errata Build flags. 38# These should be enabled by the platform if the erratum workaround needs to be 39# applied. 40 41# Flag to apply erratum 826319 workaround during reset. This erratum applies 42# only to revision <= r0p2 of the Cortex A53 cpu. 43ERRATA_A53_826319 ?=0 44 45# Flag to apply erratum 835769 workaround at compile and link time. This 46# erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this 47# workaround can lead the linker to create "*.stub" sections. 48ERRATA_A53_835769 ?=0 49 50# Flag to apply erratum 836870 workaround during reset. This erratum applies 51# only to revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this 52# erratum workaround is enabled by default in hardware. 53ERRATA_A53_836870 ?=0 54 55# Flag to apply erratum 843419 workaround at link time. 56# This erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this 57# workaround could lead the linker to emit "*.stub" sections which are 4kB 58# aligned. 59ERRATA_A53_843419 ?=0 60 61# Flag to apply errata 855873 during reset. This errata applies to all 62# revisions of the Cortex A53 CPU, but this firmware workaround only works 63# for revisions r0p3 and higher. Earlier revisions are taken care 64# of by the rich OS. 65ERRATA_A53_855873 ?=0 66 67# Flag to apply erratum 806969 workaround during reset. This erratum applies 68# only to revision r0p0 of the Cortex A57 cpu. 69ERRATA_A57_806969 ?=0 70 71# Flag to apply erratum 813419 workaround during reset. This erratum applies 72# only to revision r0p0 of the Cortex A57 cpu. 73ERRATA_A57_813419 ?=0 74 75# Flag to apply erratum 813420 workaround during reset. This erratum applies 76# only to revision r0p0 of the Cortex A57 cpu. 77ERRATA_A57_813420 ?=0 78 79# Flag to apply erratum 826974 workaround during reset. This erratum applies 80# only to revision <= r1p1 of the Cortex A57 cpu. 81ERRATA_A57_826974 ?=0 82 83# Flag to apply erratum 826977 workaround during reset. This erratum applies 84# only to revision <= r1p1 of the Cortex A57 cpu. 85ERRATA_A57_826977 ?=0 86 87# Flag to apply erratum 828024 workaround during reset. This erratum applies 88# only to revision <= r1p1 of the Cortex A57 cpu. 89ERRATA_A57_828024 ?=0 90 91# Flag to apply erratum 829520 workaround during reset. This erratum applies 92# only to revision <= r1p2 of the Cortex A57 cpu. 93ERRATA_A57_829520 ?=0 94 95# Flag to apply erratum 833471 workaround during reset. This erratum applies 96# only to revision <= r1p2 of the Cortex A57 cpu. 97ERRATA_A57_833471 ?=0 98 99# Flag to apply erratum 855972 workaround during reset. This erratum applies 100# only to revision <= r1p3 of the Cortex A57 cpu. 101ERRATA_A57_859972 ?=0 102 103# Flag to apply erratum 855971 workaround during reset. This erratum applies 104# only to revision <= r0p3 of the Cortex A72 cpu. 105ERRATA_A72_859971 ?=0 106 107# Process ERRATA_A53_826319 flag 108$(eval $(call assert_boolean,ERRATA_A53_826319)) 109$(eval $(call add_define,ERRATA_A53_826319)) 110 111# Process ERRATA_A53_835769 flag 112$(eval $(call assert_boolean,ERRATA_A53_835769)) 113$(eval $(call add_define,ERRATA_A53_835769)) 114 115# Process ERRATA_A53_836870 flag 116$(eval $(call assert_boolean,ERRATA_A53_836870)) 117$(eval $(call add_define,ERRATA_A53_836870)) 118 119# Process ERRATA_A53_843419 flag 120$(eval $(call assert_boolean,ERRATA_A53_843419)) 121$(eval $(call add_define,ERRATA_A53_843419)) 122 123# Process ERRATA_A53_855873 flag 124$(eval $(call assert_boolean,ERRATA_A53_855873)) 125$(eval $(call add_define,ERRATA_A53_855873)) 126 127# Process ERRATA_A57_806969 flag 128$(eval $(call assert_boolean,ERRATA_A57_806969)) 129$(eval $(call add_define,ERRATA_A57_806969)) 130 131# Process ERRATA_A57_813419 flag 132$(eval $(call assert_boolean,ERRATA_A57_813419)) 133$(eval $(call add_define,ERRATA_A57_813419)) 134 135# Process ERRATA_A57_813420 flag 136$(eval $(call assert_boolean,ERRATA_A57_813420)) 137$(eval $(call add_define,ERRATA_A57_813420)) 138 139# Process ERRATA_A57_826974 flag 140$(eval $(call assert_boolean,ERRATA_A57_826974)) 141$(eval $(call add_define,ERRATA_A57_826974)) 142 143# Process ERRATA_A57_826977 flag 144$(eval $(call assert_boolean,ERRATA_A57_826977)) 145$(eval $(call add_define,ERRATA_A57_826977)) 146 147# Process ERRATA_A57_828024 flag 148$(eval $(call assert_boolean,ERRATA_A57_828024)) 149$(eval $(call add_define,ERRATA_A57_828024)) 150 151# Process ERRATA_A57_829520 flag 152$(eval $(call assert_boolean,ERRATA_A57_829520)) 153$(eval $(call add_define,ERRATA_A57_829520)) 154 155# Process ERRATA_A57_833471 flag 156$(eval $(call assert_boolean,ERRATA_A57_833471)) 157$(eval $(call add_define,ERRATA_A57_833471)) 158 159# Process ERRATA_A57_859972 flag 160$(eval $(call assert_boolean,ERRATA_A57_859972)) 161$(eval $(call add_define,ERRATA_A57_859972)) 162 163# Process ERRATA_A72_859971 flag 164$(eval $(call assert_boolean,ERRATA_A72_859971)) 165$(eval $(call add_define,ERRATA_A72_859971)) 166 167# Errata build flags 168ifneq (${ERRATA_A53_843419},0) 169TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419 170endif 171 172ifneq (${ERRATA_A53_835769},0) 173TF_CFLAGS_aarch64 += -mfix-cortex-a53-835769 174TF_LDFLAGS_aarch64 += --fix-cortex-a53-835769 175endif 176