1# 2# Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are met: 6# 7# Redistributions of source code must retain the above copyright notice, this 8# list of conditions and the following disclaimer. 9# 10# Redistributions in binary form must reproduce the above copyright notice, 11# this list of conditions and the following disclaimer in the documentation 12# and/or other materials provided with the distribution. 13# 14# Neither the name of ARM nor the names of its contributors may be used 15# to endorse or promote products derived from this software without specific 16# prior written permission. 17# 18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28# POSSIBILITY OF SUCH DAMAGE. 29# 30 31# Cortex A57 specific optimisation to skip L1 cache flush when 32# cluster is powered down. 33SKIP_A57_L1_FLUSH_PWR_DWN ?=0 34 35# Flag to disable the cache non-temporal hint. 36# It is enabled by default. 37A53_DISABLE_NON_TEMPORAL_HINT ?=1 38 39# Flag to disable the cache non-temporal hint. 40# It is enabled by default. 41A57_DISABLE_NON_TEMPORAL_HINT ?=1 42 43# Process SKIP_A57_L1_FLUSH_PWR_DWN flag 44$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) 45$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) 46 47# Process A53_DISABLE_NON_TEMPORAL_HINT flag 48$(eval $(call assert_boolean,A53_DISABLE_NON_TEMPORAL_HINT)) 49$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT)) 50 51# Process A57_DISABLE_NON_TEMPORAL_HINT flag 52$(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT)) 53$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT)) 54 55 56# CPU Errata Build flags. 57# These should be enabled by the platform if the erratum workaround needs to be 58# applied. 59 60# Flag to apply erratum 826319 workaround during reset. This erratum applies 61# only to revision <= r0p2 of the Cortex A53 cpu. 62ERRATA_A53_826319 ?=0 63 64# Flag to apply erratum 836870 workaround during reset. This erratum applies 65# only to revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this 66# erratum workaround is enabled by default in hardware. 67ERRATA_A53_836870 ?=0 68 69# Flag to apply errata 855873 during reset. This errata applies to all 70# revisions of the Cortex A53 CPU, but this firmware workaround only works 71# for revisions r0p3 and higher. Earlier revisions are taken care 72# of by the rich OS. 73ERRATA_A53_855873 ?=0 74 75# Flag to apply erratum 806969 workaround during reset. This erratum applies 76# only to revision r0p0 of the Cortex A57 cpu. 77ERRATA_A57_806969 ?=0 78 79# Flag to apply erratum 813419 workaround during reset. This erratum applies 80# only to revision r0p0 of the Cortex A57 cpu. 81ERRATA_A57_813419 ?=0 82 83# Flag to apply erratum 813420 workaround during reset. This erratum applies 84# only to revision r0p0 of the Cortex A57 cpu. 85ERRATA_A57_813420 ?=0 86 87# Flag to apply erratum 826974 workaround during reset. This erratum applies 88# only to revision <= r1p1 of the Cortex A57 cpu. 89ERRATA_A57_826974 ?=0 90 91# Flag to apply erratum 826977 workaround during reset. This erratum applies 92# only to revision <= r1p1 of the Cortex A57 cpu. 93ERRATA_A57_826977 ?=0 94 95# Flag to apply erratum 828024 workaround during reset. This erratum applies 96# only to revision <= r1p1 of the Cortex A57 cpu. 97ERRATA_A57_828024 ?=0 98 99# Flag to apply erratum 829520 workaround during reset. This erratum applies 100# only to revision <= r1p2 of the Cortex A57 cpu. 101ERRATA_A57_829520 ?=0 102 103# Flag to apply erratum 833471 workaround during reset. This erratum applies 104# only to revision <= r1p2 of the Cortex A57 cpu. 105ERRATA_A57_833471 ?=0 106 107# Process ERRATA_A53_826319 flag 108$(eval $(call assert_boolean,ERRATA_A53_826319)) 109$(eval $(call add_define,ERRATA_A53_826319)) 110 111# Process ERRATA_A53_836870 flag 112$(eval $(call assert_boolean,ERRATA_A53_836870)) 113$(eval $(call add_define,ERRATA_A53_836870)) 114 115# Process ERRATA_A53_855873 flag 116$(eval $(call assert_boolean,ERRATA_A53_855873)) 117$(eval $(call add_define,ERRATA_A53_855873)) 118 119# Process ERRATA_A57_806969 flag 120$(eval $(call assert_boolean,ERRATA_A57_806969)) 121$(eval $(call add_define,ERRATA_A57_806969)) 122 123# Process ERRATA_A57_813419 flag 124$(eval $(call assert_boolean,ERRATA_A57_813419)) 125$(eval $(call add_define,ERRATA_A57_813419)) 126 127# Process ERRATA_A57_813420 flag 128$(eval $(call assert_boolean,ERRATA_A57_813420)) 129$(eval $(call add_define,ERRATA_A57_813420)) 130 131# Process ERRATA_A57_826974 flag 132$(eval $(call assert_boolean,ERRATA_A57_826974)) 133$(eval $(call add_define,ERRATA_A57_826974)) 134 135# Process ERRATA_A57_826977 flag 136$(eval $(call assert_boolean,ERRATA_A57_826977)) 137$(eval $(call add_define,ERRATA_A57_826977)) 138 139# Process ERRATA_A57_828024 flag 140$(eval $(call assert_boolean,ERRATA_A57_828024)) 141$(eval $(call add_define,ERRATA_A57_828024)) 142 143# Process ERRATA_A57_829520 flag 144$(eval $(call assert_boolean,ERRATA_A57_829520)) 145$(eval $(call add_define,ERRATA_A57_829520)) 146 147# Process ERRATA_A57_833471 flag 148$(eval $(call assert_boolean,ERRATA_A57_833471)) 149$(eval $(call add_define,ERRATA_A57_833471)) 150