15541bb3fSSoby Mathew# 2*da6d75a0SJohn Tsichritzis# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 35541bb3fSSoby Mathew# 482cb2c1aSdp-arm# SPDX-License-Identifier: BSD-3-Clause 55541bb3fSSoby Mathew# 65541bb3fSSoby Mathew 75541bb3fSSoby Mathew# Cortex A57 specific optimisation to skip L1 cache flush when 85541bb3fSSoby Mathew# cluster is powered down. 95541bb3fSSoby MathewSKIP_A57_L1_FLUSH_PWR_DWN ?=0 105541bb3fSSoby Mathew 1154035fc4SSandrine Bailleux# Flag to disable the cache non-temporal hint. 1254035fc4SSandrine Bailleux# It is enabled by default. 1354035fc4SSandrine BailleuxA53_DISABLE_NON_TEMPORAL_HINT ?=1 1454035fc4SSandrine Bailleux 1554035fc4SSandrine Bailleux# Flag to disable the cache non-temporal hint. 1654035fc4SSandrine Bailleux# It is enabled by default. 1754035fc4SSandrine BailleuxA57_DISABLE_NON_TEMPORAL_HINT ?=1 1854035fc4SSandrine Bailleux 19f62ad322SDimitris PapastamosWORKAROUND_CVE_2017_5715 ?=1 20b8a25bbbSDimitris PapastamosWORKAROUND_CVE_2018_3639 ?=1 21fe007b2eSDimitris PapastamosDYNAMIC_WORKAROUND_CVE_2018_3639 ?=0 22f62ad322SDimitris Papastamos 235541bb3fSSoby Mathew# Process SKIP_A57_L1_FLUSH_PWR_DWN flag 245541bb3fSSoby Mathew$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) 255541bb3fSSoby Mathew$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) 265541bb3fSSoby Mathew 2754035fc4SSandrine Bailleux# Process A53_DISABLE_NON_TEMPORAL_HINT flag 2854035fc4SSandrine Bailleux$(eval $(call assert_boolean,A53_DISABLE_NON_TEMPORAL_HINT)) 2954035fc4SSandrine Bailleux$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT)) 3054035fc4SSandrine Bailleux 3154035fc4SSandrine Bailleux# Process A57_DISABLE_NON_TEMPORAL_HINT flag 3254035fc4SSandrine Bailleux$(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT)) 3354035fc4SSandrine Bailleux$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT)) 3454035fc4SSandrine Bailleux 35f62ad322SDimitris Papastamos# Process WORKAROUND_CVE_2017_5715 flag 36f62ad322SDimitris Papastamos$(eval $(call assert_boolean,WORKAROUND_CVE_2017_5715)) 37f62ad322SDimitris Papastamos$(eval $(call add_define,WORKAROUND_CVE_2017_5715)) 385541bb3fSSoby Mathew 39b8a25bbbSDimitris Papastamos# Process WORKAROUND_CVE_2018_3639 flag 40b8a25bbbSDimitris Papastamos$(eval $(call assert_boolean,WORKAROUND_CVE_2018_3639)) 41b8a25bbbSDimitris Papastamos$(eval $(call add_define,WORKAROUND_CVE_2018_3639)) 42b8a25bbbSDimitris Papastamos 43fe007b2eSDimitris Papastamos$(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639)) 44fe007b2eSDimitris Papastamos$(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639)) 45fe007b2eSDimitris Papastamos 46fe007b2eSDimitris Papastamosifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0) 47fe007b2eSDimitris Papastamos ifeq (${WORKAROUND_CVE_2018_3639},0) 48fe007b2eSDimitris Papastamos $(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1") 49fe007b2eSDimitris Papastamos endif 50fe007b2eSDimitris Papastamosendif 51fe007b2eSDimitris Papastamos 52097b787aSSandrine Bailleux# CPU Errata Build flags. 53097b787aSSandrine Bailleux# These should be enabled by the platform if the erratum workaround needs to be 54097b787aSSandrine Bailleux# applied. 555541bb3fSSoby Mathew 56097b787aSSandrine Bailleux# Flag to apply erratum 826319 workaround during reset. This erratum applies 57097b787aSSandrine Bailleux# only to revision <= r0p2 of the Cortex A53 cpu. 586b0d97b2SJimmy HuangERRATA_A53_826319 ?=0 596b0d97b2SJimmy Huang 60a94cc374SDouglas Raillard# Flag to apply erratum 835769 workaround at compile and link time. This 61a94cc374SDouglas Raillard# erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this 62a94cc374SDouglas Raillard# workaround can lead the linker to create "*.stub" sections. 63a94cc374SDouglas RaillardERRATA_A53_835769 ?=0 64a94cc374SDouglas Raillard 65097b787aSSandrine Bailleux# Flag to apply erratum 836870 workaround during reset. This erratum applies 66097b787aSSandrine Bailleux# only to revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this 673fbe46d7SDouglas Raillard# erratum workaround is enabled by default in hardware. 686b0d97b2SJimmy HuangERRATA_A53_836870 ?=0 696b0d97b2SJimmy Huang 70a94cc374SDouglas Raillard# Flag to apply erratum 843419 workaround at link time. 71a94cc374SDouglas Raillard# This erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this 72a94cc374SDouglas Raillard# workaround could lead the linker to emit "*.stub" sections which are 4kB 73a94cc374SDouglas Raillard# aligned. 74a94cc374SDouglas RaillardERRATA_A53_843419 ?=0 75a94cc374SDouglas Raillard 76b75dc0e4SAndre Przywara# Flag to apply errata 855873 during reset. This errata applies to all 77b75dc0e4SAndre Przywara# revisions of the Cortex A53 CPU, but this firmware workaround only works 78b75dc0e4SAndre Przywara# for revisions r0p3 and higher. Earlier revisions are taken care 79b75dc0e4SAndre Przywara# of by the rich OS. 80b75dc0e4SAndre PrzywaraERRATA_A53_855873 ?=0 81b75dc0e4SAndre Przywara 82097b787aSSandrine Bailleux# Flag to apply erratum 806969 workaround during reset. This erratum applies 83097b787aSSandrine Bailleux# only to revision r0p0 of the Cortex A57 cpu. 845541bb3fSSoby MathewERRATA_A57_806969 ?=0 855541bb3fSSoby Mathew 86ccbec91cSAntonio Nino Diaz# Flag to apply erratum 813419 workaround during reset. This erratum applies 87ccbec91cSAntonio Nino Diaz# only to revision r0p0 of the Cortex A57 cpu. 88ccbec91cSAntonio Nino DiazERRATA_A57_813419 ?=0 89ccbec91cSAntonio Nino Diaz 90097b787aSSandrine Bailleux# Flag to apply erratum 813420 workaround during reset. This erratum applies 91097b787aSSandrine Bailleux# only to revision r0p0 of the Cortex A57 cpu. 925541bb3fSSoby MathewERRATA_A57_813420 ?=0 935541bb3fSSoby Mathew 94df22d602SSandrine Bailleux# Flag to apply erratum 826974 workaround during reset. This erratum applies 95df22d602SSandrine Bailleux# only to revision <= r1p1 of the Cortex A57 cpu. 96df22d602SSandrine BailleuxERRATA_A57_826974 ?=0 97df22d602SSandrine Bailleux 9807288865SSandrine Bailleux# Flag to apply erratum 826977 workaround during reset. This erratum applies 9907288865SSandrine Bailleux# only to revision <= r1p1 of the Cortex A57 cpu. 10007288865SSandrine BailleuxERRATA_A57_826977 ?=0 10107288865SSandrine Bailleux 102a8b1c769SSandrine Bailleux# Flag to apply erratum 828024 workaround during reset. This erratum applies 103a8b1c769SSandrine Bailleux# only to revision <= r1p1 of the Cortex A57 cpu. 104a8b1c769SSandrine BailleuxERRATA_A57_828024 ?=0 105a8b1c769SSandrine Bailleux 1060b77197bSSandrine Bailleux# Flag to apply erratum 829520 workaround during reset. This erratum applies 1070b77197bSSandrine Bailleux# only to revision <= r1p2 of the Cortex A57 cpu. 1080b77197bSSandrine BailleuxERRATA_A57_829520 ?=0 1090b77197bSSandrine Bailleux 110adeecf92SSandrine Bailleux# Flag to apply erratum 833471 workaround during reset. This erratum applies 111adeecf92SSandrine Bailleux# only to revision <= r1p2 of the Cortex A57 cpu. 112adeecf92SSandrine BailleuxERRATA_A57_833471 ?=0 113adeecf92SSandrine Bailleux 11445b52c20SEleanor Bonnici# Flag to apply erratum 855972 workaround during reset. This erratum applies 11545b52c20SEleanor Bonnici# only to revision <= r1p3 of the Cortex A57 cpu. 11645b52c20SEleanor BonniciERRATA_A57_859972 ?=0 11745b52c20SEleanor Bonnici 1186de9b336SEleanor Bonnici# Flag to apply erratum 855971 workaround during reset. This erratum applies 1196de9b336SEleanor Bonnici# only to revision <= r0p3 of the Cortex A72 cpu. 1206de9b336SEleanor BonniciERRATA_A72_859971 ?=0 1216de9b336SEleanor Bonnici 122040b546eSDimitris Papastamos# Flag to apply T32 CLREX workaround during reset. This erratum applies 123*da6d75a0SJohn Tsichritzis# only to r0p0 and r1p0 of the Neoverse N1 cpu. 124*da6d75a0SJohn TsichritzisERRATA_N1_1043202 ?=1 125040b546eSDimitris Papastamos 1268a677180SJohn Tsichritzis# Flag to apply DSU erratum 936184. This erratum applies to DSUs containing 1278a677180SJohn Tsichritzis# the ACP interface and revision < r2p0. Applying the workaround results in 1288a677180SJohn Tsichritzis# higher DSU power consumption on idle. 1298a677180SJohn TsichritzisERRATA_DSU_936184 ?=0 1308a677180SJohn Tsichritzis 1316b0d97b2SJimmy Huang# Process ERRATA_A53_826319 flag 1326b0d97b2SJimmy Huang$(eval $(call assert_boolean,ERRATA_A53_826319)) 1336b0d97b2SJimmy Huang$(eval $(call add_define,ERRATA_A53_826319)) 1346b0d97b2SJimmy Huang 135a94cc374SDouglas Raillard# Process ERRATA_A53_835769 flag 136a94cc374SDouglas Raillard$(eval $(call assert_boolean,ERRATA_A53_835769)) 137a94cc374SDouglas Raillard$(eval $(call add_define,ERRATA_A53_835769)) 138a94cc374SDouglas Raillard 1396b0d97b2SJimmy Huang# Process ERRATA_A53_836870 flag 1406b0d97b2SJimmy Huang$(eval $(call assert_boolean,ERRATA_A53_836870)) 1416b0d97b2SJimmy Huang$(eval $(call add_define,ERRATA_A53_836870)) 1426b0d97b2SJimmy Huang 143a94cc374SDouglas Raillard# Process ERRATA_A53_843419 flag 144a94cc374SDouglas Raillard$(eval $(call assert_boolean,ERRATA_A53_843419)) 145a94cc374SDouglas Raillard$(eval $(call add_define,ERRATA_A53_843419)) 146a94cc374SDouglas Raillard 147b75dc0e4SAndre Przywara# Process ERRATA_A53_855873 flag 148b75dc0e4SAndre Przywara$(eval $(call assert_boolean,ERRATA_A53_855873)) 149b75dc0e4SAndre Przywara$(eval $(call add_define,ERRATA_A53_855873)) 150b75dc0e4SAndre Przywara 1515541bb3fSSoby Mathew# Process ERRATA_A57_806969 flag 1525541bb3fSSoby Mathew$(eval $(call assert_boolean,ERRATA_A57_806969)) 1535541bb3fSSoby Mathew$(eval $(call add_define,ERRATA_A57_806969)) 1545541bb3fSSoby Mathew 155ccbec91cSAntonio Nino Diaz# Process ERRATA_A57_813419 flag 156ccbec91cSAntonio Nino Diaz$(eval $(call assert_boolean,ERRATA_A57_813419)) 157ccbec91cSAntonio Nino Diaz$(eval $(call add_define,ERRATA_A57_813419)) 158ccbec91cSAntonio Nino Diaz 1595541bb3fSSoby Mathew# Process ERRATA_A57_813420 flag 1605541bb3fSSoby Mathew$(eval $(call assert_boolean,ERRATA_A57_813420)) 1615541bb3fSSoby Mathew$(eval $(call add_define,ERRATA_A57_813420)) 162df22d602SSandrine Bailleux 163df22d602SSandrine Bailleux# Process ERRATA_A57_826974 flag 164df22d602SSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_826974)) 165df22d602SSandrine Bailleux$(eval $(call add_define,ERRATA_A57_826974)) 166a8b1c769SSandrine Bailleux 16707288865SSandrine Bailleux# Process ERRATA_A57_826977 flag 16807288865SSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_826977)) 16907288865SSandrine Bailleux$(eval $(call add_define,ERRATA_A57_826977)) 17007288865SSandrine Bailleux 171a8b1c769SSandrine Bailleux# Process ERRATA_A57_828024 flag 172a8b1c769SSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_828024)) 173a8b1c769SSandrine Bailleux$(eval $(call add_define,ERRATA_A57_828024)) 1740b77197bSSandrine Bailleux 1750b77197bSSandrine Bailleux# Process ERRATA_A57_829520 flag 1760b77197bSSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_829520)) 1770b77197bSSandrine Bailleux$(eval $(call add_define,ERRATA_A57_829520)) 178adeecf92SSandrine Bailleux 179adeecf92SSandrine Bailleux# Process ERRATA_A57_833471 flag 180adeecf92SSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_833471)) 181adeecf92SSandrine Bailleux$(eval $(call add_define,ERRATA_A57_833471)) 182a94cc374SDouglas Raillard 18345b52c20SEleanor Bonnici# Process ERRATA_A57_859972 flag 18445b52c20SEleanor Bonnici$(eval $(call assert_boolean,ERRATA_A57_859972)) 18545b52c20SEleanor Bonnici$(eval $(call add_define,ERRATA_A57_859972)) 18645b52c20SEleanor Bonnici 1876de9b336SEleanor Bonnici# Process ERRATA_A72_859971 flag 1886de9b336SEleanor Bonnici$(eval $(call assert_boolean,ERRATA_A72_859971)) 1896de9b336SEleanor Bonnici$(eval $(call add_define,ERRATA_A72_859971)) 1906de9b336SEleanor Bonnici 191*da6d75a0SJohn Tsichritzis# Process ERRATA_N1_1043202 flag 192*da6d75a0SJohn Tsichritzis$(eval $(call assert_boolean,ERRATA_N1_1043202)) 193*da6d75a0SJohn Tsichritzis$(eval $(call add_define,ERRATA_N1_1043202)) 194040b546eSDimitris Papastamos 1958a677180SJohn Tsichritzis# Process ERRATA_DSU_936184 flag 1968a677180SJohn Tsichritzis$(eval $(call assert_boolean,ERRATA_DSU_936184)) 1978a677180SJohn Tsichritzis$(eval $(call add_define,ERRATA_DSU_936184)) 1988a677180SJohn Tsichritzis 199a94cc374SDouglas Raillard# Errata build flags 200a94cc374SDouglas Raillardifneq (${ERRATA_A53_843419},0) 201c2b8806fSDouglas RaillardTF_LDFLAGS_aarch64 += --fix-cortex-a53-843419 202a94cc374SDouglas Raillardendif 203a94cc374SDouglas Raillard 204a94cc374SDouglas Raillardifneq (${ERRATA_A53_835769},0) 205a94cc374SDouglas RaillardTF_CFLAGS_aarch64 += -mfix-cortex-a53-835769 206c2b8806fSDouglas RaillardTF_LDFLAGS_aarch64 += --fix-cortex-a53-835769 207a94cc374SDouglas Raillardendif 208