xref: /rk3399_ARM-atf/lib/cpus/cpu-ops.mk (revision 6e78973ea28def5a8cc59a434f3cdef5f3858d23)
15541bb3fSSoby Mathew#
2da6d75a0SJohn Tsichritzis# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
35541bb3fSSoby Mathew#
482cb2c1aSdp-arm# SPDX-License-Identifier: BSD-3-Clause
55541bb3fSSoby Mathew#
65541bb3fSSoby Mathew
75541bb3fSSoby Mathew# Cortex A57 specific optimisation to skip L1 cache flush when
85541bb3fSSoby Mathew# cluster is powered down.
95541bb3fSSoby MathewSKIP_A57_L1_FLUSH_PWR_DWN	?=0
105541bb3fSSoby Mathew
1154035fc4SSandrine Bailleux# Flag to disable the cache non-temporal hint.
1254035fc4SSandrine Bailleux# It is enabled by default.
1354035fc4SSandrine BailleuxA53_DISABLE_NON_TEMPORAL_HINT	?=1
1454035fc4SSandrine Bailleux
1554035fc4SSandrine Bailleux# Flag to disable the cache non-temporal hint.
1654035fc4SSandrine Bailleux# It is enabled by default.
1754035fc4SSandrine BailleuxA57_DISABLE_NON_TEMPORAL_HINT	?=1
1854035fc4SSandrine Bailleux
19f62ad322SDimitris PapastamosWORKAROUND_CVE_2017_5715	?=1
20b8a25bbbSDimitris PapastamosWORKAROUND_CVE_2018_3639	?=1
21fe007b2eSDimitris PapastamosDYNAMIC_WORKAROUND_CVE_2018_3639	?=0
22f62ad322SDimitris Papastamos
235541bb3fSSoby Mathew# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
245541bb3fSSoby Mathew$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
255541bb3fSSoby Mathew$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
265541bb3fSSoby Mathew
2754035fc4SSandrine Bailleux# Process A53_DISABLE_NON_TEMPORAL_HINT flag
2854035fc4SSandrine Bailleux$(eval $(call assert_boolean,A53_DISABLE_NON_TEMPORAL_HINT))
2954035fc4SSandrine Bailleux$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT))
3054035fc4SSandrine Bailleux
3154035fc4SSandrine Bailleux# Process A57_DISABLE_NON_TEMPORAL_HINT flag
3254035fc4SSandrine Bailleux$(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT))
3354035fc4SSandrine Bailleux$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT))
3454035fc4SSandrine Bailleux
35f62ad322SDimitris Papastamos# Process WORKAROUND_CVE_2017_5715 flag
36f62ad322SDimitris Papastamos$(eval $(call assert_boolean,WORKAROUND_CVE_2017_5715))
37f62ad322SDimitris Papastamos$(eval $(call add_define,WORKAROUND_CVE_2017_5715))
385541bb3fSSoby Mathew
39b8a25bbbSDimitris Papastamos# Process WORKAROUND_CVE_2018_3639 flag
40b8a25bbbSDimitris Papastamos$(eval $(call assert_boolean,WORKAROUND_CVE_2018_3639))
41b8a25bbbSDimitris Papastamos$(eval $(call add_define,WORKAROUND_CVE_2018_3639))
42b8a25bbbSDimitris Papastamos
43fe007b2eSDimitris Papastamos$(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639))
44fe007b2eSDimitris Papastamos$(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639))
45fe007b2eSDimitris Papastamos
46fe007b2eSDimitris Papastamosifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
47fe007b2eSDimitris Papastamos    ifeq (${WORKAROUND_CVE_2018_3639},0)
48fe007b2eSDimitris Papastamos        $(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")
49fe007b2eSDimitris Papastamos    endif
50fe007b2eSDimitris Papastamosendif
51fe007b2eSDimitris Papastamos
52097b787aSSandrine Bailleux# CPU Errata Build flags.
53097b787aSSandrine Bailleux# These should be enabled by the platform if the erratum workaround needs to be
54097b787aSSandrine Bailleux# applied.
555541bb3fSSoby Mathew
56097b787aSSandrine Bailleux# Flag to apply erratum 826319 workaround during reset. This erratum applies
57097b787aSSandrine Bailleux# only to revision <= r0p2 of the Cortex A53 cpu.
586b0d97b2SJimmy HuangERRATA_A53_826319	?=0
596b0d97b2SJimmy Huang
60a94cc374SDouglas Raillard# Flag to apply erratum 835769 workaround at compile and link time.  This
61a94cc374SDouglas Raillard# erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this
62a94cc374SDouglas Raillard# workaround can lead the linker to create "*.stub" sections.
63a94cc374SDouglas RaillardERRATA_A53_835769	?=0
64a94cc374SDouglas Raillard
65097b787aSSandrine Bailleux# Flag to apply erratum 836870 workaround during reset. This erratum applies
66097b787aSSandrine Bailleux# only to revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this
673fbe46d7SDouglas Raillard# erratum workaround is enabled by default in hardware.
686b0d97b2SJimmy HuangERRATA_A53_836870	?=0
696b0d97b2SJimmy Huang
70a94cc374SDouglas Raillard# Flag to apply erratum 843419 workaround at link time.
71a94cc374SDouglas Raillard# This erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this
72a94cc374SDouglas Raillard# workaround could lead the linker to emit "*.stub" sections which are 4kB
73a94cc374SDouglas Raillard# aligned.
74a94cc374SDouglas RaillardERRATA_A53_843419	?=0
75a94cc374SDouglas Raillard
76b75dc0e4SAndre Przywara# Flag to apply errata 855873 during reset. This errata applies to all
77b75dc0e4SAndre Przywara# revisions of the Cortex A53 CPU, but this firmware workaround only works
78b75dc0e4SAndre Przywara# for revisions r0p3 and higher. Earlier revisions are taken care
79b75dc0e4SAndre Przywara# of by the rich OS.
80b75dc0e4SAndre PrzywaraERRATA_A53_855873	?=0
81b75dc0e4SAndre Przywara
821afeee92SAmbroise Vincent# Flag to apply erratum 768277 workaround during reset. This erratum applies
831afeee92SAmbroise Vincent# only to revision r0p0 of the Cortex A55 cpu.
841afeee92SAmbroise VincentERRATA_A55_768277	?=0
851afeee92SAmbroise Vincent
86a6cc6610SAmbroise Vincent# Flag to apply erratum 778703 workaround during reset. This erratum applies
87a6cc6610SAmbroise Vincent# only to revision r0p0 of the Cortex A55 cpu.
88a6cc6610SAmbroise VincentERRATA_A55_778703	?=0
89a6cc6610SAmbroise Vincent
906ab87d29SAmbroise Vincent# Flag to apply erratum 798797 workaround during reset. This erratum applies
916ab87d29SAmbroise Vincent# only to revision r0p0 of the Cortex A55 cpu.
926ab87d29SAmbroise VincentERRATA_A55_798797	?=0
936ab87d29SAmbroise Vincent
94*6e78973eSAmbroise Vincent# Flag to apply erratum 846532 workaround during reset. This erratum applies
95*6e78973eSAmbroise Vincent# only to revision <= r0p1 of the Cortex A55 cpu.
96*6e78973eSAmbroise VincentERRATA_A55_846532	?=0
97*6e78973eSAmbroise Vincent
98097b787aSSandrine Bailleux# Flag to apply erratum 806969 workaround during reset. This erratum applies
99097b787aSSandrine Bailleux# only to revision r0p0 of the Cortex A57 cpu.
1005541bb3fSSoby MathewERRATA_A57_806969	?=0
1015541bb3fSSoby Mathew
102ccbec91cSAntonio Nino Diaz# Flag to apply erratum 813419 workaround during reset. This erratum applies
103ccbec91cSAntonio Nino Diaz# only to revision r0p0 of the Cortex A57 cpu.
104ccbec91cSAntonio Nino DiazERRATA_A57_813419	?=0
105ccbec91cSAntonio Nino Diaz
106097b787aSSandrine Bailleux# Flag to apply erratum 813420  workaround during reset. This erratum applies
107097b787aSSandrine Bailleux# only to revision r0p0 of the Cortex A57 cpu.
1085541bb3fSSoby MathewERRATA_A57_813420	?=0
1095541bb3fSSoby Mathew
110df22d602SSandrine Bailleux# Flag to apply erratum 826974 workaround during reset. This erratum applies
111df22d602SSandrine Bailleux# only to revision <= r1p1 of the Cortex A57 cpu.
112df22d602SSandrine BailleuxERRATA_A57_826974	?=0
113df22d602SSandrine Bailleux
11407288865SSandrine Bailleux# Flag to apply erratum 826977 workaround during reset. This erratum applies
11507288865SSandrine Bailleux# only to revision <= r1p1 of the Cortex A57 cpu.
11607288865SSandrine BailleuxERRATA_A57_826977	?=0
11707288865SSandrine Bailleux
118a8b1c769SSandrine Bailleux# Flag to apply erratum 828024 workaround during reset. This erratum applies
119a8b1c769SSandrine Bailleux# only to revision <= r1p1 of the Cortex A57 cpu.
120a8b1c769SSandrine BailleuxERRATA_A57_828024	?=0
121a8b1c769SSandrine Bailleux
1220b77197bSSandrine Bailleux# Flag to apply erratum 829520 workaround during reset. This erratum applies
1230b77197bSSandrine Bailleux# only to revision <= r1p2 of the Cortex A57 cpu.
1240b77197bSSandrine BailleuxERRATA_A57_829520	?=0
1250b77197bSSandrine Bailleux
126adeecf92SSandrine Bailleux# Flag to apply erratum 833471 workaround during reset. This erratum applies
127adeecf92SSandrine Bailleux# only to revision <= r1p2 of the Cortex A57 cpu.
128adeecf92SSandrine BailleuxERRATA_A57_833471	?=0
129adeecf92SSandrine Bailleux
13045b52c20SEleanor Bonnici# Flag to apply erratum 855972 workaround during reset. This erratum applies
13145b52c20SEleanor Bonnici# only to revision <= r1p3 of the Cortex A57 cpu.
13245b52c20SEleanor BonniciERRATA_A57_859972	?=0
13345b52c20SEleanor Bonnici
1346de9b336SEleanor Bonnici# Flag to apply erratum 855971 workaround during reset. This erratum applies
1356de9b336SEleanor Bonnici# only to revision <= r0p3 of the Cortex A72 cpu.
1366de9b336SEleanor BonniciERRATA_A72_859971	?=0
1376de9b336SEleanor Bonnici
138040b546eSDimitris Papastamos# Flag to apply T32 CLREX workaround during reset. This erratum applies
139da6d75a0SJohn Tsichritzis# only to r0p0 and r1p0 of the Neoverse N1 cpu.
140da6d75a0SJohn TsichritzisERRATA_N1_1043202	?=1
141040b546eSDimitris Papastamos
1428a677180SJohn Tsichritzis# Flag to apply DSU erratum 936184. This erratum applies to DSUs containing
1438a677180SJohn Tsichritzis# the ACP interface and revision < r2p0. Applying the workaround results in
1448a677180SJohn Tsichritzis# higher DSU power consumption on idle.
1458a677180SJohn TsichritzisERRATA_DSU_936184	?=0
1468a677180SJohn Tsichritzis
1476b0d97b2SJimmy Huang# Process ERRATA_A53_826319 flag
1486b0d97b2SJimmy Huang$(eval $(call assert_boolean,ERRATA_A53_826319))
1496b0d97b2SJimmy Huang$(eval $(call add_define,ERRATA_A53_826319))
1506b0d97b2SJimmy Huang
151a94cc374SDouglas Raillard# Process ERRATA_A53_835769 flag
152a94cc374SDouglas Raillard$(eval $(call assert_boolean,ERRATA_A53_835769))
153a94cc374SDouglas Raillard$(eval $(call add_define,ERRATA_A53_835769))
154a94cc374SDouglas Raillard
1556b0d97b2SJimmy Huang# Process ERRATA_A53_836870 flag
1566b0d97b2SJimmy Huang$(eval $(call assert_boolean,ERRATA_A53_836870))
1576b0d97b2SJimmy Huang$(eval $(call add_define,ERRATA_A53_836870))
1586b0d97b2SJimmy Huang
159a94cc374SDouglas Raillard# Process ERRATA_A53_843419 flag
160a94cc374SDouglas Raillard$(eval $(call assert_boolean,ERRATA_A53_843419))
161a94cc374SDouglas Raillard$(eval $(call add_define,ERRATA_A53_843419))
162a94cc374SDouglas Raillard
163b75dc0e4SAndre Przywara# Process ERRATA_A53_855873 flag
164b75dc0e4SAndre Przywara$(eval $(call assert_boolean,ERRATA_A53_855873))
165b75dc0e4SAndre Przywara$(eval $(call add_define,ERRATA_A53_855873))
166b75dc0e4SAndre Przywara
1671afeee92SAmbroise Vincent# Process ERRATA_A55_768277 flag
1681afeee92SAmbroise Vincent$(eval $(call assert_boolean,ERRATA_A55_768277))
1691afeee92SAmbroise Vincent$(eval $(call add_define,ERRATA_A55_768277))
1701afeee92SAmbroise Vincent
171a6cc6610SAmbroise Vincent# Process ERRATA_A55_778703 flag
172a6cc6610SAmbroise Vincent$(eval $(call assert_boolean,ERRATA_A55_778703))
173a6cc6610SAmbroise Vincent$(eval $(call add_define,ERRATA_A55_778703))
174a6cc6610SAmbroise Vincent
1756ab87d29SAmbroise Vincent# Process ERRATA_A55_798797 flag
1766ab87d29SAmbroise Vincent$(eval $(call assert_boolean,ERRATA_A55_798797))
1776ab87d29SAmbroise Vincent$(eval $(call add_define,ERRATA_A55_798797))
1786ab87d29SAmbroise Vincent
179*6e78973eSAmbroise Vincent# Process ERRATA_A55_846532 flag
180*6e78973eSAmbroise Vincent$(eval $(call assert_boolean,ERRATA_A55_846532))
181*6e78973eSAmbroise Vincent$(eval $(call add_define,ERRATA_A55_846532))
182*6e78973eSAmbroise Vincent
1835541bb3fSSoby Mathew# Process ERRATA_A57_806969 flag
1845541bb3fSSoby Mathew$(eval $(call assert_boolean,ERRATA_A57_806969))
1855541bb3fSSoby Mathew$(eval $(call add_define,ERRATA_A57_806969))
1865541bb3fSSoby Mathew
187ccbec91cSAntonio Nino Diaz# Process ERRATA_A57_813419 flag
188ccbec91cSAntonio Nino Diaz$(eval $(call assert_boolean,ERRATA_A57_813419))
189ccbec91cSAntonio Nino Diaz$(eval $(call add_define,ERRATA_A57_813419))
190ccbec91cSAntonio Nino Diaz
1915541bb3fSSoby Mathew# Process ERRATA_A57_813420 flag
1925541bb3fSSoby Mathew$(eval $(call assert_boolean,ERRATA_A57_813420))
1935541bb3fSSoby Mathew$(eval $(call add_define,ERRATA_A57_813420))
194df22d602SSandrine Bailleux
195df22d602SSandrine Bailleux# Process ERRATA_A57_826974 flag
196df22d602SSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_826974))
197df22d602SSandrine Bailleux$(eval $(call add_define,ERRATA_A57_826974))
198a8b1c769SSandrine Bailleux
19907288865SSandrine Bailleux# Process ERRATA_A57_826977 flag
20007288865SSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_826977))
20107288865SSandrine Bailleux$(eval $(call add_define,ERRATA_A57_826977))
20207288865SSandrine Bailleux
203a8b1c769SSandrine Bailleux# Process ERRATA_A57_828024 flag
204a8b1c769SSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_828024))
205a8b1c769SSandrine Bailleux$(eval $(call add_define,ERRATA_A57_828024))
2060b77197bSSandrine Bailleux
2070b77197bSSandrine Bailleux# Process ERRATA_A57_829520 flag
2080b77197bSSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_829520))
2090b77197bSSandrine Bailleux$(eval $(call add_define,ERRATA_A57_829520))
210adeecf92SSandrine Bailleux
211adeecf92SSandrine Bailleux# Process ERRATA_A57_833471 flag
212adeecf92SSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_833471))
213adeecf92SSandrine Bailleux$(eval $(call add_define,ERRATA_A57_833471))
214a94cc374SDouglas Raillard
21545b52c20SEleanor Bonnici# Process ERRATA_A57_859972 flag
21645b52c20SEleanor Bonnici$(eval $(call assert_boolean,ERRATA_A57_859972))
21745b52c20SEleanor Bonnici$(eval $(call add_define,ERRATA_A57_859972))
21845b52c20SEleanor Bonnici
2196de9b336SEleanor Bonnici# Process ERRATA_A72_859971 flag
2206de9b336SEleanor Bonnici$(eval $(call assert_boolean,ERRATA_A72_859971))
2216de9b336SEleanor Bonnici$(eval $(call add_define,ERRATA_A72_859971))
2226de9b336SEleanor Bonnici
223da6d75a0SJohn Tsichritzis# Process ERRATA_N1_1043202 flag
224da6d75a0SJohn Tsichritzis$(eval $(call assert_boolean,ERRATA_N1_1043202))
225da6d75a0SJohn Tsichritzis$(eval $(call add_define,ERRATA_N1_1043202))
226040b546eSDimitris Papastamos
2278a677180SJohn Tsichritzis# Process ERRATA_DSU_936184 flag
2288a677180SJohn Tsichritzis$(eval $(call assert_boolean,ERRATA_DSU_936184))
2298a677180SJohn Tsichritzis$(eval $(call add_define,ERRATA_DSU_936184))
2308a677180SJohn Tsichritzis
231a94cc374SDouglas Raillard# Errata build flags
232a94cc374SDouglas Raillardifneq (${ERRATA_A53_843419},0)
233c2b8806fSDouglas RaillardTF_LDFLAGS_aarch64	+= --fix-cortex-a53-843419
234a94cc374SDouglas Raillardendif
235a94cc374SDouglas Raillard
236a94cc374SDouglas Raillardifneq (${ERRATA_A53_835769},0)
237a94cc374SDouglas RaillardTF_CFLAGS_aarch64	+= -mfix-cortex-a53-835769
238c2b8806fSDouglas RaillardTF_LDFLAGS_aarch64	+= --fix-cortex-a53-835769
239a94cc374SDouglas Raillardendif
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