1/* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue neoverse_v1 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 32workaround_reset_start neoverse_v1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 33 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, BIT(46) 34workaround_reset_end neoverse_v1, CVE(2024, 5660) 35 36check_erratum_ls neoverse_v1, CVE(2024, 5660), CPU_REV(1, 2) 37 38workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635 39 /* Inserts a DMB SY before and after MRS PAR_EL1 */ 40 ldr x0, =0x0 41 msr NEOVERSE_V1_CPUPSELR_EL3, x0 42 ldr x0, = 0xEE070F14 43 msr NEOVERSE_V1_CPUPOR_EL3, x0 44 ldr x0, = 0xFFFF0FFF 45 msr NEOVERSE_V1_CPUPMR_EL3, x0 46 ldr x0, =0x4005027FF 47 msr NEOVERSE_V1_CPUPCR_EL3, x0 48 49 /* Inserts a DMB SY before STREX imm offset */ 50 ldr x0, =0x1 51 msr NEOVERSE_V1_CPUPSELR_EL3, x0 52 ldr x0, =0x00e8400000 53 msr NEOVERSE_V1_CPUPOR_EL3, x0 54 ldr x0, =0x00fff00000 55 msr NEOVERSE_V1_CPUPMR_EL3, x0 56 ldr x0, = 0x4001027FF 57 msr NEOVERSE_V1_CPUPCR_EL3, x0 58 59 /* Inserts a DMB SY before STREX[BHD}/STLEX* */ 60 ldr x0, =0x2 61 msr NEOVERSE_V1_CPUPSELR_EL3, x0 62 ldr x0, =0x00e8c00040 63 msr NEOVERSE_V1_CPUPOR_EL3, x0 64 ldr x0, =0x00fff00040 65 msr NEOVERSE_V1_CPUPMR_EL3, x0 66 ldr x0, = 0x4001027FF 67 msr NEOVERSE_V1_CPUPCR_EL3, x0 68 69 /* Inserts a DMB SY after STREX imm offset */ 70 ldr x0, =0x3 71 msr NEOVERSE_V1_CPUPSELR_EL3, x0 72 ldr x0, =0x00e8400000 73 msr NEOVERSE_V1_CPUPOR_EL3, x0 74 ldr x0, =0x00fff00000 75 msr NEOVERSE_V1_CPUPMR_EL3, x0 76 ldr x0, = 0x4004027FF 77 msr NEOVERSE_V1_CPUPCR_EL3, x0 78 79 /* Inserts a DMB SY after STREX[BHD}/STLEX* */ 80 ldr x0, =0x4 81 msr NEOVERSE_V1_CPUPSELR_EL3, x0 82 ldr x0, =0x00e8c00040 83 msr NEOVERSE_V1_CPUPOR_EL3, x0 84 ldr x0, =0x00fff00040 85 msr NEOVERSE_V1_CPUPMR_EL3, x0 86 ldr x0, = 0x4004027FF 87 msr NEOVERSE_V1_CPUPCR_EL3, x0 88 89workaround_reset_end neoverse_v1, ERRATUM(1618635) 90 91check_erratum_ls neoverse_v1, ERRATUM(1618635), CPU_REV(0, 0) 92 93workaround_reset_start neoverse_v1, ERRATUM(1774420), ERRATA_V1_1774420 94 /* Set bit 53 in CPUECTLR_EL1 */ 95 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53 96workaround_reset_end neoverse_v1, ERRATUM(1774420) 97 98check_erratum_ls neoverse_v1, ERRATUM(1774420), CPU_REV(1, 0) 99 100workaround_reset_start neoverse_v1, ERRATUM(1791573), ERRATA_V1_1791573 101 /* Set bit 2 in ACTLR2_EL1 */ 102 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2 103workaround_reset_end neoverse_v1, ERRATUM(1791573) 104 105check_erratum_ls neoverse_v1, ERRATUM(1791573), CPU_REV(1, 0) 106 107workaround_reset_start neoverse_v1, ERRATUM(1852267), ERRATA_V1_1852267 108 /* Set bit 28 in ACTLR2_EL1 */ 109 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28 110workaround_reset_end neoverse_v1, ERRATUM(1852267) 111 112check_erratum_ls neoverse_v1, ERRATUM(1852267), CPU_REV(1, 0) 113 114workaround_reset_start neoverse_v1, ERRATUM(1925756), ERRATA_V1_1925756 115 /* Set bit 8 in CPUECTLR_EL1 */ 116 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_8 117workaround_reset_end neoverse_v1, ERRATUM(1925756) 118 119check_erratum_ls neoverse_v1, ERRATUM(1925756), CPU_REV(1, 1) 120 121workaround_reset_start neoverse_v1, ERRATUM(1940577), ERRATA_V1_1940577 122 mov x0, #0 123 msr S3_6_C15_C8_0, x0 124 ldr x0, =0x10E3900002 125 msr S3_6_C15_C8_2, x0 126 ldr x0, =0x10FFF00083 127 msr S3_6_C15_C8_3, x0 128 ldr x0, =0x2001003FF 129 msr S3_6_C15_C8_1, x0 130 131 mov x0, #1 132 msr S3_6_C15_C8_0, x0 133 ldr x0, =0x10E3800082 134 msr S3_6_C15_C8_2, x0 135 ldr x0, =0x10FFF00083 136 msr S3_6_C15_C8_3, x0 137 ldr x0, =0x2001003FF 138 msr S3_6_C15_C8_1, x0 139 140 mov x0, #2 141 msr S3_6_C15_C8_0, x0 142 ldr x0, =0x10E3800200 143 msr S3_6_C15_C8_2, x0 144 ldr x0, =0x10FFF003E0 145 msr S3_6_C15_C8_3, x0 146 ldr x0, =0x2001003FF 147 msr S3_6_C15_C8_1, x0 148 149workaround_reset_end neoverse_v1, ERRATUM(1940577) 150 151check_erratum_range neoverse_v1, ERRATUM(1940577), CPU_REV(1, 0), CPU_REV(1, 1) 152 153workaround_reset_start neoverse_v1, ERRATUM(1966096), ERRATA_V1_1966096 154 mov x0, #0x3 155 msr S3_6_C15_C8_0, x0 156 ldr x0, =0xEE010F12 157 msr S3_6_C15_C8_2, x0 158 ldr x0, =0xFFFF0FFF 159 msr S3_6_C15_C8_3, x0 160 ldr x0, =0x80000000003FF 161 msr S3_6_C15_C8_1, x0 162workaround_reset_end neoverse_v1, ERRATUM(1966096) 163 164check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1) 165 166workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267 167 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 168 mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV 169 bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH 170 msr NEOVERSE_V1_CPUECTLR_EL1, x1 171workaround_reset_end neoverse_v1, ERRATUM(2108267) 172 173check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 2) 174 175workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242 176 mov x0, #0x3 177 msr S3_6_C15_C8_0, x0 178 ldr x0, =0xEE720F14 179 msr S3_6_C15_C8_2, x0 180 ldr x0, =0xFFFF0FDF 181 msr S3_6_C15_C8_3, x0 182 ldr x0, =0x40000005003FF 183 msr S3_6_C15_C8_1, x0 184workaround_reset_end neoverse_v1, ERRATUM(2139242) 185 186check_erratum_ls neoverse_v1, ERRATUM(2139242), CPU_REV(1, 1) 187 188workaround_reset_start neoverse_v1, ERRATUM(2216392), ERRATA_V1_2216392 189 ldr x0, =0x5 190 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 191 ldr x0, =0x10F600E000 192 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 193 ldr x0, =0x10FF80E000 194 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 195 ldr x0, =0x80000000003FF 196 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 197workaround_reset_end neoverse_v1, ERRATUM(2216392) 198 199check_erratum_range neoverse_v1, ERRATUM(2216392), CPU_REV(1, 0), CPU_REV(1, 1) 200 201workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912 202 /* Set bit 0 in ACTLR2_EL1 */ 203 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0 204workaround_reset_end neoverse_v1, ERRATUM(2294912) 205 206check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 2) 207 208workaround_reset_start neoverse_v1, ERRATUM(2348377), ERRATA_V1_2348377 209 /* Set bit 61 in CPUACTLR5_EL1 */ 210 sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_61 211workaround_reset_end neoverse_v1, ERRATUM(2348377) 212 213check_erratum_ls neoverse_v1, ERRATUM(2348377), CPU_REV(1, 1) 214 215workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203 216 /* Set bit 40 in ACTLR2_EL1 */ 217 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40 218workaround_reset_end neoverse_v1, ERRATUM(2372203) 219 220check_erratum_ls neoverse_v1, ERRATUM(2372203), CPU_REV(1, 1) 221 222workaround_runtime_start neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093 223 /* dsb before isb of power down sequence */ 224 dsb sy 225workaround_runtime_end neoverse_v1, ERRATUM(2743093) 226 227check_erratum_ls neoverse_v1, ERRATUM(2743093), CPU_REV(1, 2) 228 229workaround_reset_start neoverse_v1, ERRATUM(2743233), ERRATA_V1_2743233 230 sysreg_bit_clear NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_56 231 sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_55 232workaround_reset_end neoverse_v1, ERRATUM(2743233) 233 234check_erratum_ls neoverse_v1, ERRATUM(2743233), CPU_REV(1, 2) 235 236workaround_reset_start neoverse_v1, ERRATUM(2779461), ERRATA_V1_2779461 237 sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, NEOVERSE_V1_ACTLR3_EL1_BIT_47 238workaround_reset_end neoverse_v1, ERRATUM(2779461) 239 240check_erratum_ls neoverse_v1, ERRATUM(2779461), CPU_REV(1, 2) 241 242 243workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960 244#if IMAGE_BL31 245 /* 246 * The Neoverse-V1 generic vectors are overridden to apply errata 247 * mitigation on exception entry from lower ELs. 248 */ 249 override_vector_table wa_cve_vbar_neoverse_v1 250#endif /* IMAGE_BL31 */ 251workaround_reset_end neoverse_v1, CVE(2022,23960) 252 253check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 254 255 /* --------------------------------------------- 256 * HW will do the cache maintenance while powering down 257 * --------------------------------------------- 258 */ 259func neoverse_v1_core_pwr_dwn 260 /* --------------------------------------------- 261 * Enable CPU power down bit in power control register 262 * --------------------------------------------- 263 */ 264 sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 265 apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093, NO_GET_CPU_REV 266 267 isb 268 ret 269endfunc neoverse_v1_core_pwr_dwn 270 271cpu_reset_func_start neoverse_v1 272 /* Disable speculative loads */ 273 msr SSBS, xzr 274cpu_reset_func_end neoverse_v1 275 276 /* --------------------------------------------- 277 * This function provides Neoverse-V1 specific 278 * register information for crash reporting. 279 * It needs to return with x6 pointing to 280 * a list of register names in ascii and 281 * x8 - x15 having values of registers to be 282 * reported. 283 * --------------------------------------------- 284 */ 285.section .rodata.neoverse_v1_regs, "aS" 286neoverse_v1_regs: /* The ascii list of register names to be reported */ 287 .asciz "cpuectlr_el1", "" 288 289func neoverse_v1_cpu_reg_dump 290 adr x6, neoverse_v1_regs 291 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 292 ret 293endfunc neoverse_v1_cpu_reg_dump 294 295declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 296 neoverse_v1_reset_func, \ 297 neoverse_v1_core_pwr_dwn 298