1/* 2 * Copyright (c) 2019-2020, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* -------------------------------------------------- 25 * Errata Workaround for Neoverse V1 Errata #1791573. 26 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_neoverse_v1_1791573_wa 32 /* Check workaround compatibility. */ 33 mov x17, x30 34 bl check_errata_1791573 35 cbz x0, 1f 36 37 /* Set bit 2 in ACTLR2_EL1 */ 38 mrs x1, NEOVERSE_V1_ACTLR2_EL1 39 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 40 msr NEOVERSE_V1_ACTLR2_EL1, x1 41 isb 421: 43 ret x17 44endfunc errata_neoverse_v1_1791573_wa 45 46func check_errata_1791573 47 /* Applies to r0p0 and r1p0. */ 48 mov x1, #0x10 49 b cpu_rev_var_ls 50endfunc check_errata_1791573 51 52 /* -------------------------------------------------- 53 * Errata Workaround for Neoverse V1 Erratum #1940577 54 * This applies to revisions r1p0 - r1p1 and is open. 55 * It also exists in r0p0 but there is no fix in that 56 * revision. 57 * Inputs: 58 * x0: variant[4:7] and revision[0:3] of current cpu. 59 * Shall clobber: x0-x17 60 * -------------------------------------------------- 61 */ 62func errata_neoverse_v1_1940577_wa 63 /* Compare x0 against revisions r1p0 - r1p1 */ 64 mov x17, x30 65 bl check_errata_1940577 66 cbz x0, 1f 67 68 mov x0, #0 69 msr S3_6_C15_C8_0, x0 70 ldr x0, =0x10E3900002 71 msr S3_6_C15_C8_2, x0 72 ldr x0, =0x10FFF00083 73 msr S3_6_C15_C8_3, x0 74 ldr x0, =0x2001003FF 75 msr S3_6_C15_C8_1, x0 76 77 mov x0, #1 78 msr S3_6_C15_C8_0, x0 79 ldr x0, =0x10E3800082 80 msr S3_6_C15_C8_2, x0 81 ldr x0, =0x10FFF00083 82 msr S3_6_C15_C8_3, x0 83 ldr x0, =0x2001003FF 84 msr S3_6_C15_C8_1, x0 85 86 mov x0, #2 87 msr S3_6_C15_C8_0, x0 88 ldr x0, =0x10E3800200 89 msr S3_6_C15_C8_2, x0 90 ldr x0, =0x10FFF003E0 91 msr S3_6_C15_C8_3, x0 92 ldr x0, =0x2001003FF 93 msr S3_6_C15_C8_1, x0 94 95 isb 961: 97 ret x17 98endfunc errata_neoverse_v1_1940577_wa 99 100func check_errata_1940577 101 /* Applies to revisions r1p0 - r1p1. */ 102 mov x1, #0x10 103 mov x2, #0x11 104 b cpu_rev_var_range 105endfunc check_errata_1940577 106 107 /* --------------------------------------------- 108 * HW will do the cache maintenance while powering down 109 * --------------------------------------------- 110 */ 111func neoverse_v1_core_pwr_dwn 112 /* --------------------------------------------- 113 * Enable CPU power down bit in power control register 114 * --------------------------------------------- 115 */ 116 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 117 orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 118 msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 119 isb 120 ret 121endfunc neoverse_v1_core_pwr_dwn 122 123 /* 124 * Errata printing function for Neoverse V1. Must follow AAPCS. 125 */ 126#if REPORT_ERRATA 127func neoverse_v1_errata_report 128 stp x8, x30, [sp, #-16]! 129 130 bl cpu_get_rev_var 131 mov x8, x0 132 133 /* 134 * Report all errata. The revision-variant information is passed to 135 * checking functions of each errata. 136 */ 137 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 138 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 139 140 ldp x8, x30, [sp], #16 141 ret 142endfunc neoverse_v1_errata_report 143#endif 144 145func neoverse_v1_reset_func 146 mov x19, x30 147 148 /* Disable speculative loads */ 149 msr SSBS, xzr 150 isb 151 152#if ERRATA_V1_1791573 153 mov x0, x18 154 bl errata_neoverse_v1_1791573_wa 155#endif 156 157#if ERRATA_V1_1940577 158 mov x0, x18 159 bl errata_neoverse_v1_1940577_wa 160#endif 161 162 ret x19 163endfunc neoverse_v1_reset_func 164 165 /* --------------------------------------------- 166 * This function provides Neoverse-V1 specific 167 * register information for crash reporting. 168 * It needs to return with x6 pointing to 169 * a list of register names in ascii and 170 * x8 - x15 having values of registers to be 171 * reported. 172 * --------------------------------------------- 173 */ 174.section .rodata.neoverse_v1_regs, "aS" 175neoverse_v1_regs: /* The ascii list of register names to be reported */ 176 .asciz "cpuectlr_el1", "" 177 178func neoverse_v1_cpu_reg_dump 179 adr x6, neoverse_v1_regs 180 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 181 ret 182endfunc neoverse_v1_cpu_reg_dump 183 184declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 185 neoverse_v1_reset_func, \ 186 neoverse_v1_core_pwr_dwn 187