1/* 2 * Copyright (c) 2019-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29 /* -------------------------------------------------- 30 * Errata Workaround for Neoverse V1 Errata #1618635. 31 * This applies to revision r0p0 and is fixed in 32 * r1p0. 33 * x0: variant[4:7] and revision[0:3] of current cpu. 34 * Shall clobber: x0, x17 35 * -------------------------------------------------- 36 */ 37func errata_neoverse_v1_1618635_wa 38 /* Check workaround compatibility. */ 39 mov x17, x30 40 bl check_errata_1618635 41 cbz x0, 1f 42 43 /* Inserts a DMB SY before and after MRS PAR_EL1 */ 44 ldr x0, =0x0 45 msr NEOVERSE_V1_CPUPSELR_EL3, x0 46 ldr x0, = 0xEE070F14 47 msr NEOVERSE_V1_CPUPOR_EL3, x0 48 ldr x0, = 0xFFFF0FFF 49 msr NEOVERSE_V1_CPUPMR_EL3, x0 50 ldr x0, =0x4005027FF 51 msr NEOVERSE_V1_CPUPCR_EL3, x0 52 53 /* Inserts a DMB SY before STREX imm offset */ 54 ldr x0, =0x1 55 msr NEOVERSE_V1_CPUPSELR_EL3, x0 56 ldr x0, =0x00e8400000 57 msr NEOVERSE_V1_CPUPOR_EL3, x0 58 ldr x0, =0x00fff00000 59 msr NEOVERSE_V1_CPUPMR_EL3, x0 60 ldr x0, = 0x4001027FF 61 msr NEOVERSE_V1_CPUPCR_EL3, x0 62 63 /* Inserts a DMB SY before STREX[BHD}/STLEX* */ 64 ldr x0, =0x2 65 msr NEOVERSE_V1_CPUPSELR_EL3, x0 66 ldr x0, =0x00e8c00040 67 msr NEOVERSE_V1_CPUPOR_EL3, x0 68 ldr x0, =0x00fff00040 69 msr NEOVERSE_V1_CPUPMR_EL3, x0 70 ldr x0, = 0x4001027FF 71 msr NEOVERSE_V1_CPUPCR_EL3, x0 72 73 /* Inserts a DMB SY after STREX imm offset */ 74 ldr x0, =0x3 75 msr NEOVERSE_V1_CPUPSELR_EL3, x0 76 ldr x0, =0x00e8400000 77 msr NEOVERSE_V1_CPUPOR_EL3, x0 78 ldr x0, =0x00fff00000 79 msr NEOVERSE_V1_CPUPMR_EL3, x0 80 ldr x0, = 0x4004027FF 81 msr NEOVERSE_V1_CPUPCR_EL3, x0 82 83 /* Inserts a DMB SY after STREX[BHD}/STLEX* */ 84 ldr x0, =0x4 85 msr NEOVERSE_V1_CPUPSELR_EL3, x0 86 ldr x0, =0x00e8c00040 87 msr NEOVERSE_V1_CPUPOR_EL3, x0 88 ldr x0, =0x00fff00040 89 msr NEOVERSE_V1_CPUPMR_EL3, x0 90 ldr x0, = 0x4004027FF 91 msr NEOVERSE_V1_CPUPCR_EL3, x0 92 93 /* Synchronize to enable patches */ 94 isb 951: 96 ret x17 97endfunc errata_neoverse_v1_1618635_wa 98 99func check_errata_1618635 100 /* Applies to revision r0p0. */ 101 mov x1, #0x00 102 b cpu_rev_var_ls 103endfunc check_errata_1618635 104 105 /* -------------------------------------------------- 106 * Errata Workaround for Neoverse V1 Errata #1774420. 107 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 108 * x0: variant[4:7] and revision[0:3] of current cpu. 109 * Shall clobber: x0-x17 110 * -------------------------------------------------- 111 */ 112func errata_neoverse_v1_1774420_wa 113 /* Check workaround compatibility. */ 114 mov x17, x30 115 bl check_errata_1774420 116 cbz x0, 1f 117 118 /* Set bit 53 in CPUECTLR_EL1 */ 119 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 120 orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53 121 msr NEOVERSE_V1_CPUECTLR_EL1, x1 122 isb 1231: 124 ret x17 125endfunc errata_neoverse_v1_1774420_wa 126 127func check_errata_1774420 128 /* Applies to r0p0 and r1p0. */ 129 mov x1, #0x10 130 b cpu_rev_var_ls 131endfunc check_errata_1774420 132 133 /* -------------------------------------------------- 134 * Errata Workaround for Neoverse V1 Errata #1791573. 135 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 136 * x0: variant[4:7] and revision[0:3] of current cpu. 137 * Shall clobber: x0-x17 138 * -------------------------------------------------- 139 */ 140func errata_neoverse_v1_1791573_wa 141 /* Check workaround compatibility. */ 142 mov x17, x30 143 bl check_errata_1791573 144 cbz x0, 1f 145 146 /* Set bit 2 in ACTLR2_EL1 */ 147 mrs x1, NEOVERSE_V1_ACTLR2_EL1 148 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 149 msr NEOVERSE_V1_ACTLR2_EL1, x1 150 isb 1511: 152 ret x17 153endfunc errata_neoverse_v1_1791573_wa 154 155func check_errata_1791573 156 /* Applies to r0p0 and r1p0. */ 157 mov x1, #0x10 158 b cpu_rev_var_ls 159endfunc check_errata_1791573 160 161 /* -------------------------------------------------- 162 * Errata Workaround for Neoverse V1 Errata #1852267. 163 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 164 * x0: variant[4:7] and revision[0:3] of current cpu. 165 * Shall clobber: x0-x17 166 * -------------------------------------------------- 167 */ 168func errata_neoverse_v1_1852267_wa 169 /* Check workaround compatibility. */ 170 mov x17, x30 171 bl check_errata_1852267 172 cbz x0, 1f 173 174 /* Set bit 28 in ACTLR2_EL1 */ 175 mrs x1, NEOVERSE_V1_ACTLR2_EL1 176 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28 177 msr NEOVERSE_V1_ACTLR2_EL1, x1 178 isb 1791: 180 ret x17 181endfunc errata_neoverse_v1_1852267_wa 182 183func check_errata_1852267 184 /* Applies to r0p0 and r1p0. */ 185 mov x1, #0x10 186 b cpu_rev_var_ls 187endfunc check_errata_1852267 188 189 /* -------------------------------------------------- 190 * Errata Workaround for Neoverse V1 Errata #1925756. 191 * This applies to revisions <= r1p1. 192 * x0: variant[4:7] and revision[0:3] of current cpu. 193 * Shall clobber: x0-x17 194 * -------------------------------------------------- 195 */ 196func errata_neoverse_v1_1925756_wa 197 /* Check workaround compatibility. */ 198 mov x17, x30 199 bl check_errata_1925756 200 cbz x0, 1f 201 202 /* Set bit 8 in CPUECTLR_EL1 */ 203 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 204 orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_8 205 msr NEOVERSE_V1_CPUECTLR_EL1, x1 206 isb 2071: 208 ret x17 209endfunc errata_neoverse_v1_1925756_wa 210 211func check_errata_1925756 212 /* Applies to <= r1p1. */ 213 mov x1, #0x11 214 b cpu_rev_var_ls 215endfunc check_errata_1925756 216 217 /* -------------------------------------------------- 218 * Errata Workaround for Neoverse V1 Erratum #1940577 219 * This applies to revisions r1p0 - r1p1 and is open. 220 * It also exists in r0p0 but there is no fix in that 221 * revision. 222 * Inputs: 223 * x0: variant[4:7] and revision[0:3] of current cpu. 224 * Shall clobber: x0-x17 225 * -------------------------------------------------- 226 */ 227func errata_neoverse_v1_1940577_wa 228 /* Compare x0 against revisions r1p0 - r1p1 */ 229 mov x17, x30 230 bl check_errata_1940577 231 cbz x0, 1f 232 233 mov x0, #0 234 msr S3_6_C15_C8_0, x0 235 ldr x0, =0x10E3900002 236 msr S3_6_C15_C8_2, x0 237 ldr x0, =0x10FFF00083 238 msr S3_6_C15_C8_3, x0 239 ldr x0, =0x2001003FF 240 msr S3_6_C15_C8_1, x0 241 242 mov x0, #1 243 msr S3_6_C15_C8_0, x0 244 ldr x0, =0x10E3800082 245 msr S3_6_C15_C8_2, x0 246 ldr x0, =0x10FFF00083 247 msr S3_6_C15_C8_3, x0 248 ldr x0, =0x2001003FF 249 msr S3_6_C15_C8_1, x0 250 251 mov x0, #2 252 msr S3_6_C15_C8_0, x0 253 ldr x0, =0x10E3800200 254 msr S3_6_C15_C8_2, x0 255 ldr x0, =0x10FFF003E0 256 msr S3_6_C15_C8_3, x0 257 ldr x0, =0x2001003FF 258 msr S3_6_C15_C8_1, x0 259 260 isb 2611: 262 ret x17 263endfunc errata_neoverse_v1_1940577_wa 264 265func check_errata_1940577 266 /* Applies to revisions r1p0 - r1p1. */ 267 mov x1, #0x10 268 mov x2, #0x11 269 b cpu_rev_var_range 270endfunc check_errata_1940577 271 272 /* -------------------------------------------------- 273 * Errata Workaround for Neoverse V1 Errata #1966096 274 * This applies to revisions r1p0 - r1p1 and is open. 275 * It also exists in r0p0 but there is no workaround 276 * for that revision. 277 * x0: variant[4:7] and revision[0:3] of current cpu. 278 * Shall clobber: x0-x17 279 * -------------------------------------------------- 280 */ 281func errata_neoverse_v1_1966096_wa 282 /* Check workaround compatibility. */ 283 mov x17, x30 284 bl check_errata_1966096 285 cbz x0, 1f 286 287 /* Apply the workaround. */ 288 mov x0, #0x3 289 msr S3_6_C15_C8_0, x0 290 ldr x0, =0xEE010F12 291 msr S3_6_C15_C8_2, x0 292 ldr x0, =0xFFFF0FFF 293 msr S3_6_C15_C8_3, x0 294 ldr x0, =0x80000000003FF 295 msr S3_6_C15_C8_1, x0 296 isb 297 2981: 299 ret x17 300endfunc errata_neoverse_v1_1966096_wa 301 302func check_errata_1966096 303 mov x1, #0x10 304 mov x2, #0x11 305 b cpu_rev_var_range 306endfunc check_errata_1966096 307 308 /* -------------------------------------------------- 309 * Errata Workaround for Neoverse V1 Errata #2139242. 310 * This applies to revisions r0p0, r1p0, and r1p1, it 311 * is still open. 312 * x0: variant[4:7] and revision[0:3] of current cpu. 313 * Shall clobber: x0-x17 314 * -------------------------------------------------- 315 */ 316func errata_neoverse_v1_2139242_wa 317 /* Check workaround compatibility. */ 318 mov x17, x30 319 bl check_errata_2139242 320 cbz x0, 1f 321 322 /* Apply the workaround. */ 323 mov x0, #0x3 324 msr S3_6_C15_C8_0, x0 325 ldr x0, =0xEE720F14 326 msr S3_6_C15_C8_2, x0 327 ldr x0, =0xFFFF0FDF 328 msr S3_6_C15_C8_3, x0 329 ldr x0, =0x40000005003FF 330 msr S3_6_C15_C8_1, x0 331 isb 332 3331: 334 ret x17 335endfunc errata_neoverse_v1_2139242_wa 336 337func check_errata_2139242 338 /* Applies to r0p0, r1p0, r1p1 */ 339 mov x1, #0x11 340 b cpu_rev_var_ls 341endfunc check_errata_2139242 342 343 /* -------------------------------------------------- 344 * Errata Workaround for Neoverse V1 Errata #2108267. 345 * This applies to revisions r0p0, r1p0, and r1p1, it 346 * is still open. 347 * x0: variant[4:7] and revision[0:3] of current cpu. 348 * Shall clobber: x0-x1, x17 349 * -------------------------------------------------- 350 */ 351func errata_neoverse_v1_2108267_wa 352 /* Check workaround compatibility. */ 353 mov x17, x30 354 bl check_errata_2108267 355 cbz x0, 1f 356 357 /* Apply the workaround. */ 358 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 359 mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV 360 bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH 361 msr NEOVERSE_V1_CPUECTLR_EL1, x1 3621: 363 ret x17 364endfunc errata_neoverse_v1_2108267_wa 365 366func check_errata_2108267 367 /* Applies to r0p0, r1p0, r1p1 */ 368 mov x1, #0x11 369 b cpu_rev_var_ls 370endfunc check_errata_2108267 371 372 /* -------------------------------------------------- 373 * Errata Workaround for Neoverse V1 Errata #2216392. 374 * This applies to revisions r1p0 and r1p1 and is 375 * still open. 376 * This issue is also present in r0p0 but there is no 377 * workaround in that revision. 378 * x0: variant[4:7] and revision[0:3] of current cpu. 379 * Shall clobber: x0-x17 380 * -------------------------------------------------- 381 */ 382func errata_neoverse_v1_2216392_wa 383 /* Check workaround compatibility. */ 384 mov x17, x30 385 bl check_errata_2216392 386 cbz x0, 1f 387 388 ldr x0, =0x5 389 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 390 ldr x0, =0x10F600E000 391 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 392 ldr x0, =0x10FF80E000 393 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 394 ldr x0, =0x80000000003FF 395 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 396 397 isb 3981: 399 ret x17 400endfunc errata_neoverse_v1_2216392_wa 401 402func check_errata_2216392 403 /* Applies to revisions r1p0 and r1p1. */ 404 mov x1, #CPU_REV(1, 0) 405 mov x2, #CPU_REV(1, 1) 406 b cpu_rev_var_range 407endfunc check_errata_2216392 408 409 /* ----------------------------------------------------------------- 410 * Errata Workaround for Neoverse V1 Errata #2294912. 411 * This applies to revisions r0p0, r1p0, and r1p1 and is still open. 412 * x0: variant[4:7] and revision[0:3] of current cpu. 413 * Shall clobber: x0-x17 414 * ----------------------------------------------------------------- 415 */ 416func errata_neoverse_v1_2294912_wa 417 /* Check workaround compatibility. */ 418 mov x17, x30 419 bl check_errata_2294912 420 cbz x0, 1f 421 422 /* Set bit 0 in ACTLR2_EL1 */ 423 mrs x1, NEOVERSE_V1_ACTLR2_EL1 424 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_0 425 msr NEOVERSE_V1_ACTLR2_EL1, x1 426 isb 4271: 428 ret x17 429endfunc errata_neoverse_v1_2294912_wa 430 431func check_errata_2294912 432 /* Applies to r0p0, r1p0, and r1p1 right now */ 433 mov x1, #0x11 434 b cpu_rev_var_ls 435endfunc check_errata_2294912 436 437 /* --------------------------------------------------- 438 * Errata Workaround for Neoverse V1 Errata #2372203. 439 * This applies to revisions <= r1p1 and is still open. 440 * x0: variant[4:7] and revision[0:3] of current cpu. 441 * Shall clobber: x0-x17 442 * ---------------------------------------------------- 443 */ 444func errata_neoverse_v1_2372203_wa 445 /* Check workaround compatibility. */ 446 mov x17, x30 447 bl check_errata_2372203 448 cbz x0, 1f 449 450 /* Set bit 40 in ACTLR2_EL1 */ 451 mrs x1, NEOVERSE_V1_ACTLR2_EL1 452 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_40 453 msr NEOVERSE_V1_ACTLR2_EL1, x1 454 isb 4551: 456 ret x17 457endfunc errata_neoverse_v1_2372203_wa 458 459func check_errata_2372203 460 /* Applies to <= r1p1. */ 461 mov x1, #0x11 462 b cpu_rev_var_ls 463endfunc check_errata_2372203 464 465 /* ---------------------------------------------------- 466 * Errata Workaround for Neoverse V1 Errata #2743093. 467 * This applies to revisions <= r1p2 and is still open. 468 * x0: variant[4:7] and revision[0:3] of current cpu. 469 * Shall clobber: x0-x17 470 * ---------------------------------------------------- 471 */ 472func errata_neoverse_v1_2743093_wa 473 mov x17, x30 474 bl check_errata_2743093 475 cbz x0, 1f 476 477 /* dsb before isb of power down sequence */ 478 dsb sy 4791: 480 ret x17 481endfunc errata_neoverse_v1_2743093_wa 482 483func check_errata_2743093 484 /* Applies to all revisions <= r1p2 */ 485 mov x1, #0x12 486 b cpu_rev_var_ls 487endfunc check_errata_2743093 488 489func check_errata_cve_2022_23960 490#if WORKAROUND_CVE_2022_23960 491 mov x0, #ERRATA_APPLIES 492#else 493 mov x0, #ERRATA_MISSING 494#endif 495 ret 496endfunc check_errata_cve_2022_23960 497 498 /* --------------------------------------------- 499 * HW will do the cache maintenance while powering down 500 * --------------------------------------------- 501 */ 502func neoverse_v1_core_pwr_dwn 503 /* --------------------------------------------- 504 * Enable CPU power down bit in power control register 505 * --------------------------------------------- 506 */ 507 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 508 orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 509 msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 510#if ERRATA_V1_2743093 511 mov x15, x30 512 bl cpu_get_rev_var 513 bl errata_neoverse_v1_2743093_wa 514 mov x30, x15 515#endif /* ERRATA_V1_2743093 */ 516 isb 517 ret 518endfunc neoverse_v1_core_pwr_dwn 519 520 /* 521 * Errata printing function for Neoverse V1. Must follow AAPCS. 522 */ 523#if REPORT_ERRATA 524func neoverse_v1_errata_report 525 stp x8, x30, [sp, #-16]! 526 527 bl cpu_get_rev_var 528 mov x8, x0 529 530 /* 531 * Report all errata. The revision-variant information is passed to 532 * checking functions of each errata. 533 */ 534 report_errata ERRATA_V1_1618635, neoverse_v1, 1618635 535 report_errata ERRATA_V1_1774420, neoverse_v1, 1774420 536 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 537 report_errata ERRATA_V1_1852267, neoverse_v1, 1852267 538 report_errata ERRATA_V1_1925756, neoverse_v1, 1925756 539 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 540 report_errata ERRATA_V1_1966096, neoverse_v1, 1966096 541 report_errata ERRATA_V1_2108267, neoverse_v1, 2108267 542 report_errata ERRATA_V1_2139242, neoverse_v1, 2139242 543 report_errata ERRATA_V1_2216392, neoverse_v1, 2216392 544 report_errata ERRATA_V1_2294912, neoverse_v1, 2294912 545 report_errata ERRATA_V1_2372203, neoverse_v1, 2372203 546 report_errata ERRATA_V1_2743093, neoverse_v1, 2743093 547 report_errata WORKAROUND_CVE_2022_23960, neoverse_v1, cve_2022_23960 548 549 ldp x8, x30, [sp], #16 550 ret 551endfunc neoverse_v1_errata_report 552#endif 553 554func neoverse_v1_reset_func 555 mov x19, x30 556 557 /* Disable speculative loads */ 558 msr SSBS, xzr 559 isb 560 561 /* Get the CPU revision and stash it in x18. */ 562 bl cpu_get_rev_var 563 mov x18, x0 564 565#if ERRATA_V1_1618635 566 mov x0, x18 567 bl errata_neoverse_v1_1618635_wa 568#endif 569 570#if ERRATA_V1_1774420 571 mov x0, x18 572 bl errata_neoverse_v1_1774420_wa 573#endif 574 575#if ERRATA_V1_1791573 576 mov x0, x18 577 bl errata_neoverse_v1_1791573_wa 578#endif 579 580#if ERRATA_V1_1852267 581 mov x0, x18 582 bl errata_neoverse_v1_1852267_wa 583#endif 584 585#if ERRATA_V1_1925756 586 mov x0, x18 587 bl errata_neoverse_v1_1925756_wa 588#endif 589 590#if ERRATA_V1_1940577 591 mov x0, x18 592 bl errata_neoverse_v1_1940577_wa 593#endif 594 595#if ERRATA_V1_1966096 596 mov x0, x18 597 bl errata_neoverse_v1_1966096_wa 598#endif 599 600#if ERRATA_V1_2139242 601 mov x0, x18 602 bl errata_neoverse_v1_2139242_wa 603#endif 604 605#if ERRATA_V1_2108267 606 mov x0, x18 607 bl errata_neoverse_v1_2108267_wa 608#endif 609 610#if ERRATA_V1_2216392 611 mov x0, x18 612 bl errata_neoverse_v1_2216392_wa 613#endif 614 615#if ERRATA_V1_2294912 616 mov x0, x18 617 bl errata_neoverse_v1_2294912_wa 618#endif 619 620#if ERRATA_V1_2372203 621 mov x0, x18 622 bl errata_neoverse_v1_2372203_wa 623#endif 624 625#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 626 /* 627 * The Neoverse-V1 generic vectors are overridden to apply errata 628 * mitigation on exception entry from lower ELs. 629 */ 630 adr x0, wa_cve_vbar_neoverse_v1 631 msr vbar_el3, x0 632#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 633 634 isb 635 ret x19 636endfunc neoverse_v1_reset_func 637 638 /* --------------------------------------------- 639 * This function provides Neoverse-V1 specific 640 * register information for crash reporting. 641 * It needs to return with x6 pointing to 642 * a list of register names in ascii and 643 * x8 - x15 having values of registers to be 644 * reported. 645 * --------------------------------------------- 646 */ 647.section .rodata.neoverse_v1_regs, "aS" 648neoverse_v1_regs: /* The ascii list of register names to be reported */ 649 .asciz "cpuectlr_el1", "" 650 651func neoverse_v1_cpu_reg_dump 652 adr x6, neoverse_v1_regs 653 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 654 ret 655endfunc neoverse_v1_cpu_reg_dump 656 657declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 658 neoverse_v1_reset_func, \ 659 neoverse_v1_core_pwr_dwn 660