1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_n3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse-N3 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue neoverse_n3 25 26.global check_erratum_neoverse_n3_3699563 27 28add_erratum_entry neoverse_n3, ERRATUM(3699563), ERRATA_N3_3699563 29 30check_erratum_ls neoverse_n3, ERRATUM(3699563), CPU_REV(0, 0) 31 32cpu_reset_func_start neoverse_n3 33 /* Disable speculative loads */ 34 msr SSBS, xzr 35 36#if !NEOVERSE_Nx_EXTERNAL_LLC 37 /* ------------------------------------------------------------- 38 * Neoverse n3 has that last level cache is external by default. 39 * Clear the bit when NEOVERSE_Nx_EXTERNAL_LLC is not enabled. 40 * ------------------------------------------------------------- 41 */ 42 sysreg_bit_clear NEOVERSE_N3_CPUECTLR2_EL1, NEOVERSE_N3_CPUECTLR2_EL1_SW_EXT_LLC_BIT 43#endif 44cpu_reset_func_end neoverse_n3 45 46 /* ---------------------------------------------------- 47 * HW will do the cache maintenance while powering down 48 * ---------------------------------------------------- 49 */ 50func neoverse_n3_core_pwr_dwn 51 /* --------------------------------------------------- 52 * Enable CPU power down bit in power control register 53 * --------------------------------------------------- 54 */ 55 sysreg_bit_set NEOVERSE_N3_CPUPWRCTLR_EL1, NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 56 isb 57 ret 58endfunc neoverse_n3_core_pwr_dwn 59 60 /* --------------------------------------------- 61 * This function provides Neoverse-N3 specific 62 * register information for crash reporting. 63 * It needs to return with x6 pointing to 64 * a list of register names in ascii and 65 * x8 - x15 having values of registers to be 66 * reported. 67 * --------------------------------------------- 68 */ 69.section .rodata.neoverse_n3_regs, "aS" 70neoverse_n3_regs: /* The ascii list of register names to be reported */ 71 .asciz "cpuectlr_el1", "" 72 73func neoverse_n3_cpu_reg_dump 74 adr x6, neoverse_n3_regs 75 mrs x8, NEOVERSE_N3_CPUECTLR_EL1 76 ret 77endfunc neoverse_n3_cpu_reg_dump 78 79declare_cpu_ops neoverse_n3, NEOVERSE_N3_MIDR, \ 80 neoverse_n3_reset_func, \ 81 neoverse_n3_core_pwr_dwn 82