1/* 2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_n3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse-N3 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_func_start neoverse_n3 25 /* Disable speculative loads */ 26 msr SSBS, xzr 27 28#if NEOVERSE_Nx_EXTERNAL_LLC 29 /* Some systems may have External LLC, core needs to be made aware */ 30 sysreg_bit_set NEOVERSE_N3_CPUECTLR_EL1, NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT 31#endif 32cpu_reset_func_end neoverse_n3 33 34 /* ---------------------------------------------------- 35 * HW will do the cache maintenance while powering down 36 * ---------------------------------------------------- 37 */ 38func neoverse_n3_core_pwr_dwn 39 /* --------------------------------------------------- 40 * Enable CPU power down bit in power control register 41 * --------------------------------------------------- 42 */ 43 sysreg_bit_set NEOVERSE_N3_CPUPWRCTLR_EL1, NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 44 isb 45 ret 46endfunc neoverse_n3_core_pwr_dwn 47 48 /* --------------------------------------------- 49 * This function provides Neoverse-N3 specific 50 * register information for crash reporting. 51 * It needs to return with x6 pointing to 52 * a list of register names in ascii and 53 * x8 - x15 having values of registers to be 54 * reported. 55 * --------------------------------------------- 56 */ 57.section .rodata.neoverse_n3_regs, "aS" 58neoverse_n3_regs: /* The ascii list of register names to be reported */ 59 .asciz "cpuectlr_el1", "" 60 61func neoverse_n3_cpu_reg_dump 62 adr x6, neoverse_n3_regs 63 mrs x8, NEOVERSE_N3_CPUECTLR_EL1 64 ret 65endfunc neoverse_n3_cpu_reg_dump 66 67declare_cpu_ops neoverse_n3, NEOVERSE_N3_MIDR, \ 68 neoverse_n3_reset_func, \ 69 neoverse_n3_core_pwr_dwn 70