1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_n3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse-N3 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue neoverse_n3 25 26.global check_erratum_neoverse_n3_3699563 27 28add_erratum_entry neoverse_n3, ERRATUM(3699563), ERRATA_N3_3699563 29 30check_erratum_ls neoverse_n3, ERRATUM(3699563), CPU_REV(0, 0) 31 32cpu_reset_func_start neoverse_n3 33 /* Disable speculative loads */ 34 msr SSBS, xzr 35 36#if NEOVERSE_Nx_EXTERNAL_LLC 37 /* Some systems may have External LLC, core needs to be made aware */ 38 sysreg_bit_set NEOVERSE_N3_CPUECTLR_EL1, NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT 39#endif 40cpu_reset_func_end neoverse_n3 41 42 /* ---------------------------------------------------- 43 * HW will do the cache maintenance while powering down 44 * ---------------------------------------------------- 45 */ 46func neoverse_n3_core_pwr_dwn 47 /* --------------------------------------------------- 48 * Enable CPU power down bit in power control register 49 * --------------------------------------------------- 50 */ 51 sysreg_bit_set NEOVERSE_N3_CPUPWRCTLR_EL1, NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 52 isb 53 ret 54endfunc neoverse_n3_core_pwr_dwn 55 56 /* --------------------------------------------- 57 * This function provides Neoverse-N3 specific 58 * register information for crash reporting. 59 * It needs to return with x6 pointing to 60 * a list of register names in ascii and 61 * x8 - x15 having values of registers to be 62 * reported. 63 * --------------------------------------------- 64 */ 65.section .rodata.neoverse_n3_regs, "aS" 66neoverse_n3_regs: /* The ascii list of register names to be reported */ 67 .asciz "cpuectlr_el1", "" 68 69func neoverse_n3_cpu_reg_dump 70 adr x6, neoverse_n3_regs 71 mrs x8, NEOVERSE_N3_CPUECTLR_EL1 72 ret 73endfunc neoverse_n3_cpu_reg_dump 74 75declare_cpu_ops neoverse_n3, NEOVERSE_N3_MIDR, \ 76 neoverse_n3_reset_func, \ 77 neoverse_n3_core_pwr_dwn 78