1*ba6b6949SGovindraj Raja/* 2*ba6b6949SGovindraj Raja * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3*ba6b6949SGovindraj Raja * 4*ba6b6949SGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 5*ba6b6949SGovindraj Raja */ 6*ba6b6949SGovindraj Raja 7*ba6b6949SGovindraj Raja#include <arch.h> 8*ba6b6949SGovindraj Raja#include <asm_macros.S> 9*ba6b6949SGovindraj Raja#include <common/bl_common.h> 10*ba6b6949SGovindraj Raja#include <neoverse_n3.h> 11*ba6b6949SGovindraj Raja#include <cpu_macros.S> 12*ba6b6949SGovindraj Raja#include <plat_macros.S> 13*ba6b6949SGovindraj Raja 14*ba6b6949SGovindraj Raja/* Hardware handled coherency */ 15*ba6b6949SGovindraj Raja#if HW_ASSISTED_COHERENCY == 0 16*ba6b6949SGovindraj Raja#error "Neoverse-N3 must be compiled with HW_ASSISTED_COHERENCY enabled" 17*ba6b6949SGovindraj Raja#endif 18*ba6b6949SGovindraj Raja 19*ba6b6949SGovindraj Raja/* 64-bit only core */ 20*ba6b6949SGovindraj Raja#if CTX_INCLUDE_AARCH32_REGS == 1 21*ba6b6949SGovindraj Raja#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22*ba6b6949SGovindraj Raja#endif 23*ba6b6949SGovindraj Raja 24*ba6b6949SGovindraj Rajacpu_reset_func_start neoverse_n3 25*ba6b6949SGovindraj Raja /* Disable speculative loads */ 26*ba6b6949SGovindraj Raja msr SSBS, xzr 27*ba6b6949SGovindraj Rajacpu_reset_func_end neoverse_n3 28*ba6b6949SGovindraj Raja 29*ba6b6949SGovindraj Raja /* ---------------------------------------------------- 30*ba6b6949SGovindraj Raja * HW will do the cache maintenance while powering down 31*ba6b6949SGovindraj Raja * ---------------------------------------------------- 32*ba6b6949SGovindraj Raja */ 33*ba6b6949SGovindraj Rajafunc neoverse_n3_core_pwr_dwn 34*ba6b6949SGovindraj Raja /* --------------------------------------------------- 35*ba6b6949SGovindraj Raja * Enable CPU power down bit in power control register 36*ba6b6949SGovindraj Raja * --------------------------------------------------- 37*ba6b6949SGovindraj Raja */ 38*ba6b6949SGovindraj Raja sysreg_bit_set NEOVERSE_N3_CPUPWRCTLR_EL1, NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 39*ba6b6949SGovindraj Raja isb 40*ba6b6949SGovindraj Raja ret 41*ba6b6949SGovindraj Rajaendfunc neoverse_n3_core_pwr_dwn 42*ba6b6949SGovindraj Raja 43*ba6b6949SGovindraj Rajaerrata_report_shim neoverse_n3 44*ba6b6949SGovindraj Raja 45*ba6b6949SGovindraj Raja /* --------------------------------------------- 46*ba6b6949SGovindraj Raja * This function provides Neoverse-N3 specific 47*ba6b6949SGovindraj Raja * register information for crash reporting. 48*ba6b6949SGovindraj Raja * It needs to return with x6 pointing to 49*ba6b6949SGovindraj Raja * a list of register names in ascii and 50*ba6b6949SGovindraj Raja * x8 - x15 having values of registers to be 51*ba6b6949SGovindraj Raja * reported. 52*ba6b6949SGovindraj Raja * --------------------------------------------- 53*ba6b6949SGovindraj Raja */ 54*ba6b6949SGovindraj Raja.section .rodata.neoverse_n3_regs, "aS" 55*ba6b6949SGovindraj Rajaneoverse_n3_regs: /* The ascii list of register names to be reported */ 56*ba6b6949SGovindraj Raja .asciz "cpuectlr_el1", "" 57*ba6b6949SGovindraj Raja 58*ba6b6949SGovindraj Rajafunc neoverse_n3_cpu_reg_dump 59*ba6b6949SGovindraj Raja adr x6, neoverse_n3_regs 60*ba6b6949SGovindraj Raja mrs x8, NEOVERSE_N3_CPUECTLR_EL1 61*ba6b6949SGovindraj Raja ret 62*ba6b6949SGovindraj Rajaendfunc neoverse_n3_cpu_reg_dump 63*ba6b6949SGovindraj Raja 64*ba6b6949SGovindraj Rajadeclare_cpu_ops neoverse_n3, NEOVERSE_N3_MIDR, \ 65*ba6b6949SGovindraj Raja neoverse_n3_reset_func, \ 66*ba6b6949SGovindraj Raja neoverse_n3_core_pwr_dwn 67