1ba6b6949SGovindraj Raja/* 2ba6b6949SGovindraj Raja * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3ba6b6949SGovindraj Raja * 4ba6b6949SGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 5ba6b6949SGovindraj Raja */ 6ba6b6949SGovindraj Raja 7ba6b6949SGovindraj Raja#include <arch.h> 8ba6b6949SGovindraj Raja#include <asm_macros.S> 9ba6b6949SGovindraj Raja#include <common/bl_common.h> 10ba6b6949SGovindraj Raja#include <neoverse_n3.h> 11ba6b6949SGovindraj Raja#include <cpu_macros.S> 12ba6b6949SGovindraj Raja#include <plat_macros.S> 13ba6b6949SGovindraj Raja 14ba6b6949SGovindraj Raja/* Hardware handled coherency */ 15ba6b6949SGovindraj Raja#if HW_ASSISTED_COHERENCY == 0 16ba6b6949SGovindraj Raja#error "Neoverse-N3 must be compiled with HW_ASSISTED_COHERENCY enabled" 17ba6b6949SGovindraj Raja#endif 18ba6b6949SGovindraj Raja 19ba6b6949SGovindraj Raja/* 64-bit only core */ 20ba6b6949SGovindraj Raja#if CTX_INCLUDE_AARCH32_REGS == 1 21ba6b6949SGovindraj Raja#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22ba6b6949SGovindraj Raja#endif 23ba6b6949SGovindraj Raja 24ba6b6949SGovindraj Rajacpu_reset_func_start neoverse_n3 25ba6b6949SGovindraj Raja /* Disable speculative loads */ 26ba6b6949SGovindraj Raja msr SSBS, xzr 27*6fbc98b1SYounghyun Park 28*6fbc98b1SYounghyun Park#if NEOVERSE_Nx_EXTERNAL_LLC 29*6fbc98b1SYounghyun Park /* Some systems may have External LLC, core needs to be made aware */ 30*6fbc98b1SYounghyun Park sysreg_bit_set NEOVERSE_N3_CPUECTLR_EL1, NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT 31*6fbc98b1SYounghyun Park#endif 32ba6b6949SGovindraj Rajacpu_reset_func_end neoverse_n3 33ba6b6949SGovindraj Raja 34ba6b6949SGovindraj Raja /* ---------------------------------------------------- 35ba6b6949SGovindraj Raja * HW will do the cache maintenance while powering down 36ba6b6949SGovindraj Raja * ---------------------------------------------------- 37ba6b6949SGovindraj Raja */ 38ba6b6949SGovindraj Rajafunc neoverse_n3_core_pwr_dwn 39ba6b6949SGovindraj Raja /* --------------------------------------------------- 40ba6b6949SGovindraj Raja * Enable CPU power down bit in power control register 41ba6b6949SGovindraj Raja * --------------------------------------------------- 42ba6b6949SGovindraj Raja */ 43ba6b6949SGovindraj Raja sysreg_bit_set NEOVERSE_N3_CPUPWRCTLR_EL1, NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 44ba6b6949SGovindraj Raja isb 45ba6b6949SGovindraj Raja ret 46ba6b6949SGovindraj Rajaendfunc neoverse_n3_core_pwr_dwn 47ba6b6949SGovindraj Raja 48ba6b6949SGovindraj Rajaerrata_report_shim neoverse_n3 49ba6b6949SGovindraj Raja 50ba6b6949SGovindraj Raja /* --------------------------------------------- 51ba6b6949SGovindraj Raja * This function provides Neoverse-N3 specific 52ba6b6949SGovindraj Raja * register information for crash reporting. 53ba6b6949SGovindraj Raja * It needs to return with x6 pointing to 54ba6b6949SGovindraj Raja * a list of register names in ascii and 55ba6b6949SGovindraj Raja * x8 - x15 having values of registers to be 56ba6b6949SGovindraj Raja * reported. 57ba6b6949SGovindraj Raja * --------------------------------------------- 58ba6b6949SGovindraj Raja */ 59ba6b6949SGovindraj Raja.section .rodata.neoverse_n3_regs, "aS" 60ba6b6949SGovindraj Rajaneoverse_n3_regs: /* The ascii list of register names to be reported */ 61ba6b6949SGovindraj Raja .asciz "cpuectlr_el1", "" 62ba6b6949SGovindraj Raja 63ba6b6949SGovindraj Rajafunc neoverse_n3_cpu_reg_dump 64ba6b6949SGovindraj Raja adr x6, neoverse_n3_regs 65ba6b6949SGovindraj Raja mrs x8, NEOVERSE_N3_CPUECTLR_EL1 66ba6b6949SGovindraj Raja ret 67ba6b6949SGovindraj Rajaendfunc neoverse_n3_cpu_reg_dump 68ba6b6949SGovindraj Raja 69ba6b6949SGovindraj Rajadeclare_cpu_ops neoverse_n3, NEOVERSE_N3_MIDR, \ 70ba6b6949SGovindraj Raja neoverse_n3_reset_func, \ 71ba6b6949SGovindraj Raja neoverse_n3_core_pwr_dwn 72