1/* 2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11 12/* Hardware handled coherency */ 13#if HW_ASSISTED_COHERENCY == 0 14#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 15#endif 16 17/* 64-bit only core */ 18#if CTX_INCLUDE_AARCH32_REGS == 1 19#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 20#endif 21 22/* -------------------------------------------------- 23 * Errata Workaround for Neoverse N2 Erratum 2002655. 24 * This applies to revision r0p0 of Neoverse N2. it is still open. 25 * Inputs: 26 * x0: variant[4:7] and revision[0:3] of current cpu. 27 * Shall clobber: x0-x17 28 * -------------------------------------------------- 29 */ 30func errata_n2_2002655_wa 31 /* Check revision. */ 32 mov x17, x30 33 bl check_errata_2002655 34 cbz x0, 1f 35 36 /* Apply instruction patching sequence */ 37 ldr x0,=0x6 38 msr S3_6_c15_c8_0,x0 39 ldr x0,=0xF3A08002 40 msr S3_6_c15_c8_2,x0 41 ldr x0,=0xFFF0F7FE 42 msr S3_6_c15_c8_3,x0 43 ldr x0,=0x40000001003ff 44 msr S3_6_c15_c8_1,x0 45 ldr x0,=0x7 46 msr S3_6_c15_c8_0,x0 47 ldr x0,=0xBF200000 48 msr S3_6_c15_c8_2,x0 49 ldr x0,=0xFFEF0000 50 msr S3_6_c15_c8_3,x0 51 ldr x0,=0x40000001003f3 52 msr S3_6_c15_c8_1,x0 53 isb 541: 55 ret x17 56endfunc errata_n2_2002655_wa 57 58func check_errata_2002655 59 /* Applies to r0p0 */ 60 mov x1, #0x00 61 b cpu_rev_var_ls 62endfunc check_errata_2002655 63 64/* --------------------------------------------------------------- 65 * Errata Workaround for Neoverse N2 Erratum 2067956. 66 * This applies to revision r0p0 of Neoverse N2 and is still open. 67 * Inputs: 68 * x0: variant[4:7] and revision[0:3] of current cpu. 69 * Shall clobber: x0-x17 70 * --------------------------------------------------------------- 71 */ 72func errata_n2_2067956_wa 73 /* Compare x0 against revision r0p0 */ 74 mov x17, x30 75 bl check_errata_2067956 76 cbz x0, 1f 77 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 78 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 79 msr NEOVERSE_N2_CPUACTLR_EL1, x1 801: 81 ret x17 82endfunc errata_n2_2067956_wa 83 84func check_errata_2067956 85 /* Applies to r0p0 */ 86 mov x1, #0x00 87 b cpu_rev_var_ls 88endfunc check_errata_2067956 89 90/* --------------------------------------------------------------- 91 * Errata Workaround for Neoverse N2 Erratum 2025414. 92 * This applies to revision r0p0 of Neoverse N2 and is still open. 93 * Inputs: 94 * x0: variant[4:7] and revision[0:3] of current cpu. 95 * Shall clobber: x0-x17 96 * --------------------------------------------------------------- 97 */ 98func errata_n2_2025414_wa 99 /* Compare x0 against revision r0p0 */ 100 mov x17, x30 101 bl check_errata_2025414 102 cbz x0, 1f 103 mrs x1, NEOVERSE_N2_CPUECTLR_EL1 104 orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 105 msr NEOVERSE_N2_CPUECTLR_EL1, x1 106 1071: 108 ret x17 109endfunc errata_n2_2025414_wa 110 111func check_errata_2025414 112 /* Applies to r0p0 */ 113 mov x1, #0x00 114 b cpu_rev_var_ls 115endfunc check_errata_2025414 116 117/* --------------------------------------------------------------- 118 * Errata Workaround for Neoverse N2 Erratum 2189731. 119 * This applies to revision r0p0 of Neoverse N2 and is still open. 120 * Inputs: 121 * x0: variant[4:7] and revision[0:3] of current cpu. 122 * Shall clobber: x0-x17 123 * --------------------------------------------------------------- 124 */ 125func errata_n2_2189731_wa 126 /* Compare x0 against revision r0p0 */ 127 mov x17, x30 128 bl check_errata_2189731 129 cbz x0, 1f 130 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 131 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 132 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 133 1341: 135 ret x17 136endfunc errata_n2_2189731_wa 137 138func check_errata_2189731 139 /* Applies to r0p0 */ 140 mov x1, #0x00 141 b cpu_rev_var_ls 142endfunc check_errata_2189731 143 144/* -------------------------------------------------- 145 * Errata Workaround for Neoverse N2 Erratum 2138956. 146 * This applies to revision r0p0 of Neoverse N2. it is still open. 147 * Inputs: 148 * x0: variant[4:7] and revision[0:3] of current cpu. 149 * Shall clobber: x0-x17 150 * -------------------------------------------------- 151 */ 152func errata_n2_2138956_wa 153 /* Check revision. */ 154 mov x17, x30 155 bl check_errata_2138956 156 cbz x0, 1f 157 158 /* Apply instruction patching sequence */ 159 ldr x0,=0x3 160 msr S3_6_c15_c8_0,x0 161 ldr x0,=0xF3A08002 162 msr S3_6_c15_c8_2,x0 163 ldr x0,=0xFFF0F7FE 164 msr S3_6_c15_c8_3,x0 165 ldr x0,=0x10002001003FF 166 msr S3_6_c15_c8_1,x0 167 ldr x0,=0x4 168 msr S3_6_c15_c8_0,x0 169 ldr x0,=0xBF200000 170 msr S3_6_c15_c8_2,x0 171 ldr x0,=0xFFEF0000 172 msr S3_6_c15_c8_3,x0 173 ldr x0,=0x10002001003F3 174 msr S3_6_c15_c8_1,x0 175 isb 1761: 177 ret x17 178endfunc errata_n2_2138956_wa 179 180func check_errata_2138956 181 /* Applies to r0p0 */ 182 mov x1, #0x00 183 b cpu_rev_var_ls 184endfunc check_errata_2138956 185 186/* -------------------------------------------------- 187 * Errata Workaround for Neoverse N2 Erratum 2138953. 188 * This applies to revision r0p0 of Neoverse N2. it is still open. 189 * Inputs: 190 * x0: variant[4:7] and revision[0:3] of current cpu. 191 * Shall clobber: x0-x1, x17 192 * -------------------------------------------------- 193 */ 194func errata_n2_2138953_wa 195 /* Check revision. */ 196 mov x17, x30 197 bl check_errata_2138953 198 cbz x0, 1f 199 200 /* Apply instruction patching sequence */ 201 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 202 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 203 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 204 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 2051: 206 ret x17 207endfunc errata_n2_2138953_wa 208 209func check_errata_2138953 210 /* Applies to r0p0 */ 211 mov x1, #0x00 212 b cpu_rev_var_ls 213endfunc check_errata_2138953 214 215 /* ------------------------------------------- 216 * The CPU Ops reset function for Neoverse N2. 217 * ------------------------------------------- 218 */ 219func neoverse_n2_reset_func 220 mov x19, x30 221 222 /* Check if the PE implements SSBS */ 223 mrs x0, id_aa64pfr1_el1 224 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 225 b.eq 1f 226 227 /* Disable speculative loads */ 228 msr SSBS, xzr 2291: 230 /* Force all cacheable atomic instructions to be near */ 231 mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 232 orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 233 msr NEOVERSE_N2_CPUACTLR2_EL1, x0 234 235#if ERRATA_N2_2067956 236 mov x0, x18 237 bl errata_n2_2067956_wa 238#endif 239 240#if ERRATA_N2_2025414 241 mov x0, x18 242 bl errata_n2_2025414_wa 243#endif 244 245#if ERRATA_N2_2189731 246 mov x0, x18 247 bl errata_n2_2189731_wa 248#endif 249 250 251#if ERRATA_N2_2138956 252 mov x0, x18 253 bl errata_n2_2138956_wa 254#endif 255 256#if ERRATA_N2_2138953 257 mov x0, x18 258 bl errata_n2_2138953_wa 259#endif 260 261#if ENABLE_AMU 262 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 263 mrs x0, cptr_el3 264 orr x0, x0, #TAM_BIT 265 msr cptr_el3, x0 266 267 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 268 mrs x0, cptr_el2 269 orr x0, x0, #TAM_BIT 270 msr cptr_el2, x0 271 272 /* No need to enable the counters as this would be done at el3 exit */ 273#endif 274 275#if NEOVERSE_Nx_EXTERNAL_LLC 276 /* Some systems may have External LLC, core needs to be made aware */ 277 mrs x0, NEOVERSE_N2_CPUECTLR_EL1 278 orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 279 msr NEOVERSE_N2_CPUECTLR_EL1, x0 280#endif 281 282 bl cpu_get_rev_var 283 mov x18, x0 284 285#if ERRATA_N2_2002655 286 mov x0, x18 287 bl errata_n2_2002655_wa 288#endif 289 290 isb 291 ret x19 292endfunc neoverse_n2_reset_func 293 294func neoverse_n2_core_pwr_dwn 295 /* --------------------------------------------------- 296 * Enable CPU power down bit in power control register 297 * No need to do cache maintenance here. 298 * --------------------------------------------------- 299 */ 300 mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 301 orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT 302 msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 303 isb 304 ret 305endfunc neoverse_n2_core_pwr_dwn 306 307#if REPORT_ERRATA 308/* 309 * Errata printing function for Neoverse N2 cores. Must follow AAPCS. 310 */ 311func neoverse_n2_errata_report 312 stp x8, x30, [sp, #-16]! 313 314 bl cpu_get_rev_var 315 mov x8, x0 316 317 /* 318 * Report all errata. The revision-variant information is passed to 319 * checking functions of each errata. 320 */ 321 report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 322 report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 323 report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 324 report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 325 report_errata ERRATA_N2_2138956, neoverse_n2, 2138956 326 report_errata ERRATA_N2_2138953, neoverse_n2, 2138953 327 328 ldp x8, x30, [sp], #16 329 ret 330endfunc neoverse_n2_errata_report 331#endif 332 333 /* --------------------------------------------- 334 * This function provides Neoverse N2 specific 335 * register information for crash reporting. 336 * It needs to return with x6 pointing to 337 * a list of register names in ASCII and 338 * x8 - x15 having values of registers to be 339 * reported. 340 * --------------------------------------------- 341 */ 342.section .rodata.neoverse_n2_regs, "aS" 343neoverse_n2_regs: /* The ASCII list of register names to be reported */ 344 .asciz "cpupwrctlr_el1", "" 345 346func neoverse_n2_cpu_reg_dump 347 adr x6, neoverse_n2_regs 348 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 349 ret 350endfunc neoverse_n2_cpu_reg_dump 351 352declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 353 neoverse_n2_reset_func, \ 354 neoverse_n2_core_pwr_dwn 355