1/* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11#include "wa_cve_2022_23960_bhb_vector.S" 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23#if WORKAROUND_CVE_2022_23960 24 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 25#endif /* WORKAROUND_CVE_2022_23960 */ 26 27/* 28 * ERRATA_DSU_2313941: 29 * The errata is defined in dsu_helpers.S and applies to Neoverse N2. 30 * Henceforth creating symbolic names to the already existing errata 31 * workaround functions to get them registered under the Errata Framework. 32 */ 33.equ check_erratum_neoverse_n2_2313941, check_errata_dsu_2313941 34.equ erratum_neoverse_n2_2313941_wa, errata_dsu_2313941_wa 35add_erratum_entry neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 36 37/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 38workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 39 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46) 40workaround_reset_end neoverse_n2, CVE(2024, 5660) 41 42check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3) 43 44workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 45 /* Apply instruction patching sequence */ 46 ldr x0,=0x6 47 msr S3_6_c15_c8_0,x0 48 ldr x0,=0xF3A08002 49 msr S3_6_c15_c8_2,x0 50 ldr x0,=0xFFF0F7FE 51 msr S3_6_c15_c8_3,x0 52 ldr x0,=0x40000001003ff 53 msr S3_6_c15_c8_1,x0 54 ldr x0,=0x7 55 msr S3_6_c15_c8_0,x0 56 ldr x0,=0xBF200000 57 msr S3_6_c15_c8_2,x0 58 ldr x0,=0xFFEF0000 59 msr S3_6_c15_c8_3,x0 60 ldr x0,=0x40000001003f3 61 msr S3_6_c15_c8_1,x0 62workaround_reset_end neoverse_n2, ERRATUM(2002655) 63 64check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) 65 66workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 67 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 68workaround_reset_end neoverse_n2, ERRATUM(2025414) 69 70check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) 71 72workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 73 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 74workaround_reset_end neoverse_n2, ERRATUM(2067956) 75 76check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) 77 78workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 79 /* Stash ERRSELR_EL1 in x2 */ 80 mrs x2, ERRSELR_EL1 81 82 /* Select error record 0 and clear ED bit */ 83 msr ERRSELR_EL1, xzr 84 mrs x1, ERXCTLR_EL1 85 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 86 msr ERXCTLR_EL1, x1 87 88 /* Restore ERRSELR_EL1 from x2 */ 89 msr ERRSELR_EL1, x2 90workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB 91 92check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0) 93 94workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 95 /* Apply instruction patching sequence */ 96 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 97 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 98 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 99 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 100workaround_reset_end neoverse_n2, ERRATUM(2138953) 101 102check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3) 103 104workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 105 /* Apply instruction patching sequence */ 106 ldr x0,=0x3 107 msr S3_6_c15_c8_0,x0 108 ldr x0,=0xF3A08002 109 msr S3_6_c15_c8_2,x0 110 ldr x0,=0xFFF0F7FE 111 msr S3_6_c15_c8_3,x0 112 ldr x0,=0x10002001003FF 113 msr S3_6_c15_c8_1,x0 114 ldr x0,=0x4 115 msr S3_6_c15_c8_0,x0 116 ldr x0,=0xBF200000 117 msr S3_6_c15_c8_2,x0 118 ldr x0,=0xFFEF0000 119 msr S3_6_c15_c8_3,x0 120 ldr x0,=0x10002001003F3 121 msr S3_6_c15_c8_1,x0 122workaround_reset_end neoverse_n2, ERRATUM(2138956) 123 124check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) 125 126 127workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 128 /* Apply instruction patching sequence */ 129 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 130workaround_reset_end neoverse_n2, ERRATUM(2138958) 131 132check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) 133 134workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 135 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 136workaround_reset_end neoverse_n2, ERRATUM(2189731) 137 138check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) 139 140workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 141 /* Apply instruction patching sequence */ 142 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 143 ldr x0, =0x2 144 msr S3_6_c15_c8_0, x0 145 ldr x0, =0x10F600E000 146 msr S3_6_c15_c8_2, x0 147 ldr x0, =0x10FF80E000 148 msr S3_6_c15_c8_3, x0 149 ldr x0, =0x80000000003FF 150 msr S3_6_c15_c8_1, x0 151workaround_reset_end neoverse_n2, ERRATUM(2242400) 152 153check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) 154 155workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 156 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 157workaround_reset_end neoverse_n2, ERRATUM(2242415) 158 159check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) 160 161workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 162 /* Apply instruction patching sequence */ 163 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 164workaround_reset_end neoverse_n2, ERRATUM(2280757) 165 166check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) 167 168workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 169 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 170 * the workaround. Second call clears it to undo it. */ 171 sysreg_bit_toggle NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 172workaround_runtime_end neoverse_n2, ERRATUM(2326639) 173 174check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) 175 176workaround_runtime_start neoverse_n2, ERRATUM(2340933), ERRATA_N2_2340933 177 /* Set bit 61 in CPUACTLR5_EL1 */ 178 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61) 179workaround_runtime_end neoverse_n2, ERRATUM(2340933) 180 181check_erratum_ls neoverse_n2, ERRATUM(2340933), CPU_REV(0, 0) 182 183workaround_runtime_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952 184 /* Set TXREQ to STATIC and full L2 TQ size */ 185 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 186 mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL 187 bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH 188 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 189workaround_runtime_end neoverse_n2, ERRATUM(2346952) 190 191check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2) 192 193workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 194 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM 195 * ST to behave like PLD/PFRM LD and not cause 196 * invalidations to other PE caches. 197 */ 198 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 199workaround_reset_end neoverse_n2, ERRATUM(2376738) 200 201check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3) 202 203workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 204 /*Set bit 40 in ACTLR2_EL1 */ 205 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 206workaround_reset_end neoverse_n2, ERRATUM(2388450) 207 208check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) 209 210workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014 211 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 212 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 213 sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 214workaround_reset_end neoverse_n2, ERRATUM(2743014) 215 216check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2) 217 218workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 219 /* dsb before isb of power down sequence */ 220 dsb sy 221workaround_runtime_end neoverse_n2, ERRATUM(2743089) 222 223check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) 224 225workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511 226 /* Set bit 47 in ACTLR3_EL1 */ 227 sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 228workaround_reset_end neoverse_n2, ERRATUM(2779511) 229 230check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2) 231 232workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 233#if IMAGE_BL31 234 /* 235 * The Neoverse-N2 generic vectors are overridden to apply errata 236 * mitigation on exception entry from lower ELs. 237 */ 238 override_vector_table wa_cve_vbar_neoverse_n2 239#endif /* IMAGE_BL31 */ 240workaround_reset_end neoverse_n2, CVE(2022,23960) 241 242check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 243 244 /* ------------------------------------------- 245 * The CPU Ops reset function for Neoverse N2. 246 * ------------------------------------------- 247 */ 248cpu_reset_func_start neoverse_n2 249 250 /* Check if the PE implements SSBS */ 251 mrs x0, id_aa64pfr1_el1 252 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 253 b.eq 1f 254 255 /* Disable speculative loads */ 256 msr SSBS, xzr 2571: 258 /* Force all cacheable atomic instructions to be near */ 259 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 260 261#if ENABLE_FEAT_AMU 262 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 263 sysreg_bit_clear cptr_el3, TAM_BIT 264 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 265 sysreg_bit_clear cptr_el2, TAM_BIT 266 /* No need to enable the counters as this would be done at el3 exit */ 267#endif 268 269#if NEOVERSE_Nx_EXTERNAL_LLC 270 /* Some systems may have External LLC, core needs to be made aware */ 271 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 272#endif 273cpu_reset_func_end neoverse_n2 274 275func neoverse_n2_core_pwr_dwn 276 apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478, NO_GET_CPU_REV 277 apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV 278 279 /* --------------------------------------------------- 280 * Enable CPU power down bit in power control register 281 * No need to do cache maintenance here. 282 * --------------------------------------------------- 283 */ 284 sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT 285 286 apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089, NO_GET_CPU_REV 287 288 isb 289 ret 290endfunc neoverse_n2_core_pwr_dwn 291 292 /* --------------------------------------------- 293 * This function provides Neoverse N2 specific 294 * register information for crash reporting. 295 * It needs to return with x6 pointing to 296 * a list of register names in ASCII and 297 * x8 - x15 having values of registers to be 298 * reported. 299 * --------------------------------------------- 300 */ 301.section .rodata.neoverse_n2_regs, "aS" 302neoverse_n2_regs: /* The ASCII list of register names to be reported */ 303 .asciz "cpupwrctlr_el1", "" 304 305func neoverse_n2_cpu_reg_dump 306 adr x6, neoverse_n2_regs 307 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 308 ret 309endfunc neoverse_n2_cpu_reg_dump 310 311declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 312 neoverse_n2_reset_func, \ 313 neoverse_n2_core_pwr_dwn 314