1/* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <dsu_macros.S> 11#include <neoverse_n2.h> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24.global check_erratum_neoverse_n2_3701773 25 26#if WORKAROUND_CVE_2022_23960 27 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 28#endif /* WORKAROUND_CVE_2022_23960 */ 29 30cpu_reset_prologue neoverse_n2 31 32workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 33 /* Apply instruction patching sequence */ 34 ldr x0,=0x6 35 msr S3_6_c15_c8_0,x0 36 ldr x0,=0xF3A08002 37 msr S3_6_c15_c8_2,x0 38 ldr x0,=0xFFF0F7FE 39 msr S3_6_c15_c8_3,x0 40 ldr x0,=0x40000001003ff 41 msr S3_6_c15_c8_1,x0 42 ldr x0,=0x7 43 msr S3_6_c15_c8_0,x0 44 ldr x0,=0xBF200000 45 msr S3_6_c15_c8_2,x0 46 ldr x0,=0xFFEF0000 47 msr S3_6_c15_c8_3,x0 48 ldr x0,=0x40000001003f3 49 msr S3_6_c15_c8_1,x0 50workaround_reset_end neoverse_n2, ERRATUM(2002655) 51 52check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) 53 54workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 55 /* Stash ERRSELR_EL1 in x2 */ 56 mrs x2, ERRSELR_EL1 57 58 /* Select error record 0 and clear ED bit */ 59 msr ERRSELR_EL1, xzr 60 mrs x1, ERXCTLR_EL1 61 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 62 msr ERXCTLR_EL1, x1 63 64 /* Restore ERRSELR_EL1 from x2 */ 65 msr ERRSELR_EL1, x2 66workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB 67 68check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0) 69 70workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 71 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 72workaround_reset_end neoverse_n2, ERRATUM(2025414) 73 74check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) 75 76workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 77 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 78workaround_reset_end neoverse_n2, ERRATUM(2067956) 79 80check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) 81 82workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 83 /* Apply instruction patching sequence */ 84 ldr x0,=0x3 85 msr S3_6_c15_c8_0,x0 86 ldr x0,=0xF3A08002 87 msr S3_6_c15_c8_2,x0 88 ldr x0,=0xFFF0F7FE 89 msr S3_6_c15_c8_3,x0 90 ldr x0,=0x10002001003FF 91 msr S3_6_c15_c8_1,x0 92 ldr x0,=0x4 93 msr S3_6_c15_c8_0,x0 94 ldr x0,=0xBF200000 95 msr S3_6_c15_c8_2,x0 96 ldr x0,=0xFFEF0000 97 msr S3_6_c15_c8_3,x0 98 ldr x0,=0x10002001003F3 99 msr S3_6_c15_c8_1,x0 100workaround_reset_end neoverse_n2, ERRATUM(2138956) 101 102check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) 103 104 105workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 106 /* Apply instruction patching sequence */ 107 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 108workaround_reset_end neoverse_n2, ERRATUM(2138958) 109 110check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) 111 112workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 113 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 114workaround_reset_end neoverse_n2, ERRATUM(2189731) 115 116check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) 117 118workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 119 /* Apply instruction patching sequence */ 120 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 121 ldr x0, =0x2 122 msr S3_6_c15_c8_0, x0 123 ldr x0, =0x10F600E000 124 msr S3_6_c15_c8_2, x0 125 ldr x0, =0x10FF80E000 126 msr S3_6_c15_c8_3, x0 127 ldr x0, =0x80000000003FF 128 msr S3_6_c15_c8_1, x0 129workaround_reset_end neoverse_n2, ERRATUM(2242400) 130 131check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) 132 133workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 134 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 135workaround_reset_end neoverse_n2, ERRATUM(2242415) 136 137check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) 138 139workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 140 /* Apply instruction patching sequence */ 141 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 142workaround_reset_end neoverse_n2, ERRATUM(2280757) 143 144check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) 145 146workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941 147 errata_dsu_2313941_wa_impl 148workaround_reset_end neoverse_n2, ERRATUM(2313941) 149 150check_erratum_custom_start neoverse_n2, ERRATUM(2313941) 151 branch_if_scu_not_present 2f /* label 1 is used in the macro */ 152 check_errata_dsu_2313941_impl 153 2: 154 ret 155check_erratum_custom_end neoverse_n2, ERRATUM(2313941) 156 157.global erratum_neoverse_n2_2326639_wa 158workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 159 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 160 * the workaround. Second call clears it to undo it. */ 161 sysreg_bit_toggle NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 162workaround_runtime_end neoverse_n2, ERRATUM(2326639) 163 164check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) 165 166workaround_reset_start neoverse_n2, ERRATUM(2340933), ERRATA_N2_2340933 167 /* Set bit 61 in CPUACTLR5_EL1 */ 168 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61) 169workaround_reset_end neoverse_n2, ERRATUM(2340933) 170 171check_erratum_ls neoverse_n2, ERRATUM(2340933), CPU_REV(0, 0) 172 173workaround_reset_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952 174 /* Set TXREQ to STATIC and full L2 TQ size */ 175 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 176 mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL 177 bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH 178 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 179workaround_reset_end neoverse_n2, ERRATUM(2346952) 180 181check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2) 182 183workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 184 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM 185 * ST to behave like PLD/PFRM LD and not cause 186 * invalidations to other PE caches. 187 */ 188 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 189workaround_reset_end neoverse_n2, ERRATUM(2376738) 190 191check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3) 192 193workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 194 /*Set bit 40 in ACTLR2_EL1 */ 195 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 196workaround_reset_end neoverse_n2, ERRATUM(2388450) 197 198check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) 199 200workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014 201 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 202 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 203 sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 204workaround_reset_end neoverse_n2, ERRATUM(2743014) 205 206check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2) 207 208workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 209 /* dsb before isb of power down sequence */ 210 dsb sy 211workaround_runtime_end neoverse_n2, ERRATUM(2743089) 212 213check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) 214 215workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511 216 /* Set bit 47 in ACTLR3_EL1 */ 217 sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 218workaround_reset_end neoverse_n2, ERRATUM(2779511) 219 220check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2) 221 222add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773 223 224check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3) 225 226workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 227#if IMAGE_BL31 228 /* 229 * The Neoverse-N2 generic vectors are overridden to apply errata 230 * mitigation on exception entry from lower ELs. 231 */ 232 override_vector_table wa_cve_vbar_neoverse_n2 233#endif /* IMAGE_BL31 */ 234workaround_reset_end neoverse_n2, CVE(2022,23960) 235 236check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 237 238/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 239workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 240 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46) 241workaround_reset_end neoverse_n2, CVE(2024, 5660) 242 243check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3) 244 245 /* ------------------------------------------- 246 * The CPU Ops reset function for Neoverse N2. 247 * ------------------------------------------- 248 */ 249cpu_reset_func_start neoverse_n2 250 251 /* Check if the PE implements SSBS */ 252 mrs x0, id_aa64pfr1_el1 253 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 254 b.eq 1f 255 256 /* Disable speculative loads */ 257 msr SSBS, xzr 2581: 259 /* Force all cacheable atomic instructions to be near */ 260 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 261 262#if ENABLE_FEAT_AMU 263 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 264 sysreg_bit_clear cptr_el3, TAM_BIT 265 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 266 sysreg_bit_clear cptr_el2, TAM_BIT 267 /* No need to enable the counters as this would be done at el3 exit */ 268#endif 269 270#if NEOVERSE_Nx_EXTERNAL_LLC 271 /* Some systems may have External LLC, core needs to be made aware */ 272 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 273#endif 274#if NEOVERSE_N2_PREFETCHER_DISABLE 275 /* Disable region prefetcher for L2 cache perf measurement */ 276 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFDIS_BIT 277#endif 278cpu_reset_func_end neoverse_n2 279 280func neoverse_n2_core_pwr_dwn 281 apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 282 apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV 283 284 /* --------------------------------------------------- 285 * Enable CPU power down bit in power control register 286 * No need to do cache maintenance here. 287 * --------------------------------------------------- 288 */ 289 sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT 290 291 apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089, NO_GET_CPU_REV 292 293 isb 294 ret 295endfunc neoverse_n2_core_pwr_dwn 296 297 /* --------------------------------------------- 298 * This function provides Neoverse N2 specific 299 * register information for crash reporting. 300 * It needs to return with x6 pointing to 301 * a list of register names in ASCII and 302 * x8 - x15 having values of registers to be 303 * reported. 304 * --------------------------------------------- 305 */ 306.section .rodata.neoverse_n2_regs, "aS" 307neoverse_n2_regs: /* The ASCII list of register names to be reported */ 308 .asciz "cpupwrctlr_el1", "" 309 310func neoverse_n2_cpu_reg_dump 311 adr x6, neoverse_n2_regs 312 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 313 ret 314endfunc neoverse_n2_cpu_reg_dump 315 316declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 317 neoverse_n2_reset_func, \ 318 neoverse_n2_core_pwr_dwn 319