1/* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <dsu_macros.S> 11#include <neoverse_n2.h> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24.global check_erratum_neoverse_n2_3701773 25 26add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773 27 28check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3) 29 30#if WORKAROUND_CVE_2022_23960 31 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 32#endif /* WORKAROUND_CVE_2022_23960 */ 33 34cpu_reset_prologue neoverse_n2 35 36workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941 37 errata_dsu_2313941_wa_impl 38workaround_reset_end neoverse_n2, ERRATUM(2313941) 39 40check_erratum_custom_start neoverse_n2, ERRATUM(2313941) 41 branch_if_scu_not_present 2f /* label 1 is used in the macro */ 42 check_errata_dsu_2313941_impl 43 2: 44 ret 45check_erratum_custom_end neoverse_n2, ERRATUM(2313941) 46 47/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 48workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 49 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46) 50workaround_reset_end neoverse_n2, CVE(2024, 5660) 51 52check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3) 53 54workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 55 /* Apply instruction patching sequence */ 56 ldr x0,=0x6 57 msr S3_6_c15_c8_0,x0 58 ldr x0,=0xF3A08002 59 msr S3_6_c15_c8_2,x0 60 ldr x0,=0xFFF0F7FE 61 msr S3_6_c15_c8_3,x0 62 ldr x0,=0x40000001003ff 63 msr S3_6_c15_c8_1,x0 64 ldr x0,=0x7 65 msr S3_6_c15_c8_0,x0 66 ldr x0,=0xBF200000 67 msr S3_6_c15_c8_2,x0 68 ldr x0,=0xFFEF0000 69 msr S3_6_c15_c8_3,x0 70 ldr x0,=0x40000001003f3 71 msr S3_6_c15_c8_1,x0 72workaround_reset_end neoverse_n2, ERRATUM(2002655) 73 74check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) 75 76workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 77 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 78workaround_reset_end neoverse_n2, ERRATUM(2025414) 79 80check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) 81 82workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 83 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 84workaround_reset_end neoverse_n2, ERRATUM(2067956) 85 86check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) 87 88workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 89 /* Stash ERRSELR_EL1 in x2 */ 90 mrs x2, ERRSELR_EL1 91 92 /* Select error record 0 and clear ED bit */ 93 msr ERRSELR_EL1, xzr 94 mrs x1, ERXCTLR_EL1 95 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 96 msr ERXCTLR_EL1, x1 97 98 /* Restore ERRSELR_EL1 from x2 */ 99 msr ERRSELR_EL1, x2 100workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB 101 102check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0) 103 104workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 105 /* Apply instruction patching sequence */ 106 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 107 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 108 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 109 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 110workaround_reset_end neoverse_n2, ERRATUM(2138953) 111 112check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3) 113 114workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 115 /* Apply instruction patching sequence */ 116 ldr x0,=0x3 117 msr S3_6_c15_c8_0,x0 118 ldr x0,=0xF3A08002 119 msr S3_6_c15_c8_2,x0 120 ldr x0,=0xFFF0F7FE 121 msr S3_6_c15_c8_3,x0 122 ldr x0,=0x10002001003FF 123 msr S3_6_c15_c8_1,x0 124 ldr x0,=0x4 125 msr S3_6_c15_c8_0,x0 126 ldr x0,=0xBF200000 127 msr S3_6_c15_c8_2,x0 128 ldr x0,=0xFFEF0000 129 msr S3_6_c15_c8_3,x0 130 ldr x0,=0x10002001003F3 131 msr S3_6_c15_c8_1,x0 132workaround_reset_end neoverse_n2, ERRATUM(2138956) 133 134check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) 135 136 137workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 138 /* Apply instruction patching sequence */ 139 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 140workaround_reset_end neoverse_n2, ERRATUM(2138958) 141 142check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) 143 144workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 145 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 146workaround_reset_end neoverse_n2, ERRATUM(2189731) 147 148check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) 149 150workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 151 /* Apply instruction patching sequence */ 152 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 153 ldr x0, =0x2 154 msr S3_6_c15_c8_0, x0 155 ldr x0, =0x10F600E000 156 msr S3_6_c15_c8_2, x0 157 ldr x0, =0x10FF80E000 158 msr S3_6_c15_c8_3, x0 159 ldr x0, =0x80000000003FF 160 msr S3_6_c15_c8_1, x0 161workaround_reset_end neoverse_n2, ERRATUM(2242400) 162 163check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) 164 165workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 166 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 167workaround_reset_end neoverse_n2, ERRATUM(2242415) 168 169check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) 170 171workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 172 /* Apply instruction patching sequence */ 173 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 174workaround_reset_end neoverse_n2, ERRATUM(2280757) 175 176check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) 177 178.global erratum_neoverse_n2_2326639_wa 179workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 180 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 181 * the workaround. Second call clears it to undo it. */ 182 sysreg_bit_toggle NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 183workaround_runtime_end neoverse_n2, ERRATUM(2326639) 184 185check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) 186 187workaround_reset_start neoverse_n2, ERRATUM(2340933), ERRATA_N2_2340933 188 /* Set bit 61 in CPUACTLR5_EL1 */ 189 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61) 190workaround_reset_end neoverse_n2, ERRATUM(2340933) 191 192check_erratum_ls neoverse_n2, ERRATUM(2340933), CPU_REV(0, 0) 193 194workaround_reset_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952 195 /* Set TXREQ to STATIC and full L2 TQ size */ 196 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 197 mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL 198 bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH 199 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 200workaround_reset_end neoverse_n2, ERRATUM(2346952) 201 202check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2) 203 204workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 205 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM 206 * ST to behave like PLD/PFRM LD and not cause 207 * invalidations to other PE caches. 208 */ 209 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 210workaround_reset_end neoverse_n2, ERRATUM(2376738) 211 212check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3) 213 214workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 215 /*Set bit 40 in ACTLR2_EL1 */ 216 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 217workaround_reset_end neoverse_n2, ERRATUM(2388450) 218 219check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) 220 221workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014 222 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 223 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 224 sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 225workaround_reset_end neoverse_n2, ERRATUM(2743014) 226 227check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2) 228 229workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 230 /* dsb before isb of power down sequence */ 231 dsb sy 232workaround_runtime_end neoverse_n2, ERRATUM(2743089) 233 234check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) 235 236workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511 237 /* Set bit 47 in ACTLR3_EL1 */ 238 sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 239workaround_reset_end neoverse_n2, ERRATUM(2779511) 240 241check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2) 242 243workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 244#if IMAGE_BL31 245 /* 246 * The Neoverse-N2 generic vectors are overridden to apply errata 247 * mitigation on exception entry from lower ELs. 248 */ 249 override_vector_table wa_cve_vbar_neoverse_n2 250#endif /* IMAGE_BL31 */ 251workaround_reset_end neoverse_n2, CVE(2022,23960) 252 253check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 254 255 /* ------------------------------------------- 256 * The CPU Ops reset function for Neoverse N2. 257 * ------------------------------------------- 258 */ 259cpu_reset_func_start neoverse_n2 260 261 /* Check if the PE implements SSBS */ 262 mrs x0, id_aa64pfr1_el1 263 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 264 b.eq 1f 265 266 /* Disable speculative loads */ 267 msr SSBS, xzr 2681: 269 /* Force all cacheable atomic instructions to be near */ 270 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 271 272#if ENABLE_FEAT_AMU 273 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 274 sysreg_bit_clear cptr_el3, TAM_BIT 275 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 276 sysreg_bit_clear cptr_el2, TAM_BIT 277 /* No need to enable the counters as this would be done at el3 exit */ 278#endif 279 280#if NEOVERSE_Nx_EXTERNAL_LLC 281 /* Some systems may have External LLC, core needs to be made aware */ 282 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 283#endif 284cpu_reset_func_end neoverse_n2 285 286func neoverse_n2_core_pwr_dwn 287 apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478, NO_GET_CPU_REV 288 apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV 289 290 /* --------------------------------------------------- 291 * Enable CPU power down bit in power control register 292 * No need to do cache maintenance here. 293 * --------------------------------------------------- 294 */ 295 sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT 296 297 apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089, NO_GET_CPU_REV 298 299 isb 300 ret 301endfunc neoverse_n2_core_pwr_dwn 302 303 /* --------------------------------------------- 304 * This function provides Neoverse N2 specific 305 * register information for crash reporting. 306 * It needs to return with x6 pointing to 307 * a list of register names in ASCII and 308 * x8 - x15 having values of registers to be 309 * reported. 310 * --------------------------------------------- 311 */ 312.section .rodata.neoverse_n2_regs, "aS" 313neoverse_n2_regs: /* The ASCII list of register names to be reported */ 314 .asciz "cpupwrctlr_el1", "" 315 316func neoverse_n2_cpu_reg_dump 317 adr x6, neoverse_n2_regs 318 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 319 ret 320endfunc neoverse_n2_cpu_reg_dump 321 322declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 323 neoverse_n2_reset_func, \ 324 neoverse_n2_core_pwr_dwn 325