1/* 2 * Copyright (c) 2020-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11#include "wa_cve_2022_23960_bhb_vector.S" 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23#if WORKAROUND_CVE_2022_23960 24 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 25#endif /* WORKAROUND_CVE_2022_23960 */ 26 27/* -------------------------------------------------- 28 * Errata Workaround for Neoverse N2 Erratum 2002655. 29 * This applies to revision r0p0 of Neoverse N2. it is still open. 30 * Inputs: 31 * x0: variant[4:7] and revision[0:3] of current cpu. 32 * Shall clobber: x0-x17 33 * -------------------------------------------------- 34 */ 35func errata_n2_2002655_wa 36 /* Check revision. */ 37 mov x17, x30 38 bl check_errata_2002655 39 cbz x0, 1f 40 41 /* Apply instruction patching sequence */ 42 ldr x0,=0x6 43 msr S3_6_c15_c8_0,x0 44 ldr x0,=0xF3A08002 45 msr S3_6_c15_c8_2,x0 46 ldr x0,=0xFFF0F7FE 47 msr S3_6_c15_c8_3,x0 48 ldr x0,=0x40000001003ff 49 msr S3_6_c15_c8_1,x0 50 ldr x0,=0x7 51 msr S3_6_c15_c8_0,x0 52 ldr x0,=0xBF200000 53 msr S3_6_c15_c8_2,x0 54 ldr x0,=0xFFEF0000 55 msr S3_6_c15_c8_3,x0 56 ldr x0,=0x40000001003f3 57 msr S3_6_c15_c8_1,x0 58 isb 591: 60 ret x17 61endfunc errata_n2_2002655_wa 62 63func check_errata_2002655 64 /* Applies to r0p0 */ 65 mov x1, #0x00 66 b cpu_rev_var_ls 67endfunc check_errata_2002655 68 69/* --------------------------------------------------------------- 70 * Errata Workaround for Neoverse N2 Erratum 2067956. 71 * This applies to revision r0p0 of Neoverse N2 and is still open. 72 * Inputs: 73 * x0: variant[4:7] and revision[0:3] of current cpu. 74 * Shall clobber: x0-x17 75 * --------------------------------------------------------------- 76 */ 77func errata_n2_2067956_wa 78 /* Compare x0 against revision r0p0 */ 79 mov x17, x30 80 bl check_errata_2067956 81 cbz x0, 1f 82 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 83 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 84 msr NEOVERSE_N2_CPUACTLR_EL1, x1 851: 86 ret x17 87endfunc errata_n2_2067956_wa 88 89func check_errata_2067956 90 /* Applies to r0p0 */ 91 mov x1, #0x00 92 b cpu_rev_var_ls 93endfunc check_errata_2067956 94 95/* --------------------------------------------------------------- 96 * Errata Workaround for Neoverse N2 Erratum 2025414. 97 * This applies to revision r0p0 of Neoverse N2 and is still open. 98 * Inputs: 99 * x0: variant[4:7] and revision[0:3] of current cpu. 100 * Shall clobber: x0-x17 101 * --------------------------------------------------------------- 102 */ 103func errata_n2_2025414_wa 104 /* Compare x0 against revision r0p0 */ 105 mov x17, x30 106 bl check_errata_2025414 107 cbz x0, 1f 108 mrs x1, NEOVERSE_N2_CPUECTLR_EL1 109 orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 110 msr NEOVERSE_N2_CPUECTLR_EL1, x1 111 1121: 113 ret x17 114endfunc errata_n2_2025414_wa 115 116func check_errata_2025414 117 /* Applies to r0p0 */ 118 mov x1, #0x00 119 b cpu_rev_var_ls 120endfunc check_errata_2025414 121 122/* --------------------------------------------------------------- 123 * Errata Workaround for Neoverse N2 Erratum 2189731. 124 * This applies to revision r0p0 of Neoverse N2 and is still open. 125 * Inputs: 126 * x0: variant[4:7] and revision[0:3] of current cpu. 127 * Shall clobber: x0-x17 128 * --------------------------------------------------------------- 129 */ 130func errata_n2_2189731_wa 131 /* Compare x0 against revision r0p0 */ 132 mov x17, x30 133 bl check_errata_2189731 134 cbz x0, 1f 135 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 136 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 137 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 138 1391: 140 ret x17 141endfunc errata_n2_2189731_wa 142 143func check_errata_2189731 144 /* Applies to r0p0 */ 145 mov x1, #0x00 146 b cpu_rev_var_ls 147endfunc check_errata_2189731 148 149/* -------------------------------------------------- 150 * Errata Workaround for Neoverse N2 Erratum 2138956. 151 * This applies to revision r0p0 of Neoverse N2. it is still open. 152 * Inputs: 153 * x0: variant[4:7] and revision[0:3] of current cpu. 154 * Shall clobber: x0-x17 155 * -------------------------------------------------- 156 */ 157func errata_n2_2138956_wa 158 /* Check revision. */ 159 mov x17, x30 160 bl check_errata_2138956 161 cbz x0, 1f 162 163 /* Apply instruction patching sequence */ 164 ldr x0,=0x3 165 msr S3_6_c15_c8_0,x0 166 ldr x0,=0xF3A08002 167 msr S3_6_c15_c8_2,x0 168 ldr x0,=0xFFF0F7FE 169 msr S3_6_c15_c8_3,x0 170 ldr x0,=0x10002001003FF 171 msr S3_6_c15_c8_1,x0 172 ldr x0,=0x4 173 msr S3_6_c15_c8_0,x0 174 ldr x0,=0xBF200000 175 msr S3_6_c15_c8_2,x0 176 ldr x0,=0xFFEF0000 177 msr S3_6_c15_c8_3,x0 178 ldr x0,=0x10002001003F3 179 msr S3_6_c15_c8_1,x0 180 isb 1811: 182 ret x17 183endfunc errata_n2_2138956_wa 184 185func check_errata_2138956 186 /* Applies to r0p0 */ 187 mov x1, #0x00 188 b cpu_rev_var_ls 189endfunc check_errata_2138956 190 191/* -------------------------------------------------- 192 * Errata Workaround for Neoverse N2 Erratum 2242415. 193 * This applies to revision r0p0 of Neoverse N2. it is still open. 194 * Inputs: 195 * x0: variant[4:7] and revision[0:3] of current cpu. 196 * Shall clobber: x0-x1, x17 197 * -------------------------------------------------- 198 */ 199func errata_n2_2242415_wa 200 /* Check revision. */ 201 mov x17, x30 202 bl check_errata_2242415 203 cbz x0, 1f 204 205 /* Apply instruction patching sequence */ 206 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 207 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 208 msr NEOVERSE_N2_CPUACTLR_EL1, x1 2091: 210 ret x17 211endfunc errata_n2_2242415_wa 212 213func check_errata_2242415 214 /* Applies to r0p0 */ 215 mov x1, #0x00 216 b cpu_rev_var_ls 217endfunc check_errata_2242415 218 219/* -------------------------------------------------- 220 * Errata Workaround for Neoverse N2 Erratum 2138953. 221 * This applies to revision r0p0 of Neoverse N2. it is still open. 222 * Inputs: 223 * x0: variant[4:7] and revision[0:3] of current cpu. 224 * Shall clobber: x0-x1, x17 225 * -------------------------------------------------- 226 */ 227func errata_n2_2138953_wa 228 /* Check revision. */ 229 mov x17, x30 230 bl check_errata_2138953 231 cbz x0, 1f 232 233 /* Apply instruction patching sequence */ 234 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 235 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 236 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 237 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 2381: 239 ret x17 240endfunc errata_n2_2138953_wa 241 242func check_errata_2138953 243 /* Applies to r0p0 */ 244 mov x1, #0x00 245 b cpu_rev_var_ls 246endfunc check_errata_2138953 247 248/* -------------------------------------------------- 249 * Errata Workaround for Neoverse N2 Erratum 2138958. 250 * This applies to revision r0p0 of Neoverse N2. it is still open. 251 * Inputs: 252 * x0: variant[4:7] and revision[0:3] of current cpu. 253 * Shall clobber: x0-x1, x17 254 * -------------------------------------------------- 255 */ 256func errata_n2_2138958_wa 257 /* Check revision. */ 258 mov x17, x30 259 bl check_errata_2138958 260 cbz x0, 1f 261 262 /* Apply instruction patching sequence */ 263 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 264 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 265 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 2661: 267 ret x17 268endfunc errata_n2_2138958_wa 269 270func check_errata_2138958 271 /* Applies to r0p0 */ 272 mov x1, #0x00 273 b cpu_rev_var_ls 274endfunc check_errata_2138958 275 276/* -------------------------------------------------- 277 * Errata Workaround for Neoverse N2 Erratum 2242400. 278 * This applies to revision r0p0 of Neoverse N2. it is still open. 279 * Inputs: 280 * x0: variant[4:7] and revision[0:3] of current cpu. 281 * Shall clobber: x0-x1, x17 282 * -------------------------------------------------- 283 */ 284func errata_n2_2242400_wa 285 /* Check revision. */ 286 mov x17, x30 287 bl check_errata_2242400 288 cbz x0, 1f 289 290 /* Apply instruction patching sequence */ 291 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 292 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 293 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 294 ldr x0, =0x2 295 msr S3_6_c15_c8_0, x0 296 ldr x0, =0x10F600E000 297 msr S3_6_c15_c8_2, x0 298 ldr x0, =0x10FF80E000 299 msr S3_6_c15_c8_3, x0 300 ldr x0, =0x80000000003FF 301 msr S3_6_c15_c8_1, x0 302 isb 3031: 304 ret x17 305endfunc errata_n2_2242400_wa 306 307func check_errata_2242400 308 /* Applies to r0p0 */ 309 mov x1, #0x00 310 b cpu_rev_var_ls 311endfunc check_errata_2242400 312 313/* -------------------------------------------------- 314 * Errata Workaround for Neoverse N2 Erratum 2280757. 315 * This applies to revision r0p0 of Neoverse N2. it is still open. 316 * Inputs: 317 * x0: variant[4:7] and revision[0:3] of current cpu. 318 * Shall clobber: x0-x1, x17 319 * -------------------------------------------------- 320 */ 321func errata_n2_2280757_wa 322 /* Check revision. */ 323 mov x17, x30 324 bl check_errata_2280757 325 cbz x0, 1f 326 327 /* Apply instruction patching sequence */ 328 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 329 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 330 msr NEOVERSE_N2_CPUACTLR_EL1, x1 3311: 332 ret x17 333endfunc errata_n2_2280757_wa 334 335func check_errata_2280757 336 /* Applies to r0p0 */ 337 mov x1, #0x00 338 b cpu_rev_var_ls 339endfunc check_errata_2280757 340 341func check_errata_cve_2022_23960 342#if WORKAROUND_CVE_2022_23960 343 mov x0, #ERRATA_APPLIES 344#else 345 mov x0, #ERRATA_MISSING 346#endif 347 ret 348endfunc check_errata_cve_2022_23960 349 350 /* ------------------------------------------- 351 * The CPU Ops reset function for Neoverse N2. 352 * ------------------------------------------- 353 */ 354func neoverse_n2_reset_func 355 mov x19, x30 356 357 /* Check if the PE implements SSBS */ 358 mrs x0, id_aa64pfr1_el1 359 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 360 b.eq 1f 361 362 /* Disable speculative loads */ 363 msr SSBS, xzr 3641: 365 /* Force all cacheable atomic instructions to be near */ 366 mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 367 orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 368 msr NEOVERSE_N2_CPUACTLR2_EL1, x0 369 370#if ERRATA_N2_2067956 371 mov x0, x18 372 bl errata_n2_2067956_wa 373#endif 374 375#if ERRATA_N2_2025414 376 mov x0, x18 377 bl errata_n2_2025414_wa 378#endif 379 380#if ERRATA_N2_2189731 381 mov x0, x18 382 bl errata_n2_2189731_wa 383#endif 384 385 386#if ERRATA_N2_2138956 387 mov x0, x18 388 bl errata_n2_2138956_wa 389#endif 390 391#if ERRATA_N2_2138953 392 mov x0, x18 393 bl errata_n2_2138953_wa 394#endif 395 396#if ERRATA_N2_2242415 397 mov x0, x18 398 bl errata_n2_2242415_wa 399#endif 400 401#if ERRATA_N2_2138958 402 mov x0, x18 403 bl errata_n2_2138958_wa 404#endif 405 406#if ERRATA_N2_2242400 407 mov x0, x18 408 bl errata_n2_2242400_wa 409#endif 410 411#if ERRATA_N2_2280757 412 mov x0, x18 413 bl errata_n2_2280757_wa 414#endif 415 416#if ENABLE_AMU 417 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 418 mrs x0, cptr_el3 419 orr x0, x0, #TAM_BIT 420 msr cptr_el3, x0 421 422 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 423 mrs x0, cptr_el2 424 orr x0, x0, #TAM_BIT 425 msr cptr_el2, x0 426 427 /* No need to enable the counters as this would be done at el3 exit */ 428#endif 429 430#if NEOVERSE_Nx_EXTERNAL_LLC 431 /* Some systems may have External LLC, core needs to be made aware */ 432 mrs x0, NEOVERSE_N2_CPUECTLR_EL1 433 orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 434 msr NEOVERSE_N2_CPUECTLR_EL1, x0 435#endif 436 437 bl cpu_get_rev_var 438 mov x18, x0 439 440#if ERRATA_N2_2002655 441 mov x0, x18 442 bl errata_n2_2002655_wa 443#endif 444 445#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 446 /* 447 * The Neoverse-N2 generic vectors are overridden to apply errata 448 * mitigation on exception entry from lower ELs. 449 */ 450 adr x0, wa_cve_vbar_neoverse_n2 451 msr vbar_el3, x0 452#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 453 454 isb 455 ret x19 456endfunc neoverse_n2_reset_func 457 458func neoverse_n2_core_pwr_dwn 459 /* --------------------------------------------------- 460 * Enable CPU power down bit in power control register 461 * No need to do cache maintenance here. 462 * --------------------------------------------------- 463 */ 464 mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 465 orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT 466 msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 467 isb 468 ret 469endfunc neoverse_n2_core_pwr_dwn 470 471#if REPORT_ERRATA 472/* 473 * Errata printing function for Neoverse N2 cores. Must follow AAPCS. 474 */ 475func neoverse_n2_errata_report 476 stp x8, x30, [sp, #-16]! 477 478 bl cpu_get_rev_var 479 mov x8, x0 480 481 /* 482 * Report all errata. The revision-variant information is passed to 483 * checking functions of each errata. 484 */ 485 report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 486 report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 487 report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 488 report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 489 report_errata ERRATA_N2_2138956, neoverse_n2, 2138956 490 report_errata ERRATA_N2_2138953, neoverse_n2, 2138953 491 report_errata ERRATA_N2_2242415, neoverse_n2, 2242415 492 report_errata ERRATA_N2_2138958, neoverse_n2, 2138958 493 report_errata ERRATA_N2_2242400, neoverse_n2, 2242400 494 report_errata ERRATA_N2_2280757, neoverse_n2, 2280757 495 report_errata WORKAROUND_CVE_2022_23960, neoverse_n2, cve_2022_23960 496 497 ldp x8, x30, [sp], #16 498 ret 499endfunc neoverse_n2_errata_report 500#endif 501 502 /* --------------------------------------------- 503 * This function provides Neoverse N2 specific 504 * register information for crash reporting. 505 * It needs to return with x6 pointing to 506 * a list of register names in ASCII and 507 * x8 - x15 having values of registers to be 508 * reported. 509 * --------------------------------------------- 510 */ 511.section .rodata.neoverse_n2_regs, "aS" 512neoverse_n2_regs: /* The ASCII list of register names to be reported */ 513 .asciz "cpupwrctlr_el1", "" 514 515func neoverse_n2_cpu_reg_dump 516 adr x6, neoverse_n2_regs 517 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 518 ret 519endfunc neoverse_n2_cpu_reg_dump 520 521declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 522 neoverse_n2_reset_func, \ 523 neoverse_n2_core_pwr_dwn 524