1/* 2 * Copyright (c) 2020-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <dsu_macros.S> 11#include <neoverse_n2.h> 12#include "wa_cve_2022_23960_bhb_vector.S" 13#include <wa_cve_2025_0647_cpprctx.h> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_neoverse_n2_3701773 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31cpu_reset_prologue neoverse_n2 32 33workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 34 /* Apply instruction patching sequence */ 35 ldr x0,=0x6 36 msr S3_6_c15_c8_0,x0 37 ldr x0,=0xF3A08002 38 msr S3_6_c15_c8_2,x0 39 ldr x0,=0xFFF0F7FE 40 msr S3_6_c15_c8_3,x0 41 ldr x0,=0x40000001003ff 42 msr S3_6_c15_c8_1,x0 43 ldr x0,=0x7 44 msr S3_6_c15_c8_0,x0 45 ldr x0,=0xBF200000 46 msr S3_6_c15_c8_2,x0 47 ldr x0,=0xFFEF0000 48 msr S3_6_c15_c8_3,x0 49 ldr x0,=0x40000001003f3 50 msr S3_6_c15_c8_1,x0 51workaround_reset_end neoverse_n2, ERRATUM(2002655) 52 53check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) 54 55workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 56 /* Stash ERRSELR_EL1 in x2 */ 57 mrs x2, ERRSELR_EL1 58 59 /* Select error record 0 and clear ED bit */ 60 msr ERRSELR_EL1, xzr 61 mrs x1, ERXCTLR_EL1 62 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 63 msr ERXCTLR_EL1, x1 64 65 /* Restore ERRSELR_EL1 from x2 */ 66 msr ERRSELR_EL1, x2 67workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB 68 69check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0) 70 71workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 72 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 73workaround_reset_end neoverse_n2, ERRATUM(2025414) 74 75check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) 76 77workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 78 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 79workaround_reset_end neoverse_n2, ERRATUM(2067956) 80 81check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) 82 83workaround_runtime_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 84 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, BIT(29) 85workaround_runtime_end neoverse_n2, ERRATUM(2138953) 86 87check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3) 88 89workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 90 /* Apply instruction patching sequence */ 91 ldr x0,=0x3 92 msr S3_6_c15_c8_0,x0 93 ldr x0,=0xF3A08002 94 msr S3_6_c15_c8_2,x0 95 ldr x0,=0xFFF0F7FE 96 msr S3_6_c15_c8_3,x0 97 ldr x0,=0x10002001003FF 98 msr S3_6_c15_c8_1,x0 99 ldr x0,=0x4 100 msr S3_6_c15_c8_0,x0 101 ldr x0,=0xBF200000 102 msr S3_6_c15_c8_2,x0 103 ldr x0,=0xFFEF0000 104 msr S3_6_c15_c8_3,x0 105 ldr x0,=0x10002001003F3 106 msr S3_6_c15_c8_1,x0 107workaround_reset_end neoverse_n2, ERRATUM(2138956) 108 109check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) 110 111workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 112 /* Apply instruction patching sequence */ 113 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 114workaround_reset_end neoverse_n2, ERRATUM(2138958) 115 116check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) 117 118workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 119 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 120workaround_reset_end neoverse_n2, ERRATUM(2189731) 121 122check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) 123 124workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 125 /* Apply instruction patching sequence */ 126 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 127 ldr x0, =0x2 128 msr S3_6_c15_c8_0, x0 129 ldr x0, =0x10F600E000 130 msr S3_6_c15_c8_2, x0 131 ldr x0, =0x10FF80E000 132 msr S3_6_c15_c8_3, x0 133 ldr x0, =0x80000000003FF 134 msr S3_6_c15_c8_1, x0 135workaround_reset_end neoverse_n2, ERRATUM(2242400) 136 137check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) 138 139workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 140 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 141workaround_reset_end neoverse_n2, ERRATUM(2242415) 142 143check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) 144 145workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 146 /* Apply instruction patching sequence */ 147 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 148workaround_reset_end neoverse_n2, ERRATUM(2280757) 149 150check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) 151 152workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941 153 errata_dsu_2313941_wa_impl 154workaround_reset_end neoverse_n2, ERRATUM(2313941) 155 156check_erratum_custom_start neoverse_n2, ERRATUM(2313941) 157 branch_if_scu_not_present 2f /* label 1 is used in the macro */ 158 check_errata_dsu_2313941_impl 159 2: 160 ret 161check_erratum_custom_end neoverse_n2, ERRATUM(2313941) 162 163.global erratum_neoverse_n2_2326639_wa 164workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 165 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 166 * the workaround. Second call clears it to undo it. */ 167 sysreg_bit_toggle NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 168workaround_runtime_end neoverse_n2, ERRATUM(2326639) 169 170check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) 171 172workaround_reset_start neoverse_n2, ERRATUM(2340933), ERRATA_N2_2340933 173 /* Set bit 61 in CPUACTLR5_EL1 */ 174 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61) 175workaround_reset_end neoverse_n2, ERRATUM(2340933) 176 177check_erratum_ls neoverse_n2, ERRATUM(2340933), CPU_REV(0, 0) 178 179workaround_reset_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952 180 /* Set TXREQ to STATIC and full L2 TQ size */ 181 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 182 mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL 183 bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH 184 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 185workaround_reset_end neoverse_n2, ERRATUM(2346952) 186 187check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2) 188 189workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 190 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM 191 * ST to behave like PLD/PFRM LD and not cause 192 * invalidations to other PE caches. 193 */ 194 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 195workaround_reset_end neoverse_n2, ERRATUM(2376738) 196 197check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3) 198 199workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 200 /*Set bit 40 in ACTLR2_EL1 */ 201 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 202workaround_reset_end neoverse_n2, ERRATUM(2388450) 203 204check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) 205 206workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014 207 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 208 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 209 sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 210workaround_reset_end neoverse_n2, ERRATUM(2743014) 211 212check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2) 213 214workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 215 /* dsb before isb of power down sequence */ 216 dsb sy 217workaround_runtime_end neoverse_n2, ERRATUM(2743089) 218 219check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) 220 221workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511 222 /* Set bit 47 in ACTLR3_EL1 */ 223 sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 224workaround_reset_end neoverse_n2, ERRATUM(2779511) 225 226check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2) 227 228workaround_runtime_start neoverse_n2, ERRATUM(3324339), ERRATA_N2_3324339 229 speculation_barrier 230workaround_runtime_end neoverse_n2, ERRATUM(3324339) 231 232check_erratum_ls neoverse_n2, ERRATUM(3324339), CPU_REV(0, 3) 233 234add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773 235 236check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3) 237 238workaround_reset_start neoverse_n2, ERRATUM(3888123), ERRATA_N2_3888123 239 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, BIT(22) 240workaround_reset_end neoverse_n2, ERRATUM(3888123) 241 242check_erratum_ls neoverse_n2, ERRATUM(3888123), CPU_REV(0, 3) 243 244workaround_reset_start neoverse_n2, ERRATUM(4302970), ERRATA_N2_4302970 245 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(50) 246workaround_reset_end neoverse_n2, ERRATUM(4302970) 247 248check_erratum_ls neoverse_n2, ERRATUM(4302970), CPU_REV(0, 3) 249 250workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 251#if IMAGE_BL31 252 /* 253 * The Neoverse-N2 generic vectors are overridden to apply errata 254 * mitigation on exception entry from lower ELs. 255 */ 256 override_vector_table wa_cve_vbar_neoverse_n2 257#endif /* IMAGE_BL31 */ 258workaround_reset_end neoverse_n2, CVE(2022,23960) 259 260check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 261 262/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 263workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 264 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46) 265workaround_reset_end neoverse_n2, CVE(2024, 5660) 266 267check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3) 268 269 /* 270 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 271 * Enables mitigation for CVE-2025-0647. 272 */ 273workaround_reset_start neoverse_n2, CVE(2025, 647), WORKAROUND_CVE_2025_0647 274 mov x0, #(WA_USE_T32_OPCODE | WA_PATCH_SLOT(0)) 275 bl wa_cve_2025_0647_instruction_patch 276workaround_reset_end neoverse_n2, CVE(2025, 647) 277 278check_erratum_chosen neoverse_n2, CVE(2025, 647), WORKAROUND_CVE_2025_0647 279 280#if WORKAROUND_CVE_2025_0647 281func neoverse_n2_impl_defined_el3_handler 282 mov x0, #WA_LS_RCG_EN 283 284 /* See if this call came from trap handler. */ 285 cmp x1, #EC_IMP_DEF_EL3 286 bne wa_cve_2025_0647_do_cpp_wa 287 orr x0, x0, #WA_IS_TRAP_HANDLER 288 b wa_cve_2025_0647_do_cpp_wa 289endfunc neoverse_n2_impl_defined_el3_handler 290#endif 291 292 /* ------------------------------------------- 293 * The CPU Ops reset function for Neoverse N2. 294 * ------------------------------------------- 295 */ 296cpu_reset_func_start neoverse_n2 297 298 /* Check if the PE implements SSBS */ 299 mrs x0, id_aa64pfr1_el1 300 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 301 b.eq 1f 302 303 /* Disable speculative loads */ 304 msr SSBS, xzr 305 apply_erratum neoverse_n2, ERRATUM(3324339), ERRATA_N2_3324339 306 3071: 308 /* Force all cacheable atomic instructions to be near */ 309 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 310 311#if ENABLE_FEAT_AMU 312 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 313 sysreg_bit_clear cptr_el3, TAM_BIT 314 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 315 sysreg_bit_clear cptr_el2, TAM_BIT 316 /* No need to enable the counters as this would be done at el3 exit */ 317#endif 318 319#if NEOVERSE_Nx_EXTERNAL_LLC 320 /* Some systems may have External LLC, core needs to be made aware */ 321 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 322#endif 323#if NEOVERSE_N2_PREFETCHER_DISABLE 324 /* Disable region prefetcher for L2 cache perf measurement */ 325 apply_erratum neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 326 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFDIS_BIT 327#endif 328cpu_reset_func_end neoverse_n2 329 330func neoverse_n2_core_pwr_dwn 331 apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 332 apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV 333 334 /* --------------------------------------------------- 335 * Enable CPU power down bit in power control register 336 * No need to do cache maintenance here. 337 * --------------------------------------------------- 338 */ 339 sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT 340 341 apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089, NO_GET_CPU_REV 342 343 isb 344 ret 345endfunc neoverse_n2_core_pwr_dwn 346 347 /* --------------------------------------------- 348 * This function provides Neoverse N2 specific 349 * register information for crash reporting. 350 * It needs to return with x6 pointing to 351 * a list of register names in ASCII and 352 * x8 - x15 having values of registers to be 353 * reported. 354 * --------------------------------------------- 355 */ 356.section .rodata.neoverse_n2_regs, "aS" 357neoverse_n2_regs: /* The ASCII list of register names to be reported */ 358 .asciz "cpupwrctlr_el1", "" 359 360func neoverse_n2_cpu_reg_dump 361 adr x6, neoverse_n2_regs 362 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 363 ret 364endfunc neoverse_n2_cpu_reg_dump 365 366#if WORKAROUND_CVE_2025_0647 367declare_cpu_ops_eh neoverse_n2, NEOVERSE_N2_MIDR, \ 368 neoverse_n2_reset_func, \ 369 neoverse_n2_impl_defined_el3_handler, \ 370 neoverse_n2_core_pwr_dwn 371#else 372declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 373 neoverse_n2_reset_func, \ 374 neoverse_n2_core_pwr_dwn 375#endif 376