1/* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11#include "wa_cve_2022_23960_bhb_vector.S" 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23.global check_erratum_neoverse_n2_3701773 24 25add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773, NO_APPLY_AT_RESET 26 27check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3) 28 29#if WORKAROUND_CVE_2022_23960 30 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 31#endif /* WORKAROUND_CVE_2022_23960 */ 32 33/* 34 * ERRATA_DSU_2313941: 35 * The errata is defined in dsu_helpers.S and applies to Neoverse N2. 36 * Henceforth creating symbolic names to the already existing errata 37 * workaround functions to get them registered under the Errata Framework. 38 */ 39.equ check_erratum_neoverse_n2_2313941, check_errata_dsu_2313941 40.equ erratum_neoverse_n2_2313941_wa, errata_dsu_2313941_wa 41add_erratum_entry neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 42 43/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 44workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 45 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46) 46workaround_reset_end neoverse_n2, CVE(2024, 5660) 47 48check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3) 49 50workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 51 /* Apply instruction patching sequence */ 52 ldr x0,=0x6 53 msr S3_6_c15_c8_0,x0 54 ldr x0,=0xF3A08002 55 msr S3_6_c15_c8_2,x0 56 ldr x0,=0xFFF0F7FE 57 msr S3_6_c15_c8_3,x0 58 ldr x0,=0x40000001003ff 59 msr S3_6_c15_c8_1,x0 60 ldr x0,=0x7 61 msr S3_6_c15_c8_0,x0 62 ldr x0,=0xBF200000 63 msr S3_6_c15_c8_2,x0 64 ldr x0,=0xFFEF0000 65 msr S3_6_c15_c8_3,x0 66 ldr x0,=0x40000001003f3 67 msr S3_6_c15_c8_1,x0 68workaround_reset_end neoverse_n2, ERRATUM(2002655) 69 70check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) 71 72workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 73 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 74workaround_reset_end neoverse_n2, ERRATUM(2025414) 75 76check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) 77 78workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 79 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 80workaround_reset_end neoverse_n2, ERRATUM(2067956) 81 82check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) 83 84workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 85 /* Stash ERRSELR_EL1 in x2 */ 86 mrs x2, ERRSELR_EL1 87 88 /* Select error record 0 and clear ED bit */ 89 msr ERRSELR_EL1, xzr 90 mrs x1, ERXCTLR_EL1 91 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 92 msr ERXCTLR_EL1, x1 93 94 /* Restore ERRSELR_EL1 from x2 */ 95 msr ERRSELR_EL1, x2 96workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB 97 98check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0) 99 100workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 101 /* Apply instruction patching sequence */ 102 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 103 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 104 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 105 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 106workaround_reset_end neoverse_n2, ERRATUM(2138953) 107 108check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3) 109 110workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 111 /* Apply instruction patching sequence */ 112 ldr x0,=0x3 113 msr S3_6_c15_c8_0,x0 114 ldr x0,=0xF3A08002 115 msr S3_6_c15_c8_2,x0 116 ldr x0,=0xFFF0F7FE 117 msr S3_6_c15_c8_3,x0 118 ldr x0,=0x10002001003FF 119 msr S3_6_c15_c8_1,x0 120 ldr x0,=0x4 121 msr S3_6_c15_c8_0,x0 122 ldr x0,=0xBF200000 123 msr S3_6_c15_c8_2,x0 124 ldr x0,=0xFFEF0000 125 msr S3_6_c15_c8_3,x0 126 ldr x0,=0x10002001003F3 127 msr S3_6_c15_c8_1,x0 128workaround_reset_end neoverse_n2, ERRATUM(2138956) 129 130check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) 131 132 133workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 134 /* Apply instruction patching sequence */ 135 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 136workaround_reset_end neoverse_n2, ERRATUM(2138958) 137 138check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) 139 140workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 141 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 142workaround_reset_end neoverse_n2, ERRATUM(2189731) 143 144check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) 145 146workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 147 /* Apply instruction patching sequence */ 148 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 149 ldr x0, =0x2 150 msr S3_6_c15_c8_0, x0 151 ldr x0, =0x10F600E000 152 msr S3_6_c15_c8_2, x0 153 ldr x0, =0x10FF80E000 154 msr S3_6_c15_c8_3, x0 155 ldr x0, =0x80000000003FF 156 msr S3_6_c15_c8_1, x0 157workaround_reset_end neoverse_n2, ERRATUM(2242400) 158 159check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) 160 161workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 162 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 163workaround_reset_end neoverse_n2, ERRATUM(2242415) 164 165check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) 166 167workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 168 /* Apply instruction patching sequence */ 169 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 170workaround_reset_end neoverse_n2, ERRATUM(2280757) 171 172check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) 173 174workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 175 /* Set bit 36 in ACTLR2_EL1 */ 176 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 177workaround_runtime_end neoverse_n2, ERRATUM(2326639) 178 179check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) 180 181workaround_runtime_start neoverse_n2, ERRATUM(2340933), ERRATA_N2_2340933 182 /* Set bit 61 in CPUACTLR5_EL1 */ 183 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61) 184workaround_runtime_end neoverse_n2, ERRATUM(2340933) 185 186check_erratum_ls neoverse_n2, ERRATUM(2340933), CPU_REV(0, 0) 187 188workaround_runtime_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952 189 /* Set TXREQ to STATIC and full L2 TQ size */ 190 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 191 mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL 192 bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH 193 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 194workaround_runtime_end neoverse_n2, ERRATUM(2346952) 195 196check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2) 197 198workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 199 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM 200 * ST to behave like PLD/PFRM LD and not cause 201 * invalidations to other PE caches. 202 */ 203 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 204workaround_reset_end neoverse_n2, ERRATUM(2376738) 205 206check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3) 207 208workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 209 /*Set bit 40 in ACTLR2_EL1 */ 210 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 211workaround_reset_end neoverse_n2, ERRATUM(2388450) 212 213check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) 214 215workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014 216 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 217 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 218 sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 219workaround_reset_end neoverse_n2, ERRATUM(2743014) 220 221check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2) 222 223workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 224 /* dsb before isb of power down sequence */ 225 dsb sy 226workaround_runtime_end neoverse_n2, ERRATUM(2743089) 227 228check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) 229 230workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511 231 /* Set bit 47 in ACTLR3_EL1 */ 232 sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 233workaround_reset_end neoverse_n2, ERRATUM(2779511) 234 235check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2) 236 237workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 238#if IMAGE_BL31 239 /* 240 * The Neoverse-N2 generic vectors are overridden to apply errata 241 * mitigation on exception entry from lower ELs. 242 */ 243 override_vector_table wa_cve_vbar_neoverse_n2 244#endif /* IMAGE_BL31 */ 245workaround_reset_end neoverse_n2, CVE(2022,23960) 246 247check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 248 249 /* ------------------------------------------- 250 * The CPU Ops reset function for Neoverse N2. 251 * ------------------------------------------- 252 */ 253cpu_reset_func_start neoverse_n2 254 255 /* Check if the PE implements SSBS */ 256 mrs x0, id_aa64pfr1_el1 257 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 258 b.eq 1f 259 260 /* Disable speculative loads */ 261 msr SSBS, xzr 2621: 263 /* Force all cacheable atomic instructions to be near */ 264 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 265 266#if ENABLE_FEAT_AMU 267 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 268 sysreg_bit_clear cptr_el3, TAM_BIT 269 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 270 sysreg_bit_clear cptr_el2, TAM_BIT 271 /* No need to enable the counters as this would be done at el3 exit */ 272#endif 273 274#if NEOVERSE_Nx_EXTERNAL_LLC 275 /* Some systems may have External LLC, core needs to be made aware */ 276 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 277#endif 278cpu_reset_func_end neoverse_n2 279 280func neoverse_n2_core_pwr_dwn 281 apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478, NO_GET_CPU_REV 282 apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV 283 284 /* --------------------------------------------------- 285 * Enable CPU power down bit in power control register 286 * No need to do cache maintenance here. 287 * --------------------------------------------------- 288 */ 289 sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT 290 291 apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089, NO_GET_CPU_REV 292 293 isb 294 ret 295endfunc neoverse_n2_core_pwr_dwn 296 297 /* --------------------------------------------- 298 * This function provides Neoverse N2 specific 299 * register information for crash reporting. 300 * It needs to return with x6 pointing to 301 * a list of register names in ASCII and 302 * x8 - x15 having values of registers to be 303 * reported. 304 * --------------------------------------------- 305 */ 306.section .rodata.neoverse_n2_regs, "aS" 307neoverse_n2_regs: /* The ASCII list of register names to be reported */ 308 .asciz "cpupwrctlr_el1", "" 309 310func neoverse_n2_cpu_reg_dump 311 adr x6, neoverse_n2_regs 312 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 313 ret 314endfunc neoverse_n2_cpu_reg_dump 315 316declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 317 neoverse_n2_reset_func, \ 318 neoverse_n2_core_pwr_dwn 319