1*25bbbd2dSJavier Almansa Sobrino/* 2*25bbbd2dSJavier Almansa Sobrino * Copyright (c) 2020, Arm Limited. All rights reserved. 3*25bbbd2dSJavier Almansa Sobrino * 4*25bbbd2dSJavier Almansa Sobrino * SPDX-License-Identifier: BSD-3-Clause 5*25bbbd2dSJavier Almansa Sobrino */ 6*25bbbd2dSJavier Almansa Sobrino 7*25bbbd2dSJavier Almansa Sobrino#include <arch.h> 8*25bbbd2dSJavier Almansa Sobrino#include <asm_macros.S> 9*25bbbd2dSJavier Almansa Sobrino#include <cpu_macros.S> 10*25bbbd2dSJavier Almansa Sobrino#include <neoverse_n2.h> 11*25bbbd2dSJavier Almansa Sobrino 12*25bbbd2dSJavier Almansa Sobrino/* Hardware handled coherency */ 13*25bbbd2dSJavier Almansa Sobrino#if HW_ASSISTED_COHERENCY == 0 14*25bbbd2dSJavier Almansa Sobrino#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 15*25bbbd2dSJavier Almansa Sobrino#endif 16*25bbbd2dSJavier Almansa Sobrino 17*25bbbd2dSJavier Almansa Sobrino/* 64-bit only core */ 18*25bbbd2dSJavier Almansa Sobrino#if CTX_INCLUDE_AARCH32_REGS == 1 19*25bbbd2dSJavier Almansa Sobrino#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 20*25bbbd2dSJavier Almansa Sobrino#endif 21*25bbbd2dSJavier Almansa Sobrino 22*25bbbd2dSJavier Almansa Sobrino /* ------------------------------------------------- 23*25bbbd2dSJavier Almansa Sobrino * The CPU Ops reset function for Neoverse N2. 24*25bbbd2dSJavier Almansa Sobrino * ------------------------------------------------- 25*25bbbd2dSJavier Almansa Sobrino */ 26*25bbbd2dSJavier Almansa Sobrinofunc neoverse_n2_reset_func 27*25bbbd2dSJavier Almansa Sobrino /* Check if the PE implements SSBS */ 28*25bbbd2dSJavier Almansa Sobrino mrs x0, id_aa64pfr1_el1 29*25bbbd2dSJavier Almansa Sobrino tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 30*25bbbd2dSJavier Almansa Sobrino b.eq 1f 31*25bbbd2dSJavier Almansa Sobrino 32*25bbbd2dSJavier Almansa Sobrino /* Disable speculative loads */ 33*25bbbd2dSJavier Almansa Sobrino msr SSBS, xzr 34*25bbbd2dSJavier Almansa Sobrino1: 35*25bbbd2dSJavier Almansa Sobrino /* Force all cacheable atomic instructions to be near */ 36*25bbbd2dSJavier Almansa Sobrino mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 37*25bbbd2dSJavier Almansa Sobrino orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 38*25bbbd2dSJavier Almansa Sobrino msr NEOVERSE_N2_CPUACTLR2_EL1, x0 39*25bbbd2dSJavier Almansa Sobrino 40*25bbbd2dSJavier Almansa Sobrino#if ENABLE_AMU 41*25bbbd2dSJavier Almansa Sobrino /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 42*25bbbd2dSJavier Almansa Sobrino mrs x0, cptr_el3 43*25bbbd2dSJavier Almansa Sobrino orr x0, x0, #TAM_BIT 44*25bbbd2dSJavier Almansa Sobrino msr cptr_el3, x0 45*25bbbd2dSJavier Almansa Sobrino 46*25bbbd2dSJavier Almansa Sobrino /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 47*25bbbd2dSJavier Almansa Sobrino mrs x0, cptr_el2 48*25bbbd2dSJavier Almansa Sobrino orr x0, x0, #TAM_BIT 49*25bbbd2dSJavier Almansa Sobrino msr cptr_el2, x0 50*25bbbd2dSJavier Almansa Sobrino 51*25bbbd2dSJavier Almansa Sobrino /* No need to enable the counters as this would be done at el3 exit */ 52*25bbbd2dSJavier Almansa Sobrino#endif 53*25bbbd2dSJavier Almansa Sobrino 54*25bbbd2dSJavier Almansa Sobrino#if NEOVERSE_Nx_EXTERNAL_LLC 55*25bbbd2dSJavier Almansa Sobrino /* Some systems may have External LLC, core needs to be made aware */ 56*25bbbd2dSJavier Almansa Sobrino mrs x0, NEOVERSE_N2_CPUECTLR_EL1 57*25bbbd2dSJavier Almansa Sobrino orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 58*25bbbd2dSJavier Almansa Sobrino msr NEOVERSE_N2_CPUECTLR_EL1, x0 59*25bbbd2dSJavier Almansa Sobrino#endif 60*25bbbd2dSJavier Almansa Sobrino 61*25bbbd2dSJavier Almansa Sobrino isb 62*25bbbd2dSJavier Almansa Sobrino ret 63*25bbbd2dSJavier Almansa Sobrinoendfunc neoverse_n2_reset_func 64*25bbbd2dSJavier Almansa Sobrino 65*25bbbd2dSJavier Almansa Sobrinofunc neoverse_n2_core_pwr_dwn 66*25bbbd2dSJavier Almansa Sobrino /* --------------------------------------------- 67*25bbbd2dSJavier Almansa Sobrino * Enable CPU power down bit in power control register 68*25bbbd2dSJavier Almansa Sobrino * No need to do cache maintenance here. 69*25bbbd2dSJavier Almansa Sobrino * --------------------------------------------- 70*25bbbd2dSJavier Almansa Sobrino */ 71*25bbbd2dSJavier Almansa Sobrino mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 72*25bbbd2dSJavier Almansa Sobrino orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT 73*25bbbd2dSJavier Almansa Sobrino msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 74*25bbbd2dSJavier Almansa Sobrino isb 75*25bbbd2dSJavier Almansa Sobrino ret 76*25bbbd2dSJavier Almansa Sobrinoendfunc neoverse_n2_core_pwr_dwn 77*25bbbd2dSJavier Almansa Sobrino 78*25bbbd2dSJavier Almansa Sobrino#if REPORT_ERRATA 79*25bbbd2dSJavier Almansa Sobrino/* 80*25bbbd2dSJavier Almansa Sobrino * Errata printing function for Neoverse N2 cores. Must follow AAPCS. 81*25bbbd2dSJavier Almansa Sobrino */ 82*25bbbd2dSJavier Almansa Sobrinofunc neoverse_n2_errata_report 83*25bbbd2dSJavier Almansa Sobrino /* No errata reported for Neoverse N2 cores */ 84*25bbbd2dSJavier Almansa Sobrino ret 85*25bbbd2dSJavier Almansa Sobrinoendfunc neoverse_n2_errata_report 86*25bbbd2dSJavier Almansa Sobrino#endif 87*25bbbd2dSJavier Almansa Sobrino 88*25bbbd2dSJavier Almansa Sobrino /* --------------------------------------------- 89*25bbbd2dSJavier Almansa Sobrino * This function provides Neoverse N2 specific 90*25bbbd2dSJavier Almansa Sobrino * register information for crash reporting. 91*25bbbd2dSJavier Almansa Sobrino * It needs to return with x6 pointing to 92*25bbbd2dSJavier Almansa Sobrino * a list of register names in ASCII and 93*25bbbd2dSJavier Almansa Sobrino * x8 - x15 having values of registers to be 94*25bbbd2dSJavier Almansa Sobrino * reported. 95*25bbbd2dSJavier Almansa Sobrino * --------------------------------------------- 96*25bbbd2dSJavier Almansa Sobrino */ 97*25bbbd2dSJavier Almansa Sobrino.section .rodata.neoverse_n2_regs, "aS" 98*25bbbd2dSJavier Almansa Sobrinoneoverse_n2_regs: /* The ASCII list of register names to be reported */ 99*25bbbd2dSJavier Almansa Sobrino .asciz "cpupwrctlr_el1", "" 100*25bbbd2dSJavier Almansa Sobrino 101*25bbbd2dSJavier Almansa Sobrinofunc neoverse_n2_cpu_reg_dump 102*25bbbd2dSJavier Almansa Sobrino adr x6, neoverse_n2_regs 103*25bbbd2dSJavier Almansa Sobrino mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 104*25bbbd2dSJavier Almansa Sobrino ret 105*25bbbd2dSJavier Almansa Sobrinoendfunc neoverse_n2_cpu_reg_dump 106*25bbbd2dSJavier Almansa Sobrino 107*25bbbd2dSJavier Almansa Sobrinodeclare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 108*25bbbd2dSJavier Almansa Sobrino neoverse_n2_reset_func, \ 109*25bbbd2dSJavier Almansa Sobrino neoverse_n2_core_pwr_dwn 110