1*bff6e602SRyan Everett/* 2*bff6e602SRyan Everett * Copyright (c) 2025, Arm Limited. All rights reserved. 3*bff6e602SRyan Everett * 4*bff6e602SRyan Everett * SPDX-License-Identifier: BSD-3-Clause 5*bff6e602SRyan Everett */ 6*bff6e602SRyan Everett 7*bff6e602SRyan Everett#include <arch.h> 8*bff6e602SRyan Everett#include <asm_macros.S> 9*bff6e602SRyan Everett#include <common/bl_common.h> 10*bff6e602SRyan Everett#include <lsc25_e_core.h> 11*bff6e602SRyan Everett#include <cpu_macros.S> 12*bff6e602SRyan Everett#include <plat_macros.S> 13*bff6e602SRyan Everett 14*bff6e602SRyan Everett/* Hardware handled coherency */ 15*bff6e602SRyan Everett#if HW_ASSISTED_COHERENCY == 0 16*bff6e602SRyan Everett#error "LSC25 E-core must be compiled with HW_ASSISTED_COHERENCY enabled" 17*bff6e602SRyan Everett#endif 18*bff6e602SRyan Everett 19*bff6e602SRyan Everett/* 64-bit only core */ 20*bff6e602SRyan Everett#if CTX_INCLUDE_AARCH32_REGS == 1 21*bff6e602SRyan Everett#error "LSC25 E-core supports only AArch64. Compile with " \ 22*bff6e602SRyan Everett "CTX_INCLUDE_AARCH32_REGS=0" 23*bff6e602SRyan Everett#endif 24*bff6e602SRyan Everett 25*bff6e602SRyan Everett#if ERRATA_SME_POWER_DOWN == 0 26*bff6e602SRyan Everett#error "LSC25 E-core needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27*bff6e602SRyan Everett#endif 28*bff6e602SRyan Everett 29*bff6e602SRyan Everettcpu_reset_prologue lsc25_e_core 30*bff6e602SRyan Everett 31*bff6e602SRyan Everettcpu_reset_func_start lsc25_e_core 32*bff6e602SRyan Everett /* ---------------------------------------------------- 33*bff6e602SRyan Everett * Disable speculative loads 34*bff6e602SRyan Everett * ---------------------------------------------------- 35*bff6e602SRyan Everett */ 36*bff6e602SRyan Everett msr SSBS, xzr 37*bff6e602SRyan Everett enable_mpmm 38*bff6e602SRyan Everettcpu_reset_func_end lsc25_e_core 39*bff6e602SRyan Everett 40*bff6e602SRyan Everett /* ---------------------------------------------------- 41*bff6e602SRyan Everett * HW will do the cache maintenance while powering down 42*bff6e602SRyan Everett * ---------------------------------------------------- 43*bff6e602SRyan Everett */ 44*bff6e602SRyan Everettfunc lsc25_e_core_core_pwr_dwn 45*bff6e602SRyan Everett /* --------------------------------------------------- 46*bff6e602SRyan Everett * Flip CPU power down bit in power control register. 47*bff6e602SRyan Everett * It will be set on powerdown and cleared on wakeup 48*bff6e602SRyan Everett * --------------------------------------------------- 49*bff6e602SRyan Everett */ 50*bff6e602SRyan Everett sysreg_bit_toggle LSC25_E_CORE_IMP_CPUPWRCTLR_EL1, \ 51*bff6e602SRyan Everett LSC25_E_CORE_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 52*bff6e602SRyan Everett isb 53*bff6e602SRyan Everett signal_pabandon_handled 54*bff6e602SRyan Everett ret 55*bff6e602SRyan Everettendfunc lsc25_e_core_core_pwr_dwn 56*bff6e602SRyan Everett 57*bff6e602SRyan Everett /* --------------------------------------------- 58*bff6e602SRyan Everett * This function provides LSC25 E-Core specific 59*bff6e602SRyan Everett * register information for crash reporting. 60*bff6e602SRyan Everett * It needs to return with x6 pointing to 61*bff6e602SRyan Everett * a list of register names in ascii and 62*bff6e602SRyan Everett * x8 - x15 having values of registers to be 63*bff6e602SRyan Everett * reported. 64*bff6e602SRyan Everett * --------------------------------------------- 65*bff6e602SRyan Everett */ 66*bff6e602SRyan Everett.section .rodata.lsc25_e_core_regs, "aS" 67*bff6e602SRyan Everettlsc25_e_core_regs: /* The ASCII list of register names to be reported */ 68*bff6e602SRyan Everett .asciz "imp_cpuectlr_el1", "" 69*bff6e602SRyan Everett 70*bff6e602SRyan Everettfunc lsc25_e_core_cpu_reg_dump 71*bff6e602SRyan Everett adr x6, lsc25_e_core_regs 72*bff6e602SRyan Everett mrs x8, LSC25_E_CORE_IMP_CPUECTLR_EL1 73*bff6e602SRyan Everett ret 74*bff6e602SRyan Everettendfunc lsc25_e_core_cpu_reg_dump 75*bff6e602SRyan Everett 76*bff6e602SRyan Everettdeclare_cpu_ops lsc25_e_core, LSC25_E_CORE_MIDR, \ 77*bff6e602SRyan Everett lsc25_e_core_reset_func, \ 78*bff6e602SRyan Everett lsc25_e_core_core_pwr_dwn 79